TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM

Cross-checking the Samsung SiPh deck obtained on site against HBM and packaging roadmaps

$005930.KS (Samsung Electronics) $TSM $000660.KS | Foundry + Memory + Silicon Photonics Vertical Integration Field Research

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Abstract

TSMC is ahead in the current CPO race. Broadcom’s 102.4 Tbps CPO switch is sampling to customers with TSMC COUPE based optical engines, and NVIDIA’s Quantum-X Photonics has started shipping. Samsung’s reported turnkey CPO roadmap points to 2029.

But that scoreboard ranks switch CPO. Once optics moves past the switch and into the package where the XPU and HBM sit, the basis of competition changes. TSMC makes logic and silicon photonics but does not make HBM itself. Samsung makes all three.

This article tests whether that difference is a real moat or an asset that has not been connected yet. We will look at the OECC 2026 speaker deck obtained on site, the first customer win, the 2.xD packaging disclosed at Nano Korea, and the multi-die yield penalty. The question is not whether Samsung can build CPO faster than TSMC. It is this: when AI’s bottleneck shifts toward memory, who can design HBM and optics together?

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Contents

1. Two Races: What TSMC Grabbed First, and What Hasn’t Opened Yet

2. 10 to 5 to 2 pJ/bit: The Physical Reason the Race Changes

3. Switch CPO and XPU-HBM Optical I/O Are Different Contests

4. Three Chips: Only Samsung Makes Them All

5. What the OECC 2026 Deck Shows About Samsung SiPh

6. The Upside of 2.xD, and the Multi-Die Yield Penalty

7. The Time Gap: TSMC Secured the First Customer References

8. The Reversal Condition: When the Bottleneck Moves to Memory

9. Scenarios + Monitoring

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1. Two Races: What TSMC Grabbed First, and What Hasn’t Opened Yet

Let’s start with the scoreboard as it stands. TSMC has put COUPE (Compact Universal Photonic Engine) into Broadcom’s 102.4 Tbps CPO Ethernet switch, the Tomahawk 6 Davisson, which is sampling to early-access customers.[1] NVIDIA’s Quantum-X Photonics switch has started shipping, and Spectrum-X Ethernet Photonics entered production per a late-May announcement, with CoreWeave, Lambda, and Oracle Cloud Infrastructure among the first adopters (broad availability comes in the second half).[2] Both rest on TSMC’s silicon photonics and SoIC 3D stacking as their core manufacturing base.[3][4] Samsung’s turnkey CPO sits at 2029 on its reported OFC 2026 roadmap.[5][6] On the clock alone, Samsung is behind. We examined that gap, along with the wider field including Tower and GlobalFoundries, in our April piece on Samsung silicon photonics.

Then on July 9, 2026, at Nano Korea, Samsung Electronics Senior Vice President Won-Kyoung Choi pointed to a different board. He said advanced packaging that co-optimizes HBM, logic, and silicon photonics at the system level is the core of the AI era, and that Samsung is developing 2.xD, a packaging scheme that puts all three into a single package.[7] This is not today’s CPO, which pulls an optical engine next to a switch ASIC. It is the next stage: putting optical I/O into the package where the compute chip and the memory live.

https://v.daum.net/v/20260710074609777

Dr. Won Kyoung Choi: https://www.linkedin.com/in/won-kyoung-choi-74775312/

TSMC has logic, silicon photonics, and CoWoS packaging, but it does not make HBM itself. Samsung makes all three. The moment optics enters the package where the XPU and HBM sit, ownership of that third chip becomes a competitive variable.

Still, owning three chips and profiting from an integrated package are separate questions. We will test this including the reason vertical integration is not an automatic moat: the multi-die yield penalty.

2. 10 to 5 to 2 pJ/bit: The Physical Reason the Race Changes

The race migrates from the switch into the package because the energy to move one bit steps down as optics gets closer to silicon. In numbers Samsung Foundry presented at OECC 2026: roughly 10 pJ per bit for pluggable optics on the board, roughly 5 pJ for an optical engine on the substrate next to the switch, and roughly 2 pJ on the interposer right beside the XPU.[8]

What makes this ladder possible is packaging. Moving the optical engine closer to the compute chip shortens the electrical path, and it cuts the signal-conditioning burden spent compensating for board and connector losses. Physics does the energy saving, but the hand that turns that physics into a product is packaging.

The physics behind the staircase is simple. Electrical signals lose more to the channel as distance grows, and beating that loss forces the transmitter and receiver to burn energy on stronger equalization and higher swing. Over distances from centimeters inside a package to a few meters between racks, fiber propagation loss changes little; coupling, optical conversion, and electronic I/O overhead dominate the link budget. So the shorter you cut the electrical leg and the sooner you convert to light, the lower the whole link’s energy budget, and the same data draws an energy staircase depending on where the optics sits.

And the ladder gets its force from the fact that data center power budgets are already at their limits. In an era when a single data center is discussed in gigawatts, the pressure to pull optics toward the package is building fast in the high-bandwidth switch tier. One caution: rather than CPO replacing every pluggable, form factors like pluggables, LPO, and CPO are likely to coexist depending on distance and power budget. NVIDIA is growing its CPO switches and its pluggable ecosystem side by side.[4] The point is not that optical modules disappear. The point is that the place where optics sits walks down the ladder, and the party executing that move changes.

Market projections point the same way. Samsung’s materials put pluggable optics (PO) at over 25% annual growth and co-packaged optics (CPO) at over 150%.[8] Read the growth-rate gap as the speed at which money is moving down the staircase.

Samsung OECC 2026 slide: SiPh platform + transceiver roadmap + pJ/bit + CPO packaging overview

3. Switch CPO and XPU-HBM Optical I/O Are Different Contests

Two adjacent architectures often grouped under the CPO and optical-I/O umbrella must be kept apart.

The present: switch CPO. This pulls the optical engine next to the switch ASIC. Broadcom’s TH6-Davisson and NVIDIA’s photonics switches belong here, and HBM is not a required component.[1][3] The core capability in this contest is stacking the PIC and EIC well (bonding such as SoIC-X) and integrating them into the switch package. This is the contest TSMC leads.

The future: the XPU-HBM optical I/O package. This puts optical I/O into the package where compute and memory live. On the interposer, the XPU or GPU sits in the middle, HBM flanks it, and optical engines (PIC + EIC) sit at the edge. A logic chip, a memory chip, and an optical chip. Three kinds, sitting at one table on the interposer for the first time, and that table is exactly what this article sets out to test. 2.xD is the plan to co-optimize exactly these three in one package.[7] It extends the silicon interposer into a panel-based redistribution-layer (RDL) interposer and grows that into high-capacity system packaging for AI data centers.[7] At this stage the optical engine is no longer a switch component but a subsystem of the compute package, and the advantage goes to organizations able to co-optimize the optics and the package from the earliest design stage.

The whole foundry field is moving in this direction. TSMC is extending COUPE into CoWoS integration, and GlobalFoundries expects silicon photonics revenue of roughly $400M this year (about double last year) and targets crossing $1B on an annualized run-rate basis by the end of 2028.[9] The memory camp is moving too. SK hynix ($000660.KS) is entering this field from three directions.

• Packaging verticalization. Its $3.87B advanced packaging and R&D fab in West Lafayette, Indiana broke ground in April 2026, targeting mass production in the second half of 2028 centered on HBM4E and HBM5, with a 19-trillion-won advanced packaging fab in Cheongju in parallel.[10][11] This is a move to own HBM stacking, screening, and bonding directly.

• Reviewing CPO for the memory system. At its 2025 Future Forum, KAIST Prof. Kyoungsik Yu and SK hynix’s VP of Advanced Package Development presented “CPO technology evolution and its impact on the memory industry,” reviewing how to apply SiPh inside and around the memory system across architecture, design, device, and package.[12]

• A public CPO ecosystem. Korea’s 2026 K-CHIPS slate lists a 200 Gb/s per lambda CPO integrated design and verification platform, and the science ministry’s program runs a 6.4 Tbps opto-chiplet interposer project, with Prof. Younghyun Kim of Hanyang University as sub-project PI on both.[13][14][15] The selected participating companies are not yet disclosed.

Optics entering the package means every camp, foundry, memory, and OSAT alike, converges on packaging as the same destination. Who arrives at that point, and from which direction, draws the map of this cycle. We compared the device-level readiness of the three foundries in [OFC 2026] Part 1 of 5: 300mm SiPh Foundry: Who Is Actually Ready?, and this piece goes into Samsung alone.

That leaves the questions. Buying the three chips from three different companies and bolting them together, versus one company making all three and designing them together from the start: are those different games? If they are, how many companies make all three? And is the answer large enough to show up in Samsung Electronics’ foundry results?

That Samsung has the three axes is something we can confirm shortly. But owning three chips and selling them to a customer as one high-yield package are entirely different problems. Now let’s verify HBM, logic, and PIC one by one, weigh them against TSMC’s time advantage, and fold it all into a single twelve-month verdict at the end.

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