Thanks for sharing！I subscribe to both of you, but neither of you mentioned Alab in CXL or memory wall problem. So I'm wondering: what do you think about Alab?
Great catch. You're right that Astera deserves a spot here. I anchored the CXL section on XConn because of the Marvell consolidation angle, but Leo is the independent leader in CXL memory pooling, and Astera's recent aiXscale move plus its NPO/CPO roadmap make it a clean "electrical connectivity crossing into optics" story. That crossing (Astera, Credo/DustPhotonics, Marvell) is exactly what I want to map next.
Also, I slightly covered them in this article. so if you are interested in them, plesde quickly check it out.
Excellent article. One thing I appreciate is that you distinguish the engineering problem from the investment timeline, particularly around the possibility that Path 3 could remain commercially important longer than originally projected.
I wondered about another layer of uncertainty. Your analysis is primarily at the micro level—technology readiness, supply chains, qualification, and adoption. How much weight do you give to macro variables such as hyperscaler financing, corporate bond markets, or broader capital-market conditions?
The technology may point toward one timeline, but the pace of data-center investment ultimately depends on the ability and willingness of hyperscalers to continue financing these enormous buildouts. Could changes in the cost of capital or infrastructure financing materially extend (or compress) that transition period, independent of the underlying technology?
I'm curious how you think about the interaction between the engineering roadmap and the financial environment.
Could you please explain how I/O chiplet and O-HBM are different paths and not complimentary ones? Doesn't the first one sit inside (the package of) GPU, and the second one connects memory to an optical lane?
Thanks for sharing！I subscribe to both of you, but neither of you mentioned Alab in CXL or memory wall problem. So I'm wondering: what do you think about Alab?
Great catch. You're right that Astera deserves a spot here. I anchored the CXL section on XConn because of the Marvell consolidation angle, but Leo is the independent leader in CXL memory pooling, and Astera's recent aiXscale move plus its NPO/CPO roadmap make it a clean "electrical connectivity crossing into optics" story. That crossing (Astera, Credo/DustPhotonics, Marvell) is exactly what I want to map next.
Also, I slightly covered them in this article. so if you are interested in them, plesde quickly check it out.
https://substack.com/@photoncap/p-194224902
Excellent article. One thing I appreciate is that you distinguish the engineering problem from the investment timeline, particularly around the possibility that Path 3 could remain commercially important longer than originally projected.
I wondered about another layer of uncertainty. Your analysis is primarily at the micro level—technology readiness, supply chains, qualification, and adoption. How much weight do you give to macro variables such as hyperscaler financing, corporate bond markets, or broader capital-market conditions?
The technology may point toward one timeline, but the pace of data-center investment ultimately depends on the ability and willingness of hyperscalers to continue financing these enormous buildouts. Could changes in the cost of capital or infrastructure financing materially extend (or compress) that transition period, independent of the underlying technology?
I'm curious how you think about the interaction between the engineering roadmap and the financial environment.
Could you please explain how I/O chiplet and O-HBM are different paths and not complimentary ones? Doesn't the first one sit inside (the package of) GPU, and the second one connects memory to an optical lane?