FormFactor Q1 2026: SK hynix 29.5%, NVIDIA 10.2%, and the First CPO Test Revenue Signal
FORM: Q1 2026 record revenue, Triton CPO ramp, SK hynix concentration. A single-stock wafer test earnings analysis
Three cycles bent together in a single quarter at FormFactor (FORM) Q1 2026. SK hynix reached 29.5% of revenue (up from 23.3% a year ago), NVIDIA was disclosed as a 10%+ customer for the first time at 10.2%, and 2026 CPO revenue guidance was raised to the high end of the $10-20M range. Revenue hit $226.1M, an all-time record (+32% YoY), with Q2 guidance at $240M. The stock returned +361% over one year, roughly 2.7x the semiconductor index (SMH, +134%). The thesis the market had been pricing in for a year was confirmed in a single quarter’s numbers. This article breaks the earnings into three axes, HBM, CPO, and AI networking, and analyzes the alignment and risk across them.
Contents
+361% in one year, 2.7x the semiconductor index. The market’s thesis confirmed in earnings
Q1 2026 earnings key numbers and 3-axis definitions
Why wafer test sits at the chokepoint of the cycle
Where the real difference begins
Axis 1: SK hynix 29.5%, Korea 35.6%, DRAM +70%
Axis 2: CPO revenue high-end guide, Triton ramp, Keystone integration, COUPE matching
Axis 3: NVIDIA 10.2% first disclosure and Foundry & Logic +30%
3-axis alignment and the next 12 months
References & Sources
1. +361% in one year, 2.7x the semiconductor index. The market’s thesis confirmed in earnings
FormFactor (FORM) returned +361.57% over one year.[1] Over the same period, the semiconductor index (SMH) returned +134% and the S&P 500 returned +14.9%.[1] That is roughly 2.7x the semiconductor index. The thesis the market had been pricing in was confirmed for the first time in numbers when Q1 2026 earnings were released on April 29, 2026.[2]
SK hynix at 29.5% of revenue, NVIDIA at 10.2%, Triton CPO production test guide raised to the high end, and revenue at $226.1M record (+32.0% YoY). HBM, CPO, and AI networking. Three cycles bent together in a single quarter.[2][3][4]
This article takes FormFactor’s Q1 2026 earnings and breaks them into three axes, HBM, CPO, and AI networking, to analyze (a) primary-source verification of each axis, (b) alignment across the three, (c) the dual nature of SK hynix concentration risk and Triton ramp upside, and (d) monitoring points for the next 12 months. This is a single-stock earnings analysis, but at the cycle level, signals from silicon photonics, HBM, and AI networking all land simultaneously.
2. Q1 2026 earnings key numbers and 3-axis definitions
Q1 2026 (fiscal quarter ended 2026-03-28) key numbers are as follows.[2]
Revenue $226.1M, +5.1% QoQ ($215.2M), +32.0% YoY ($171.4M). All-time record.
Non-GAAP gross margin 49.0%, +510 bps QoQ. +250 bps above the high end of guidance.
Non-GAAP EPS $0.56, more than double Q1 2025’s $0.23.
Cash + marketable securities $303.2M ($123.5M + $179.7M).
Q2 2026 guidance: revenue $240M +/- $5M, GM 49.5% +/- 1.5%, EPS $0.61 +/- $0.04.
2026 CPO revenue guidance: $10-20M range high end (approximately $20M).[3]
The three axes are defined as follows.
Axis 1: HBM (memory cycle)
DRAM probe card revenue $82.9M, +70% YoY.[4]
Korea revenue $80.6M (35.6% of total), nearly doubled from Q1 2025’s $43.2M.[4]
SK hynix as a single customer at 29.5% of revenue (up from 23.3% in Q1 2025, +620 bps).[4]
In an HBM4 ramp + DDR5 supply-constrained environment, probe card demand entering priority allocation.[3]
Axis 2: CPO (silicon photonics cycle)
Triton production test platform Insertion 1 entering production-ready stage.[3]
2026 CPO revenue guidance raised to high end ($20M).[3]
Co-developed with Advantest + Tokyo Electron.[3]
Keystone Photonics (optical probing specialist, Germany), acquired in Q4 2025, integration complete.[5][6]
Axis 3: AI networking (compute cycle)
NVIDIA disclosed as a 10%+ customer for the first time, at 10.2%.[4]
Foundry & Logic probe card revenue $111.2M, +30% YoY ($85.3M to $111.2M).[4]
Networking probe card growth cited as the driver of NVIDIA’s 10% entry.[3]
[Figure 1: Q1 2026 key numbers card + 3-axis diagram]
3. Why wafer test sits at the chokepoint of the cycle
Semiconductor wafer test is the step where logic, DRAM, and Flash die are electrically validated at the wafer level before moving to back-end packaging. It sits immediately upstream of bonding and packaging. When bonding capacity scales, probe test capacity must scale with it. This structure was covered in a previous PhotonCap article comparing three wafer test equipment companies (AEHR, FORM, KEYS).[7]
In silicon photonics (SiPh), wafer test is more complex. Standard logic die only need electrical probes touching the wafer, but photonic integrated circuits (PICs) require optical signal measurement alongside electrical. Optical coupling must be precisely controlled at the wafer level, both edge coupling and grating coupling must be supported, and measurement throughput requires automation compatibility (OHT, Overhead Hoist Transport).[11]
CPO (co-packaged optics) adds another layer of difficulty. EIC (electrical IC) and PIC are integrated in the same package, but EIC test equipment (Advantest, Teradyne) and PIC probing equipment (FormFactor, ficonTEC) cover different domains. On a production line, a single platform must handle both.[8] FormFactor’s Triton platform handles PIC probing, with Advantest providing electrical test integration and Tokyo Electron providing wafer handling and production automation in a co-development structure.[3]
The bonding cycle accelerating simultaneously in HBM4 and CPO was covered in a previous PhotonCap article analyzing seven bonding equipment companies including BESI.[9] As bonding capacity scales, probe test capacity must follow. Within that layer, FormFactor as a comprehensive wafer test player is exposed to HBM probe, CPO probe, and Foundry & Logic probe simultaneously.
[Figure 2: Wafer test, bonding, packaging cycle layer diagram. Where the 3 axes enter]
4. Where the real difference begins
Everything up to this point is visible from press releases and IR pages. Record quarter, Q2 guidance at $240M, 2026 CPO guidance at $20M, SK hynix at 29.5%, NVIDIA at 10.2% for the first time. That is the surface of publicly available data.
What matters is that the three numbers are not moving independently. They point to the same supply chain bottleneck. Whether HBM concentration is a direct signal of SK hynix HBM4 ramp rather than just a generic memory cycle, whether the 2026 CPO revenue high-end guide is not just first revenue but positions Triton as a potential production test platform candidate for TSMC’s COUPE production line, and whether NVIDIA’s 10.2% is a one-time networking ASIC order or the starting point of a 12-month share expansion. Those are the questions visible beyond a single quarter’s earnings.
This analysis has two hidden cards.
First, SK hynix 29.5% + Korea 35.6%, a dual-edged structure. Direct beta to HBM4 ramp, but single-customer + single-country risk is simultaneously exposed.
Second, TSMC COUPE-Triton material matching. The material stacks align, but this is not a customer relationship confirmation.
These two are the core variables for the next 12 months of this thesis.
From here, the analysis moves into axis-by-axis data, Bull/Gap/Optionality breakdowns, scenario branches, and monitoring points.
[Figure 3: 3-axis diagram. HBM, CPO, AI networking signals captured simultaneously in one quarter]
So how will these three axes diverge over the next 12 months? The answer is in the axis-level data.
