Disclaimer: This article is a joint publication. The management meeting and investment analysis were prepared by Aurelion Research, and the technical comments by PhotonCap. All content is based on publicly available information and the authors’ notes, and is provided for educational and informational purposes only. Nothing herein constitutes investment advice or a recommendation to buy, sell, or hold any security. Interview responses are paraphrased and do not represent verbatim statements by Lumentum or its management. The authors may hold positions in securities discussed. Readers should conduct their own due diligence before making any investment decisions.

Aurelion Research recently met with Kathryn Ta, Vice President of Investor Relations. We (Aurelion Research) found the conversation very useful, and it gave us a clearer view of the central debate around the stock.

Management meeting and investment analysis by Aurelion Research. Technical review comments by PhotonCap.

Aurelion Research’s Methodology: We independently reach out to company management teams. We do not receive compensation from any company covered. The answers from interviews are based on our notes and have been adapted and presented for clarity. They do not reflect the speakers’ exact words and apply Aurelion’s own thinking. We have selected the sections below that we believe are the most relevant parts of our discussion. We believe all information presented is publicly available. This content is for informational purposes only and is not investment advice or a recommendation to buy or sell any security.

AR: Our view, and it is still an emerging one, is that we are compute constrained as a society and may become more so. As models like Kimi K3, GPT 5.6 and the latest Grok get cheaper per token, elastic demand should push total token consumption higher rather than lower. How does Lumentum think about that? Does it shape capacity expansion or the innovation around data center efficiency?

Answer: Lumentum is at the “plumbing“ layer of the data center, two or three steps removed from any token economics. The number they optimise is power efficiency per bit, and the route to it is higher power lasers. The more bits moved per square area of indium phosphide, the more value delivered. Speed and efficiency are the same problem to them; faster transmission is how joules per bit comes down.

On capacity, they are adding as fast as they can. Two fabs in Japan produce most of the world’s supply of EML lasers, and capacity there is up eight-fold in two and a half years. She offered that as representative of adds made elsewhere. Lumentum now runs five fabs, including a new one starting to ramp that is not yet producing wafers. Every site has had tools added, and several have had the building shell expanded to fit more.

Thoughts:

Efficiency as the optimisation target is the right thing to be chasing. Hyperscalers are working on cost per token and that pressure runs all the way down to the “plumbing”.

The useful part is incentive alignment. Higher power and higher speed make the link more efficient and carry higher ASP at the same time. Lumentum gets paid to build what its customers actually need.

One flag. Eight-fold EML capacity in two and a half years cuts against a pure scarcity thesis. Lumentum is racing to relieve the bottleneck that gives it pricing power. We read that as confidence. Management is building for durable demand.

PhotonCap comment: One engineering caveat on the eight-fold figure. Wafer starts and qualified yield at the newest spec are different numbers. A fab-level capacity multiple does not relieve a 200G per lane shortage one to one, because the binding constraint is yield at the highest power bins, not floor space. This is also why PhotonCap reads the margin question differently. Building capacity takes money. Hitting the top bin takes years of practice. That is why the eight fold number overstates the relief, and why the shortage premium itself is not durable while the margin that survives lives in yield and mix, not in the shortage price.

AR: In the same vein, the consensus view is that we are copper constrained, which should pull optics deeper into the compute architecture. Where do you think we are on that migration between racks, into packaging, and eventually on-chip?

Answer: Today’s co-packaged optics is opportunistic rather than forced. Nvidia deploys it because a faster, more power efficient laser frees up power that can be redirected to the GPUs, which buys system performance. Copper has not run out of headroom yet.

She puts copper hitting the wall in late 2027. That is when the first scale-up CPO deployments arrive, or MPO fiber connectors where customers want a different configuration, driven by link lengths beyond roughly three meters connecting rack to rack. Credo and Broadcom argue six meters is achievable. On paper it is, but the power you would have to push through that copper makes it impractical, so the switch to optical happens around that point regardless.

Thoughts:

Voluntary demand is higher quality demand. That framing helps the bull case. You are buying two S-curves. The opportunistic one is largely played out. The scale-up one has yet to begin.

PhotonCap comment: Agreed on the copper framing. Copper’s limit is not a date. It is a cost curve of reach, speed, and power, and Kathy’s answer to the six meter claims concedes it: doable, but the power bill kills it. The same logic cuts through “voluntary.” A data center runs against a fixed power envelope, so every watt saved on networking is a watt handed to the GPUs, and Nvidia’s own material puts CPO at 3.5x lower power than pluggable transceivers. Copper is not forcing this wave; the power budget is. The scarcer power gets, the stronger this demand becomes. The weak spot is not the voluntariness but that it rides on one company’s architecture choice.

AR: Following on the Broadcom point, there are open questions about the long-term winners in optics and whether they end up being the silicon giants who can acquire an optics platform and integrate it on-chip. As value migrates toward integration, how does Lumentum avoid becoming a quality supplier of a commodity input?

Figure 1: Two Waves of Co-Packaged Optics. Figure: PhotonCap x Aurelion

Answer: Three defences, in her framing.

Competition thins out as power ratings climb. Producing 150 to 400 milliwatt lasers at high volume, high yield and high reliability is difficult, and she does not see many players able to do for Nvidia what Lumentum does today.

Second is survivorship. Lumentum and Coherent are the two companies left standing from telecom, an industry she describes as historically punishing to serve. Lumentum’s laser chip expertise came out of acquisitions and out of meeting reliability requirements the hard way. Coherent is stronger at the systems level and is working to catch up on the component side.

Third, China. New entrants are bringing on large amounts of capacity, mostly in lower power lasers. Lumentum ran the comparison internally and found materially higher yields in its finished transceivers using its own lasers, with better spec uniformity unit to unit and better reliability in testing and in the field

Thoughts:

The power argument is the one we believe. Making high-power lasers is hard and few companies can do it well. But saying you win at the top end also admits you may lose at the bottom. We can live with that, because newer designs need more power, not less.

The telecom history is the weakest argument. Surviving 25 years in a rough industry is real, but it says more about the past than about today. Broadcom and Marvell have plenty of money, and they don’t need the best laser in the world. They only need one that is good enough to put on their own chip.

The China comparison came from Lumentum’s own lab. They tested their lasers against Chinese ones and said theirs came out better. That may well be true. Nobody outside the company has checked it. And Chinese suppliers can close the gap over time. China has shown this so many times.

PhotonCap comment: A product map for readers, because reading Lumentum as an EML company misses half of this article. An EML integrates two things on one InP die: a DFB laser that generates light and an electro-absorption modulator that blinks that light into data. It is a finished modulated source, and today’s 800G and 1.6T pluggable transceivers hang off it. That is the line that is sold out right now. A CW laser is the opposite: it supplies unmodulated continuous light, and a modulator on a silicon photonics chip does the data. That is the external light source for CPO and SiPh transceivers, and the high power line built for Nvidia sits here. In short, EML is today’s cash flow and high power CW is the next mix shift. The figure below shows the structural difference.

Figure 2: Two Ways to Put Data on Light. Figure: PhotonCap x Aurelion

Figure 3: SiPho Light Source Architecture Evolution. Figure: PhotonCap x Aurelion

AR: Looking three, five, even ten years out, and thinking about how compute gets organised as a whole, which of Lumentum’s core competencies prevails? Indium phosphide lasers, MEMS, or coherent optics?

Answer: Indium phosphide laser chip manufacturing first, and she was not close on the ranking. She frames it as architecture agnostic. Customers cannot escape needing photons, and those photons will most likely come from indium phosphide whatever the design. Link counts grow either way, which makes it a high growth market. There is a VCSEL branch on the roadmap if chip-to-chip photonics moves that way, though she still expects indium phosphide to be the answer.

MEMS and optical switching second, and she expects it to become another pillar. It already handles spine replacement and cluster scale-out for Google, and it is a high volume opportunity. Being a systems supplier is new territory, although the telecom wavelength switching business is a more complicated cousin of the same problem. The form factor is much larger than telecom, which raises the reliability and performance bar.

Thoughts:

Her point about not caring which design wins is a good answer to the fear that Lumentum gets cut out. However the industry builds these systems, someone still has to make the light. That job is theirs.

She also brought up VCSELs as a backup plan for chip-to-chip links, without us asking. Worth noting she raised it on her own.

The part she left alone: her two strongest areas carry very different risks. The laser chip business works no matter how the systems are designed. Optical switching does not. It depends on which design wins, and the customer base is thin. Google is the risk there.

PhotonCap comment: “A VCSEL branch on the roadmap” is weaker than the reality. Lumentum has manufactured GaAs VCSELs at consumer volume for smartphone 3D sensing for years, with more than 10 billion emitters shipped per company disclosure. At OFC 2026 it showed that base extended to AI: a 1060nm VCSEL and photodetector 2D monolithic array co-packaged with a host ASIC, targeting slow and wide scale-up protocols such as UCIe and PCIe, with operation above 150°C and channel sparing. So what sits on the roadmap is not VCSEL technology. It is commercial adoption in AI chip-to-chip links. The materials angle matters too. VCSELs live on GaAs, not InP, which means Lumentum holds three light source platforms at once: InP EML, InP high power CW, and GaAs VCSEL. That is a stronger architecture hedge than the paraphrase suggests.

Company Introduction: A Different Method of Connectivity

Lumentum is a photonics company that designs and manufactures hardware which senses, generates, switches, and modulates laser light. Lumentum’s core competency is fabricating semiconductor lasers on indium phosphide, a compound semiconductor that emits light efficiently where silicon, an indirect bandgap material, does not. This capacity is directed at numerous end markets, most prominently AI and data centers. Lumentum describes themselves as an industry leader in providing optical and photonic products. Their demand is driven by the expansion of networking capacity for cloud service, AI compute, and data center interconnect.

Inside a data center, countless GPUs communicate with each other to efficiently compute, sending large quantities of data to one another, which is traditionally done with copper wire. However, copper wiring grows energy inefficient at large lengths and high speeds, forcing a shift into optical solutions. Photonics, conversely, converts electrical signals into light and sends them over fiber. Lumentum makes the chip inside this light-based connection in the form of an EML (electro-absorption modulated laser). An EML pairs a continuous-wave DFB laser with an electro-absorption modulator built alongside it on the same chip. The laser itself runs continuously, and the modulator gates that light on and off billions of times per second to encode the data. Keeping the laser at constant output and modulating externally avoids the wavelength drift, or chirp, that comes from switching a laser directly, which is what allows an EML to hold signal integrity at high speed and over distance. It is also what makes an EML exceptionally difficult to manufacture.

Figure 4: Inside an Optical Transmitter Module. Figure: PhotonCap x Aurelion

Figure 5: Lumentum EML product family. Source: Lumentum

They currently hold roughly 60% of the EML market, and are one of the only, if not the sole, supplier of the highest speed version at volume. Revenues have nearly doubled year over year, with margins swinging positive. Nvidia has invested $2Bn in Lumentum convertible preferred stock and has a standing purchase agreement with them. Lumentum has moved upstream from a component vendor to becoming vertically integrated into a components and systems company, with components (laser chips) accounting for roughly 65% of revenues, and systems (transceivers, optical switches, MEMS) accounting for the remaining 35%.

Figure 6: One Company, Four Light Platforms. Figure: PhotonCap x Aurelion

Implications for the AI Trade

Investor sentiment about the AI trade has largely been centered on compute, principally GPUs and memory. However, a cluster of GPUs borders on useless if they cannot communicate with one another quickly and efficiently, because at the scale model training and inference run, a single chip is massively insufficient for a model. Lumentum satisfies this need, connecting GPUs with light. Lumentum’s recent performance serves as a signal for the broader infrastructure buildout, in that their revenues have grown significantly both through higher volume, and elevated ASP with a mix-shift to 200 gig-per-lane speeds. This tells us:

1) The compute bottleneck is not solely concentrated in memory. There are shortages in areas that are multiple orders of magnitude removed from direct token generation.

When thinking about a cluster of GPUs dedicated to AI, the two high-level jobs are compute, and intra-GPU communication. The numerous GPUs that define the cluster need to remain in constant communication to split compute across them. The first two or so years of the AI trade centered around the actual computation needs, with the first constraints being GPUs, then memory, and then power and advanced packaging. While some of these bottlenecks, mainly memory, still persist, sentiment has since moved to a new constraint. Specifically, much of that sentiment has shifted to optics in recent months. Lumentum signals that this bottleneck is real and possibly persistent because its laser chip business has grown both in volume and pricing, which shows that demand is outpacing the physical ability to manufacture the product. Lumentum is the leading provider of indium phosphide chips, which is considerably more difficult to work with than silicon. Lumentum is currently optimizing the number of bits you can transfer per square area of indium phosphide. In an ordinary market, capacity expansion almost always leads to lower ASP. However, Lumentum, by optimizing for more complex and efficient optical technologies, may actually continue to see ASP increase as customers mix shift to newer chips. This is a bullish signal for the AI infrastructure buildout and hyperscaler capex.

2) The optics thesis depends on compute domains growing. It is not fully dependent on a large-scale copper shortage.

Common sentiment around optics use stipulates that copper eventually fails to function or runs out of supply, which then forces migration over to optics, making demand robust. We see this, however, as a slightly misguided mechanism. Jensen Huang, CEO of Nvidia, framed copper as being used for scale-up, and photonics for scale-out, and Broadcom has said that optical scale-up is not quite there yet. This is despite Nvidia’s vast investments in Lumentum and Coherent, while also saying there is a need for copper capacity. With the ongoing rollout of Nvidia’s Vera Rubin GPUs and CPUs, we may begin to see a deepening of constraints outside of just distance or power per meter. Rubin relies on bi-directional signaling to reach its bandwidth targets, and bi-directional signaling over copper degrades substantially at 448G per lane. There is an unknown time-to-market for 448G per lane copper, but optics can scale along modulation, fiber count, and wavelength multiplexing. This means that Kathy’s response to six-meter copper claims is actually directed more at a cost curve based on engineering capabilities rather than a physical wall.

There is a durable source of demand for optics based on the growth of compute domains, meaning the number of GPUs that must operate as one coherent unit. These domains are rapidly outgrowing what copper can serve. Nvidia has begun moving from 72 GPU domains toward as many as 576 by 2027, and copper is already confined on an NV72 rack. Once a domain encompasses multiple racks, linking must be optical regardless of copper’s current efficiency. Thus, the optics thesis necessitates that AI systems continue scaling, not only that copper hits a wall or that 448G copper becomes unattainable. So, as CPO is anticipated to scale up in FY27 or FY28, it can do so in parallel with copper and still see commercial success.

3) If intelligence begins to commoditize and open source models continue to improve, value migrates away from frontier labs into infrastructure, but within infrastructure it does not concentrate evenly.

The cost per unit of model intelligence is persistently decreasing, especially with new open source releases like Kimi K3 and Grok 4.5. If demand for tokens is elastic, which we posit it is, then consumption rises faster than price falls. So, more competitive cheaper-per-intelligence models increase aggregate demand for compute while moving margins away from frontier models. Models would, in this case, become increasingly commoditized, with high competitive pressure and low switching costs. Combined with open-weight models compressing pricing, value migrates toward layers that depend on physical scarcity. This is a widely held conclusion, however, it is normally left at a high level.

Infrastructure is a multi-layer portion of the value creation chain, including power generation and grid capacity, chips, interconnect, and more. Leading edge foundry capacity is arguably the most scarce layer in the entire supply chain, with TSMC being effectively the sole frontier supplier. HBM is also constrained across 3 global suppliers, and behaves as a commodity, with more capacity expected to come online within the next 18 to 24 months. Optical and photonic components are currently in a similar position to memory in terms of viable suppliers and industry barriers to entry, given the underlying material science in indium phosphide fabrication and reliability requirements. However, training is the most communication intensive workload, and the way that optics have traditionally traded is around training economics. Inference is less network intensive, or at least has been historically, so a mix shift toward inference does not translate to a 1:1 demand for optics. But, as inference architecture evolves, this gap may close with things like longer context windows, more intense routing, disaggregated prefill and decode, and higher agentic usage. Inference is also more geographically distributed, which will drive more data center interconnect, regardless of cluster-to-cluster linkage. Optics at large are insulated from model commoditization, because they benefit from bits moved rather than tokens generated across infrastructure.

PhotonCap comment: This gap is already closing. The joint inference solution AMD and Cerebras announced in July is the live example. Helios handles the front half, reading the prompt, and Cerebras handles the back half, generating the answer, so work in progress crosses a network between two machines. What that link is made of has not been disclosed. So this is evidence that inference moves a lot of data, not evidence of any vendor’s revenue. PhotonCap covered the architecture in Same Split, Opposite Directions: Where NVIDIA and AMD Cut the Rack Decides Where Optics Gets Paid, and the data center to data center demand in this paragraph is the axis covered in One Layer Below SemiAnalysis’s Meta Map.

4) Chinese competition is unlikely to be a factor in the near term, though this is the point on which we hold the least conviction.

Chinese competitors do persist, and their technologies currently lag on yield and high-power production. As compute demands skew in favor of energy efficiency, using potentially unreliable Chinese hardware is not particularly viable. Furthermore, with strict import restrictions and bans among US companies demanding compute, Chinese hardware is unlikely to see significant uptake over domestic producers in the near term. We hold this view with less conviction than the three above, and treat it as a live risk rather than a settled question. The evidence supporting Lumentum’s yield advantage is entirely management’s own internal comparison, and Chinese EML production is progressing faster than the near-term view assumes. We set out that counter-argument in the bear case below.

PhotonCap comment: The actual technical point deserves sharpening. The moat is not peak power. It is qualified usable power at operating temperature, multiplied by spectral quality, reliability, and high volume yield. Four terms make the picture concrete. RIN is the small flicker in a laser’s output; with PAM4, which encodes data in four brightness levels, too much flicker makes the receiver confuse levels. COD is catastrophic optical damage, the failure mode where a laser’s own light burns its output facet, and it is the wall you hit first as power climbs. SMSR measures how cleanly the laser emits one wavelength versus stray ones. FIT counts failures per billion device hours; with millions of lasers in a data center, even a slightly high FIT means something dies every day. The point is this. Headline specs are what challengers close first. Distribution tails, noise, and lifetime statistics close last, because they take volume learning and years of field data rather than design. Lumentum’s claimed edge sits exactly there, and for the same structural reason it cannot be externally verified yet.

Bull and Bear Debate

Figure 7: The Lumentum Debate, four bull arguments and five bear arguments with evidence status. Figure: PhotonCap

LITE stock currently sits about 20% below its all-time high. Sellside coverage is roughly split, with shops like TD Cowen cutting its price target to $800 from just over $990, while UBS re-affirmed a hold and Citi reiterated a buy with a $1,100 price target, opening a catalyst watch. Other price targets range from $900 to $1,400 on the sellside. Before looking at the bull and bear cases, it is worth understanding that most of the photonics supercycle has been realized and played out, as photonics stocks at large have seen earnings increases and re-rates over the past 52 weeks. So, the relevant debates revolve largely around the future state of shortage, pricing, and CPO scale-up.

The Bull Case

Folks long Lumentum tend to believe:

1) The shortage is worsening and will continue to do so as compute scales up

Components and laser chips are effectively sold out, as are most chips, while wafer fabs take years to come on line. Management has described this supply and demand imbalance as roughly 30% greater demand than is physically suppliable, which is forcing premium pricing in the near to mid term, and full wafer allocation. Japanese wafer fab capacity is at a premium and fully allocated, while laser chip shipping has more than doubled in volume year over year. A McKinsey study also projects 800G transceiver production falling short of demand by about half in FY27, with shortfalls extending through 2029.

2) Pricing is contractually locked in and skews in favor of Lumentum through FY27

All EML capacity is locked in long-term agreements (LTAs) through FY27, and customers coming back for more than their LTAs cover must pay premium prices, while customers who do not sign LTAs risk losing their entire allocation of supply. General analysts expect double digit price increases in 200G EMLs in FY26 given the lack of second source supply.

3) Optical scale-up is not modeled into short-term consensus and is a second S-curve into which you can buy

LITE’s current business is predicated on scale-out, but management describes scale-up as a game changer that would expand their TAM. They expect first scale-up shipments for CPO in late ‘27. This was also confirmed by what Kathy told us on our call. The bulls see this as incremental TAM on top of a business that is already sold out of supply capacity.

4) CW lasers for CPO are ramping harder than consensus models

This thesis point rebuts the chip selloff in June, and the argument originates with Global Semi Research, who published a direct response to the SemiAnalysis note on June 10. Their supply-chain checks put Nvidia’s guidance to Lumentum and Coherent for high-power continuous-wave lasers at roughly 40MM units in January, rising to roughly 100MM by April and May. That pulls demand forward and back-solves to CPO switch shipments of roughly 200,000 to 300,000 in 2027, scaling toward 600,000 to 800,000 in 2028. It also lines up with TSMC’s COUPE (Compact Universal Photonic Engine) plan. These are channel figures rather than company disclosure, so we weight them accordingly.

The Bear Case

1) Coherent’s 6 inch wafer is a deeply underappreciated competitive threat

Coherent’s competitive product is its 6 inch indium phosphide wafer line. By switching from 4 inch to 6 inch wafers, Coherent produces roughly 2.25 times the usable area per wafer, yielding more laser die at a lower cost per die. Lumentum still runs 4 inch wafers and is trying to catch up. If Coherent’s 6 inch yield closes the gap on Lumentum’s 4 inch performance, this deeply undermines Lumentum’s pricing power. Lumentum even framed its own competitive advantage as bits per square area of indium phosphide, so a competitor with more than twice the usable area per wafer makes direct headway on that metric. Coherent’s indium phosphide lasers are also sold out through 2027.

2) Timing CPO shipments is a risk because they may get delayed

SemiAnalysis published a report to institutional clients on June 9, 2026, arguing that scale-out CPO shipments would be revised down through FY27 and push scale-up to FY29. This implies that the photonics bottleneck trade is over-crowded and disconnected from reality, which caused a relatively violent selloff in June and is one of the most monitored aspects of the bear case. They stated that CPO output is driven by a single ASIC that is very limited, and that ASIC integration is difficult with challenging underlying economics in its current state.

PhotonCap comment: This risk needs splitting by cause. If CPO slips on ASIC or packaging integration while bandwidth demand keeps growing, demand does not disappear. It stays in pluggables longer, and pluggables are EML intensive, which is the line that is sold out today. An integration driven delay pushes CW and ELSFP revenue out while extending the EML cycle. If the delay instead comes from a broader AI capex slowdown, both architectures get hurt. There is also the other side of the same coin. The cannibalization question the call sidestepped, whether CPO eats into the roughly 35% of revenue that is transceivers and systems, flips into a cushion in the delayed CPO scenario. The ladder below shows why: CPO is one rung, and a delayed rung keeps traffic on the rung beneath it. The June selloff punished the whole optical complex without this distinction, which PhotonCap covered in There Is No Such Thing as a ‘CPO Stock’.

Figure 8: The Optical Architecture Ladder. Source: PhotonCap, DSP, LPO, NPO, CPO: The Four Optical Architectures

3) Chinese EML production is progressing fast, and may soon catch up with domestic production qualit

Chinese companies, like Zetta Semiconductor, announced mass production quality EML systems across a variety of types and wavelengths in late 2025. This shows that there are foreign players that have the production capacity and specialization to play in the photonics market. However, getting past US regulatory structures and import restrictions will be difficult. The main battleground for these technologies will likely be in the EU among non-US companies.

PhotonCap comment: Zetta no longer fits either box, not the low power dismissal and not the imminent catch-up call. On public record it announced a mass producible 100G PAM4 EML at OECC 2025 and followed with a 200G per lane device at ACP in November 2025. Device level performance deserves to be taken seriously now. The open question is exactly the logic in the PhotonCap comment above: can it hold the full spec distribution across operating temperature and lifetime, and do unit-to-unit variation and noise behavior like RIN survive hyperscale qualification. That gets proven by years of volume data, not by announcements. PhotonCap covered how profits split between chips and modules in the Chinese optical ecosystem in Chinese Optical Modules Own 7 of the Top 10 Seats.

4) Lumentum capacity should come online in 2028, which may hit a different market

Two new sources of indium phosphide capacity are coming, and they are separate projects. The first is Greensboro, North Carolina, bought from Qorvo and being converted from gallium arsenide to indium phosphide as Lumentum’s fifth indium phosphide fab. Management guided revenue contribution to roughly six quarters out from the May call, which puts it in late 2027 at the earliest. The second is the new U.S. facility funded alongside the Nvidia investment, which is a ground-up build rather than a conversion. However, capacity commitments are being baked into current contracts at peak pricing against volumes that do not arrive for at least another 18 months. LITE is expanding EML production by 40% annually, but if volume growth decelerates by the time new capacity comes on line, Lumentum’s operating leverage will work against them on a substantially larger operating asset base.

5) Customer concentration is high, and they are deeply entangled with Nvidia

Two LITE customers accounted for 26% and 12% of revenues in fiscal Q3 2026. Nvidia is a large customer, shareholder, and owner of rights to future capacity. These roles are fundamentally unaligned, and its position as a buyer is economically larger than its investment stake, so its incentives skew toward price discipline rather than support. Capacity rights also cause tension among other customers whose supplier is entangled with a competitor that has claims on output.

PhotonCap comment: Concentration is a snapshot. Addressable demand is wider. Every camp pursuing CPO needs high power light. AMD’s rack scale expansion creates EML, CW, and pluggable demand. Broadcom is a potential customer and at the same time a platform competitor with its own laser sources. Marvell can be a buyer, an ecosystem partner, and an integration layer competitor all at once. Absent a disclosed design win, though, these are demand paths, not confirmed customers. The reverse direction is also on the public record: second sourcing is in progress, not a hypothesis. NVIDIA’s technical blog names three ELS vendors, Lumentum, Sumitomo, and Coherent. The same day Lumentum got its $2B, Coherent got an identical $2B. Coherent’s OFC 2026 release formalizes its 6 inch InP ramp and a 400mW CW laser, and AAOI announced sampling of a 400mW narrow linewidth laser in December 2025. The time axis is what matters. Competing capacity lands outside the FY27 LTA window, which is exactly where the 2028 capacity argument above picks up.

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Disclaimer: This article is a joint publication. The management meeting and investment analysis were prepared by Aurelion Research, and the technical comments by PhotonCap. All content is based on publicly available information and the authors' notes, and is provided for educational and informational purposes only. Nothing herein constitutes investment advice or a recommendation to buy, sell, or hold any security. Interview responses are paraphrased and do not represent verbatim statements by Lumentum or its management. The authors may hold positions in securities discussed. Readers should conduct their own due diligence before making any investment decisions.

Abstract

Kimi K3, released July 16, is a 2.8 trillion parameter MoE model that activates 16 of 896 experts per token. Its active parameter count is estimated at roughly 50 to 60B (unofficial estimate, technical report not yet published). The trading day after TSMC reported a 77.4% jump in quarterly net income, its Taiwan-listed shares fell 7.3% and the US ADR $TSM fell 2.8%. K3 was less the sole cause of that selloff than a catalyst that amplified AI capex caution already in place. This article works through three calculations from K3’s spec: the memory its weights require (a theoretical floor of about 1.4TB at MXFP4), a KV cache baseline for its 1M token context, and the widening gap in large open-weight MoE models, where total parameters grew about 4x in 19 months while active parameters grew around 1.4x. The conclusion the public spec supports: K3 cuts per-token compute while raising memory and communication load at the same time. The article then maps that load to five supply chain exposure points: die, package, rack, campus, and test. This article is fully free.

Data cutoff: July 20, 2026. K3’s API and architecture overview are public, but the full weights and technical report are not yet released. Some figures, including the 50 to 60B active parameter count and the actual serving footprint, are independent estimates. Moonshot has stated the full weights will be released by July 27. License terms and exact configuration will be updated here once they are public.

Net Income Up 77.4%. The Next Trading Day, Down 7.3%

The trading day after reporting a 77.4% year-over-year jump in quarterly net income [1], a company’s shares fell 7.3% on the Taiwan exchange. That company was TSMC [2]. The same day, the US ADR $TSM fell 2.8% (NYSE close, 2026-07-17), SoftBank dropped 9%, the Nasdaq 100 slipped 1% intraday, and NVIDIA ($NVDA) briefly handed the largest market cap spot to Apple during the session [3].

No single cause explains that selloff. Caution around AI capex and valuations had been building for a while, and the earnings themselves, strong as they were, left cost concerns on the table [2]. But there is little disagreement that Kimi K3, the open model Moonshot AI released on July 16, was the catalyst that amplified it.

The catalyst’s logic is simple: if a frontier-class model becomes available through a low-cost API or downloadable open weights, the case for hardware spending appears to weaken. It is a familiar argument. The same selloff played out in January 2025 with DeepSeek.

And we already know how that experiment ended.

Summary: the logic behind the K3 correction is a rerun of the DeepSeek shock. That experiment already produced a result once.

The Experiment We Already Ran in January 2025

The selloff logic during the DeepSeek shock was “cheaper models mean lower infrastructure spending.” That equation never showed up in hyperscaler capex guidance afterward. You cannot claim the price drop directly caused spending to rise, but the direction was, at minimum, not the one the selloff priced in. What got cheaper was the model, not the infrastructure that runs it.

There is already a framework piece that organizes this structure: ’s analysis of open models and semiconductor demand. Its conclusion, in one line: open models do not shrink the hardware market. What gets compressed is the frontier model developer’s premium, and value moves toward hyperscalers and the semiconductor infrastructure underneath them.

Damnang’s Substack

The Open-Source AI Era: Will Hyperscalers Keep Buying Chips?

Semiconductor investors have had a run of unsettling news…

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9 days ago · 39 likes · 3 comments · Damnang

This article takes that frame as given. What it adds is a different question, worked out in numbers. What does one model like K3 physically require, and how much? And if models like this keep coming, where in the supply chain does that requirement land?

First, let’s separate what the official spec confirms from what is still an estimate.

Calculation 1: 1.4TB of Weights, and That Is the Floor

Here is what Moonshot’s official material confirms: 2.8 trillion total parameters, 16 of 896 experts activated per token, a 1 million token context window, and quantization-aware training from the SFT stage using MXFP4 weights with MXFP8 activations [4]. The active parameter count per token is not in the official material. estimates it at roughly 50 to 60B [8]. A simple 2.8T x 16/896 calculation produces about 50B, but that arithmetic assumes the parameters are spread uniformly across routed experts. In reality the 2.8T total also includes always-active attention, embeddings, routing, and shared components, so the correct expression is common parameters plus 16/896 of the routed-expert parameters. Because Moonshot has not disclosed the split between common and routed-expert parameters, the exact active count cannot yet be calculated from the official specification (unofficial external estimate).

Start with the memory the weights require. A naive conversion at 4 bits per parameter gives 2.8T x 0.5 bytes = about 1.4TB. That number is not a conservative estimate. It is a theoretical floor: raw payload with scale metadata, alignment, and communication buffers stripped out. The actual serving footprint is larger. At FP8-class precision, the figure is 2.8TB.

Put that against the nominal capacity of the current top accelerator and the scale becomes visible. NVIDIA’s Blackwell Ultra (B300/GB300) carries 288GB of HBM3E per GPU [7]. Dividing nominal capacity alone, 1.4TB is 5 GPUs’ worth and 2.8TB is 10. That is not a minimum deployment count. KV cache, activations, and parallelism overhead stack on top, and as we will see, Moonshot itself recommends a much larger configuration. Scaled to a GB300 NVL72 rack of 72 GPUs, nominal rack HBM is 72 x 288GB = about 20.7TB [7], and one copy of K3’s FP8-class weights occupies more than 13% of it as a resident.

Compare with the previous generation and the slope shows. Kimi K2 was 1.04 trillion total parameters [5]. Total parameter count grew 2.7x in twelve months.

This article’s title comes from here. The routed experts selected per token are 16 of 896, a ratio of 1.8% [4]. That ratio does not equal 1.8% of total FLOPs. Attention, the router, and shared paths keep their own compute. But the structure is clear. The model limits the active parameter set to an estimated 50 to 60B per token, yet because the router can call any expert on the next token, a high-throughput serving system needs all 2.8T weights reachable at low latency, in accelerator memory or a tier close to it. Offloading or caching some experts elsewhere is possible. The price is latency and throughput.

A library analogy helps. Active parameters are the books open on the desk for this one token. Resident weights are every book that has to stay on the shelves. Only 16 of the 896 librarians are working, but since nobody knows which one the next visitor will ask for, all of them have to sit in the waiting room. Compute cost tracks the 16 at work. Memory cost tracks the size of the room.

Figure 1: The K3 asymmetry, 16 of 896 routed experts activate per token while the full 2.8T parameter set must remain rapidly accessible

Investment read: 16-of-896 routing sparsity limits the active parameters per token, but the serving system still needs low-latency access to all 2.8T weights. With actives growing far more slowly than totals, the bottleneck’s center of gravity expands from compute alone into a system problem spanning memory capacity, bandwidth, and interconnect.

Weights, though, are half the serving memory story. The other half is created not by the model but by usage.

Calculation 2: KV Cache, the Second Memory That Usage Creates

K3’s context window is one million tokens [4]. Context carries a memory cost: the KV cache, which stores the attention keys and values of every token the model has read.

One thing to be clear about first. The calculation below is not K3’s actual KV memory. It is a counterfactual baseline: what K3 would look like if it were a standard GQA attention model. In a standard architecture, KV cache size is roughly 2 (K and V) x layers x KV heads x head dimension x context length x precision. Assume a typical frontier-scale configuration (author estimate: 60 layers, 8 GQA KV heads, head dimension 128, FP8) and a single 1M token session comes to about 123GB. That is over 40% of one B300’s nominal HBM, occupied by a single user’s conversation.

K3’s actual memory requirement is likely lower than this standard-GQA baseline. K3 is a hybrid attention design combining KDA (Kimi Delta Attention) with Gated MLA, and KDA exists precisely to cut this cost [4]. The size of the reduction cannot be calculated until the layer mix and state structure are disclosed.

Line up what the labs chose and the direction converges. DeepSeek compressed the KV cache with MLA [6]. Moonshot rebuilt attention itself with KDA. MoE sparsity cuts per-token compute, and MXFP4 quantization-aware training cuts bits per parameter [4]. Nearly every frontier architecture improvement of the past two years points the same way: not adding FLOPs, saving bits. Watch where the labs concentrate their engineering and you can read where the bottleneck sits.

KV has one more property that weights do not. Weights are a fixed cost per serving replica. KV and state are a variable cost that grows with active sessions and context length. They scale with usage, not with the number of models. The pattern so far: each time compression lowered the per-session cost, longer contexts and more concurrent sessions filled the space it opened. There is no guarantee the pattern holds. But what happened right after K3’s launch, as we will see below, was at least not the opposite.

Summary: under a standard GQA counterfactual, one 1M token session is about 123GB (author estimate). K3’s actual figure is likely lower, but the reduction cannot yet be quantified. Still, the fact that architecture work keeps converging on memory tells you where the bottleneck sits.

Calculation 3: Totals Grew 4x. Actives Grew About 1.4x

How many more models like this are coming? The sample here is not all open models. It is the largest open-weight MoE snapshot at each point in time. Dense models and small MoE are not in this sample.

December 2024, DeepSeek-V3: 671B total, 37B active, a 5.5% activation ratio [6]. July 2025, Kimi K2: 1.04T total, 32B active, 3.1% [5]. July 2026, the same weekend Moonshot shipped K3 at 2.8T, Alibaba introduced its 2.4 trillion parameter Qwen3.8-Max-Preview with an open-weight release planned [9]. Take K3’s active parameters at Ken Huang’s 50 to 60B estimate [8] and its activation ratio is 1.8 to 2.1%.

Over 19 months, total parameters grew 4.2x while active parameters grew 1.35 to 1.62x on the estimate range. The activation ratio walked down from 5.5% to 3.1% to around 2%. Back in the library, the shelves grew 4.2x over 19 months while the librarians on duty grew about 1.4x. Each generation grows the active parameter set far more slowly than the total parameter count, while the parameter set that must remain reachable keeps growing. This gap is the most important chart in this article.

Figure 2: Total vs active parameters, selected large open-weight MoE snapshots, Dec 2024 to Jul 2026

Three forces push the trend: compute constraints, competitive density, and self-hosting.

Compute constraints first. Sparsity is the cheapest way to scale model size in a compute-scarce environment. Reuters notes that US export controls have made access to computing power a key constraint for China’s AI developers [9]. When FLOPs are hard to secure, a sparse MoE that runs a bigger model on the same compute is less a choice than a forced direction. What the controls aimed to block and where demand actually grew sit in different places. Squeeze the compute, and the architecture grows toward memory.

Competitive density. It is no accident that Alibaba shipped a 2.4T model the same weekend K3 arrived [9]. Everyone from the large platforms down to startups like DeepSeek and MiniMax is in the same race [3], and a race on total scale has no incentive to stop.

Self-hosting. Moonshot has stated the full weights will be released by July 27 [4]. There is no official license announcement yet, so the actual self-hosting terms need confirming after release. If the weights land as planned, the serving infrastructure demand that has so far lived inside frontier labs gets recreated in enterprises, governments, and sovereign clouds. Everything that closes the gap between “can download a 1.4TB model” and “can run it” is hardware spending.

And just before this article went out, the most direct data point on this logic arrived. On July 19, Moonshot paused new subscriptions, saying K3 demand had approached the limits of its existing clusters within 48 hours, and allocated available compute to existing paid users [9]. A signal pointing in the exact opposite direction of “cheap open models reduce infrastructure demand,” and it came from the company that built the model.

Summary: totals up 4.2x, actives up around 1.4x. As long as that gap holds, incremental demand shifts disproportionately toward memory capacity, bandwidth, and interconnect. Not away from compute, but beyond compute alone. And the company that built the model paused new consumer subscriptions over capacity constraints three days after launch.

Where the Bottleneck Shows Up: Die to Test

Break this demand down by supply chain exposure point and five layers remain. This is an exposure map, not a time sequence. Capacity reservations, HBM production, rack networking, DCI, and test equipment orders all move in parallel, each on its own lead time. PhotonCap has covered each layer separately, so each one links to the relevant analysis.

1. Die: foundry capacity. More resident bits mean more wafers for the DRAM dies and the base and logic dies under every HBM stack, and as optical interconnect moves into the package, dedicated silicon photonics capacity. Capacity is a resource with lead times measured in years, so the land grab starts before the bottleneck makes headlines. What happened at the foundries before the laser shortage became news: Everyone Saw a Laser Shortage. The Money Went to the Foundries First.

2. Package: HBM. As K3’s arithmetic shows, the variable is not price per bit but total bits shipped. And the memory wall is not only a capacity problem. Bandwidth, latency, and the energy cost of moving those bits can constrain serving economics even when nominal capacity is enough, which is why growing capacity and growing bandwidth pull on different supply chains. Why HBM demand and optical memory pooling diverge: The More Anthropic Buys Micron HBM, the Faster Optical Memory Pooling Arrives

3. Rack: scale-up interconnect and InP. With 896 experts split across accelerators, the router’s per-token expert calls generate traffic between accelerators. Moonshot itself recommends deploying K3 on supernodes of 64 or more accelerators, noting that inference efficiency benefits from larger high-bandwidth communication domains [4]. That is a structure where scale-up domain bandwidth decides serving economics. Optics enters at the distances copper cannot reach, and the more optics wins, the more InP sells: The More Silicon Wins, the More InP Sells

4. Campus: coherent DCI. If self-hosting and inference diffusion actually spread across multiple sites, traffic between sites grows with them. Self-hosting that stays inside a single datacenter or a single cloud gives this layer limited benefit. The switch that turns this layer on is multi-site distribution. Why scale-across is a different market with a different frame: One Layer Below SemiAnalysis’s Meta Map

5. Cross-cutting: test and measurement. Test is not a final step. It runs across wafer, die, package, module, and link manufacturing at the same time. Whoever wins the four layers above, every new HBM stack and every new optical link ships only after it passes test: Compute Is the New Oil. So Who Builds the Drilling Rigs?

Investment read: the five layers are parallel exposures, not a sequence. The land grab shows first where lead times are longest (foundry capacity), and volume shows first where demand tracks usage directly (HBM, scale-up optics).

Closing: The Two Things This Correction Is Discounting Together

Damnang explains why open models do not destroy semiconductor demand. Kimi K3 shows, in its spec, where that demand goes. A structure that limits the active parameter set to an estimated 50 to 60B per token while requiring access to 2.8T weights. A total-versus-active gap that widens every generation. And a capacity shortage notice three days after launch.

The conditions that would weaken this picture belong on the record too. Expert offloading and caching working better than expected, reducing what must sit in accelerator memory. Another step up in quantization density. Self-hosting delayed by concentration in cloud APIs. KDA-class architectures cutting far deeper against the baseline than assumed. The breakdown of K3-driven demand into listed-company exposure across HBM, InP light sources, coherent DCI, and test equipment, along with the indicators to watch for each, continues in the four pieces linked above.

Even granting those conditions, this correction is discounting the model layer’s premium compression and the demand for HBM, optical interconnect, and foundry capacity at the same multiple. I do not think those two point the same way.

The fiercer the competition gets at the model layer, the more the hardware layer sells to whoever wins.

Acknowledgment

This article’s starting point is Damnang’s analysis of open models and semiconductor demand.

Damnang’s Substack

The Open-Source AI Era: Will Hyperscalers Keep Buying Chips?

Semiconductor investors have had a run of unsettling news…

Read more

9 days ago · 39 likes · 3 comments · Damnang

References & Sources

[1] TSMC, “TSMC Reports Second Quarter EPS of NT$27.25”, Jul 16, 2026.

[2] Bloomberg, “Chip Stock Rout Deepens as TSMC Selloff Drives Taiwan Correction”, Jul 17, 2026.

[3] Fortune, “Markets experience new DeepSeek shock after Moonshot AI releases Kimi K3”, Jul 17, 2026.

[4] Moonshot AI, “Kimi K3: Open Frontier Intelligence”, Jul 16, 2026.

[5] Moonshot AI, “Kimi K2: Open Agentic Intelligence”, arXiv:2507.20534, first submitted Jul 2025.

[6] DeepSeek-AI, “DeepSeek-V3 Technical Report”, arXiv:2412.19437, Dec 2024.

[7] NVIDIA, “Inside NVIDIA Blackwell Ultra: The Chip Powering the AI Factory Era”, NVIDIA Developer Blog, 2025.

[8] Ken Huang, “Demystifying Kimi K3: The Three Algorithms Behind the #1 Frontend Coding Model”, Substack, Jul 18, 2026.

[9] Reuters, “China’s Moonshot pauses Kimi subscriptions amid hot demand, IPO push”, Jul 20, 2026.

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Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

The copper in NVL72 did not kill optical demand. The market was looking inside the rack. The money is outside it. When NVIDIA wired its 72 GPUs together over an NVLink copper spine, a bear case followed: maybe optical content shrinks. That is the read SemiAnalysis called the “optical boogeyman.” But it treats scale-up and scale-out as the same network, and that is only half the picture. The moment Reflection AI signed a compute deal with SpaceX on June 22, 2026, for $150M a month and up to roughly $6.3B through 2029 [1][2][3], this stopped being GPU-rental news and became scale-out optics and field-validation news. SpaceX, which went public on June 12 ($SPCX), is shifting Colossus into a business that rents capacity to outside AI labs [4][5][6], and Anthropic (about $45B) and Google (about $30B) are already tenants on the same infrastructure [4]. Tickers in focus: $SPCX, $NVDA.

Reflection agreed to pay $150 million a month to rent compute

Start with the deal.

Reflection AI will pay SpaceX $150M every month from July 1, 2026, for access to GB300 chips. Run to the end of 2029, that is about $6.3B [1][2]. After the first three months, either side can terminate on 90 days notice [1][2]. Reflection is an open-weight model startup founded by former DeepMind researchers, Nvidia put in $800M, and its recent valuation is $25B [1].

This is not even the first deal. Tenants are lining up for the same Colossus.

• Anthropic: deal value about $45B, through mid-2029 [4].

• Google: deal value about $30B, through mid-2029 [4]

• Cursor: being acquired by SpaceX (an acquisition, not a lease) [3][4]

• Reflection: $150M a month, through end of 2029 [1][2]

Colossus, originally built to train Grok, has turned into a business that rents chips to outside AI labs [4]. The compute appetite of the open-weight camp is also adding demand to this rental model [5]. And on June 12, SpaceX went public and within days became one of the most valuable listed companies by market cap [6]. That said, $SPCX spiked right after listing and has since pulled back amid a roughly $20B bond offering and valuation concerns [6].

What matters here is not who the tenants are. It is that GPU utilization has started carrying a monthly price tag. Once rent is attached, the physical infrastructure underneath is no longer “capex that might get used someday” but “gear that has to hit a utilization target.” Compute is moving from an asset you buy to an asset you rent.

Compute is no longer gear you buy once. It has become an asset metered as monthly rent.

The Numbers on the Contract Split Into Copper and Light

For anyone who has not read the prior piece, in one line: in an AI buildout, the layer everyone passes through in a supplier-neutral way is optical modules, wafer/test, and deployment validation. This deal signals that demand at that layer is no longer just a vague capex inference. (Background is in Compute Is the New Oil. So Who Builds the Drilling Rigs?.)

The difference looks small but matters for investors. When a buildout sits on “demand will show up someday,” that is speculative capex. But when contracts with named amounts and end dates sit on top, like Anthropic, Google, and Reflection, the hardware demand underneath gains visibility [4]. With a 90-day termination clause, you cannot say it is “locked in” [1]. What changes is the question, from “will demand come” to “how much utilization is already contracted.”

So one layer down, what physical demand does that rent roll become? Hundreds of thousands of GPUs is a number on paper, but the moment it draws a path inside the rack, it splits into copper and light.

Figure 1. Colossus tenants by compute deal size and term.

Where the market misread it is the NVL72 copper spine

The problem is treating scale-up and scale-out as the same network.

A GB300 NVL72 rack holds 72 Blackwell Ultra GPUs and 36 Grace CPUs [7][8]. Power runs roughly from the 120kW range to the mid 150s kW depending on configuration and workload, and by Lenovo’s document it is 135kW TDP and up to 155kW peak [8][9]. This rack uses two kinds of network.

First, scale-up. Inside the rack, 72 GPUs are bound into one NVLink domain (1.8TB/s bidirectional) [7]. This is copper. Nvidia made it copper on purpose. Running the same links over optical transceivers would add about 20kW just for transceivers and retimers, so Nvidia wired the NVLink spine directly in copper to spend that power on compute instead [10]. That copper scale-up choice is what drove the “NVL72 kills optics” read, the one SemiAnalysis named the “optical boogeyman” and rebutted [10]. (Note that the recent optical-stock selloff is more about profit-taking on rich multiples than about this read. They are different things.)

Second, scale-out. The compute (East/West) fabric that links rack to rack. This is different. By NVIDIA’s reference architecture, an NVL72 rack (18 trays) puts a ConnectX-8 board on each tray to build the East/West fabric, and the per-tray aggregate bandwidth of that fabric is 3200 Gb/s [7]. Across the full rack, that is 72 scale-out connections at 800G class, matching the 72 GPUs. At the order-of-magnitude level, the key is one 800G-class scale-out connection per GPU [7][8][9]. And this East/West interconnect makes broad use of pluggable optical transceivers and detachable fiber [7]. Wiring the inside of the rack with copper does not reduce the optical ports leaving the rack.

So reading NVL72 as “less optical” is only half the picture. Scale-up did go copper, but optical intensity (scale-out ports per GPU) does not drop [10]. And as a cluster grows, spine sits above leaf and super-spine above that [7], so optical port demand actually rises with GPU count.

The copper in NVL72 is a scale-up story, not a scale-out story. The bigger the cluster, the more scale-out optical demand scales with GPU count.

Converting GPU count into optical ports and field-validation events

Now drop Colossus 2 scale into the physical layer. First, the uncertainty in the scale numbers. Colossus 2 bought its site last March and came online this January. Planned capacity has been reported at 2GW, roughly 555,000 GPUs, and about $18B, but these are not company-confirmed figures (trade press reporting, not confirmed by the company). In fact, against Musk’s claim of 1GW, January satellite imagery showed cooling for only about 350MW, and May reporting had 19 gas turbines being deployed [6]. So there is a large gap between plan and observation. The conversion below applies GB300 NVL72 reference-design ratios as an order-of-magnitude illustration, and Colossus 2’s actual GPU generation mix and topology have not been confirmed by the company (author estimate).

The ratio is simple. At the scale-out leaf level, it is one 800G port per GPU [7][8]. At a scale of hundreds of thousands of GPUs, that is hundreds of thousands of 800G ports at the leaf level alone (author estimate). Each optical link carries a transceiver at both ends, and once spine tiers sit above leaf, total transceiver count becomes several times the GPU count [7] (author estimate). Strip out the short runs handled by DAC/AEC and the real optical transceiver count comes in below that, but the order-of-magnitude feel is “hundreds of thousands of GPUs equals hundreds of thousands of scale-out ports, and once upper network tiers are included, a much larger number of optical transceiver endpoints.”

What the contract becomes at the physical layer:
1 GPU → 1 scale-out 800G-class connection
1 NVL72 rack → 72 GPUs → 72 scale-out connections
Hundreds of thousands of GPUs → hundreds of thousands of scale-out ports (at leaf)
Every optical endpoint → insertion-loss / return-loss / OTDR / BER validation

And each optical connection creates at least one field-validation event. (This is a different layer from semiconductor ATE test insertion. Package-level test insertions grow separately, and what we mean here is fiber field validation.) Field guides show GB300 deployments bringing in pre-terminated 144-fiber trunks and validating every connector with insertion-loss, return-loss, and OTDR [11]. More important, even transceivers that pass commissioning see BER drift as temperature rises, so a module that was fine at 25C starts accumulating errors under sustained load at 35C [11]. This is not plug-once-and-done. It creates validation demand at install time and recurring in operation. Optical module and structured-cable lead times run to months, so they can sit on the critical path of a deployment schedule [11].

The logic from the prior piece meshes here. I argued that denser packaging makes package-level test insertions grow superlinearly because of known-good-die economics, and scale-out optics points the same way. More GPUs means more optical ports, and more optical ports means more field validation and BER monitoring.

Figure 2. The two networks of GB300 NVL72: copper scale-up vs optical scale-out.

Figure 3. Translating GPU count into scale-out ports and field-validation events, an order-of-magnitude ladder.

How offtake contracts change equipment-layer beta

It is cleanest to split the demand into three layers. (This is a map of where demand lands, not a stock recommendation. The author holds no position in the names mentioned.)

• Optical modules/transceivers: the direct beneficiary of scale-out ports moving from 800G to 1.6T. Representative names include Coherent ($COHR) and Lumentum ($LITE).

• Silicon photonics/packaging: the layer that benefits when value shifts from modules to on-package via CPO/LPO.

• Optical/network test: field validation, BER, and production test. Representative names include Viavi ($VIAV) and Keysight ($KEYS).

One more structural point. A module vendor’s beta tracks closer to the port count, while a test vendor’s beta tracks closer to port count times operational complexity. So as the network moves from 800G to 1.6T, the leverage on validation difficulty can grow faster than raw unit counts. The test layer can be a more convex layer, not just trailing demand.

The key is that the character of demand changes. Before, you inferred “optical demand should follow” from hyperscaler capex guidance. Now the contract values are stated, like Anthropic about $45B, Google about $30B, and Reflection about $6.3B [4]. When a tenant runs that compute, GPUs run, and for GPUs to run, scale-out optics has to be in place, and that optics goes through validation.

Of course the 90-day termination clause is the biggest crack [1][2]. The full contract value is not guaranteed revenue. But one thing is clear. The GPU infrastructure already installed stays in place even if a tenant leaves, and taking the next tenant needs the same scale-out optics and validation. Optical and test demand is tied to the infrastructure itself, not to any single tenant.

The optical module market is not small either. 400/800G datacom optics is estimated to grow from about $9B in 2024 to about $16B in 2026, and AI-cluster optics is estimated to already exceed $4B a year [12]. Weigh one Colossus 2 buildout against that market and you can see how much a single offtake contract carries.

Tenants can change, but the scale-out optics and field validation needed to take the next tenant stay fixed to the infrastructure. The beta shifts from tenant risk to infrastructure utilization risk.

Scenarios and Monitoring

Base Case. Colossus 2 buildout proceeds as planned and tenant utilization holds. Scale-out optics and validation demand land in proportion to GPU count, and the equipment layer’s revenue visibility firms up one notch, from capex inference to contract-based.

Alternative. If CPO (co-packaged optics) and LPO (linear pluggable optics) arrive faster than expected, the value of scale-out optics shifts partly from discrete module vendors toward switch/NIC silicon and silicon photonics [12]. Transceiver counts fall, but packaging and validation difficulty rises, so the center of gravity of the beta moves from modules to photonics packaging and test.

Downside. If the 90-day termination clause actually gets pulled [1], or if the Colossus 2 buildout slips on power and site constraints, contract-based visibility retreats back to inference. The gap between the 1GW claim and the roughly 350MW observation, plus filling power with gas turbines, puts a question mark over whether this buildout gets filled as planned [6]. In that case the offtake premium fades, and optical demand goes back to moving with the hyperscaler capex cycle.

Monitoring points. (1) Whether Colossus 2 discloses actual operating capacity and GPU generation mix [6], (2) additional tenant signings and termination disclosures, (3) the pace of the 800G to 1.6T transition, (4) timing of CPO/LPO adoption [12], (5) optical module lead times (currently on the order of months [11]), (6) how $SPCX share price and the bond offering affect the pace of capex execution [6].

PhotonCap’s View

Do not read this deal as an acquisition. What SpaceX is acquiring is Cursor, and Reflection is a tenant renting compute [4]. The distinction matters because an acquisition is a one-time event, while a lease is a recurring utilization signal.

I read this deal not as a stock call but as a change in the character of demand. The equipment and validation layer that everyone passes through in a supplier-neutral way now sits on a lease with a stated contract value, not on capex inference [4]. The simplest version is this. The moment compute becomes a rental asset, the scale-out optics and field validation that physically enable that rental asset stay with the infrastructure even as tenants change.

That said, the 90-day termination clause and the 1GW versus 350MW observation gap always put an asterisk on this picture [6]. The discipline of this piece is to not read contract values and planned capacity as guaranteed numbers.

GPU tenants can change. But the optical ports, the fiber plant, and the validation workflow laid down to take those tenants do not disappear. That is why this deal reads as optical supply-chain news, not GPU news.

References & Sources

[1] TechCrunch, “SpaceX inks compute deal with Reflection AI, an open source AI lab”, Jun 2026.

[2] Reuters, “AI startup Reflection signs computing power deal with SpaceX”, Jun 2026.

[3] The Wall Street Journal, “SpaceX Strikes $6 Billion Deal With AI Startup for Data-Center Space”, Jun 2026.

[4] CNBC, “SpaceX signs computing power deal with open-source AI startup Reflection worth up to $6.3 billion”, Jun 2026.

[5] Axios, “Open-source AI gets more compute from SpaceX”, Jun 2026.

[6] Data Center Dynamics, “SpaceX secures $6.3bn compute capacity deal from AI startup Reflection”, Jun 2026.

[7] NVIDIA, “Network Logical Architecture, NVL72 AI Factory Enterprise Reference Architecture”, 2026.

[8] Lenovo Press, “Lenovo NVIDIA GB300 NVL72 Rack Scale AI Product Guide”, 2026.

[9] Introl, “NVIDIA GB300 NVL72 Deployment Guide: Blackwell Ultra Specs and Engineering”, 2025.

[10] SemiAnalysis, “Nvidia’s Optical Boogeyman: NVL72, Infiniband Scale Out, 800G and 1.6T Ramp”, Mar 2024.

[11] Akash Borate, “Understanding how to bring up NVIDIA GB300 NVL72: From Facility to First Run”, May 2026.

[12] FPX Research, “Beyond Power: The Networking Bottleneck Starting to Take Shape”, Dec 2025.

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Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

On June 22, 2026, Micron ($MU) announced a strategic agreement with Anthropic bundling a memory supply contract, joint design work, and a strategic investment into Anthropic’s Series H round [1]. Around the announcement, the stock traded at record-high levels [2]. Yet read the full agreement and the words optical, photonic, and interconnect never appear once. HBM, DRAM, SSD. All electrical memory. This piece uses that deal as a doorway to one idea. The memory wall is, at bottom, the problem of feeding data to compute fast enough, and HBM solved it by sitting the memory right next to the GPU. That very adjacency is what blocks the path to more capacity. The moment you pull memory away to add capacity, distance throws you back into the same wall. Carrying bandwidth and latency across that distance is what optics does. There are three paths to memory disaggregation, two of them optical and one electrical. The title is strong on purpose, but the claim in the body is narrower: this deal does not pull optical revenue forward so much as it strengthens the case for why optics becomes necessary. That is the author’s inference, and the body states its limits.

Intro: A Memory Deal With No Optics in It

On June 22, 2026, Micron announced its strategic agreement with Anthropic. Joint memory and storage architecture design, a multi-year supply contract, a strategic investment into Anthropic’s Series H round, and Micron’s internal adoption of Claude, all in one structure [1]. Around the announcement, $MU traded near record highs [2].

Read the agreement from top to bottom and there is no optical, no photonic, no interconnect. HBM, DRAM, SSD. A pure electrical memory deal. You might ask why PhotonCap, which covers optics, would write about this at all.

One thing first. The memory wall is not Anthropic’s problem alone. Any company scaling models, OpenAI or Google or anyone else, stands in front of the same wall. This deal is simply the most recent scene showing how much money that wall now trades for. So this piece uses the Anthropic deal only as a doorway and walks straight into the wall itself.

What the Memory Wall Actually Means

Think of the memory wall as a kitchen. The GPU is a kitchen that takes ingredients (data) and cooks (computes). The trouble is that cooking speed rises every generation, while the speed of bringing ingredients to the stove cannot keep up. However fast the kitchen, if the ingredients arrive late, it sits idle and waits. That waiting is the memory wall. The core issue is not capacity but speed, meaning bandwidth (how much at once) and latency (how quickly it arrives) [3].

HBM’s answer is simple. Put the pantry right next to the stove. Close means fast, and you can move a lot at once. HBM4 is the generation that enlarged this adjacent pantry, doubling the interface width under the JEDEC standard (JESD270-4) to push past 2 TB/s per stack [4]. NVIDIA Rubin secures roughly 22 TB/s with eight such stacks [5].

The catch is that the space next to the stove is small. The edge of the GPU die (the beachfront) has a fixed perimeter, so you cannot attach HBM without limit. Two things follow. First, to add memory you have to add GPUs. Memory and compute get locked into a fixed ratio. Second, there is a ceiling on how much memory a single GPU can reach.

This is where people often misread it. “Can’t you just add capacity? You can always buy more memory.” True. DRAM itself you can always buy more of. But the moment that memory sits far from the GPU rather than beside it, distance drops the bandwidth and stretches the latency. (For how distance and frequency break down an electrical signal, I covered it in detail in DSP, LPO, NPO, CPO: The Four Optical Architectures.) You hit the memory wall again. So the capacity problem is not a wall separate from the memory wall, it is an extension of the same one. The price HBM paid to clear the wall through adjacency is exactly the ceiling on capacity.

The short version: the memory wall is a problem of access speed [3], and HBM solves it by pinning memory right against the GPU. That adjacency creates the fixed ratio and the capacity ceiling, and the moment you try to pull memory away, distance becomes the wall again. To break this loop you have to carry speed across distance. That is where optics enters.

Why It Matters Now: Supply Is Short and Prices Are Rising

That this wall is not abstract is something the memory market is proving right now.

As it happens, Micron reports FQ3 FY2026 results after market close on June 24, 2026. The company’s prior guidance was revenue of $33.5B (plus or minus $750M), gross margin of about 81%, and non-GAAP EPS of $19.15 (plus or minus $0.40) [6]. Consensus just before publication varies by data source (revenue roughly $34B to $35.6B, EPS roughly $19.7 to $20.8), so it is hard to pin to a single number [7]. So rather than the number itself, look at the structure the number points to. If guidance holds, a gross margin near 81% would be the highest in the company’s 47-year history. This is a basis for the bull case and, at the same time, a symptom of the wall. HBM volume for 2026 is already sold out across every supplier [5], and price is the core driver of revenue growth. Prices rise because supply is short. Micron itself has said that as process transitions yield less, more greenfield wafer capacity is needed [8]. That is an admission that adding capacity keeps getting more expensive and slower.

Why this shortage is structural comes down to one ratio. Micron has stated on its earnings calls that, in the same process node, HBM consumes about three times the wafer per bit compared with ordinary DDR5, and that the ratio grows further with HBM4 [9]. Every HBM stack you add takes that much commodity DRAM supply out of the market. That is why the HBM boom drags commodity DRAM prices up with it.

The demand side sends the same signal. In early June, a one-line news item rattled memory stocks for days. The report was that NVIDIA would cut the low-power memory module (SOCAMM2) of its next-generation Vera Rubin server from 192GB to 96GB per module. The Elec and SemiAnalysis pinned the reason on an LPDDR supply shortage [10]. (This sequence is laid out well in Why NVIDIA Halved the Middle Memory. Keep in mind none of it was officially confirmed by the companies. It is reporting.) The market traded this headline twice. First it sold, reading the cut as “AI memory demand has finally cracked,” and a few days later it bought back, reading it as “no, they are rationing because there is not enough to go around.”

Nutty

Why NVIDIA Halved the Middle Memory

In early June, a single line of news rattled memory stocks for days…

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a month ago · 27 likes · 5 comments · Nutty

Both scenes point to one thing. Memory is short, and the root of the shortage is a structure where usable memory is expensive and that expensive memory has to sit next to compute. If a path opens to add capacity cheaply, decoupled from compute, this pressure eases. That path is memory disaggregation, and that is where optics shows up.

Three Paths Around the Wall: Memory Disaggregation

There is more than one way to pull memory off compute while keeping it usable. (For a map of the optical interconnect layers overall, seen through OFC 2026 papers, see I Read 24 Papers.) It splits into three paths, two of them optical and one electrical.

Path 1. Optical I/O chiplet (optical, the foundation). This is the path of building the optical input and output itself that holds bandwidth and latency when memory travels over distance. Ayar Labs is the representative. It drops an optical I/O chiplet called TeraPHY into the GPU or accelerator package, converting the electrical signal to light at the package edge and sending it out. It runs at roughly 8 Tbps bidirectional with latency around 10 to 25 nanoseconds, and because it extends the UCIe standard into optics, it is not locked to any single chip [11][12]. This is not a memory product but the foundation layer that lets memory sit far away. Ayar, with NVIDIA and AMD as investors, raised a $500M round in March 2026 and remains an independent company [11]. (For why CPO entered scale-out before scale-up, I covered it in Taiwan GTC Computex 2026: CPO.)

Path 2. Optical memory fabric, O-HBM (optical, a complement to HBM). This specializes optical I/O for memory, bringing HBM not beside the GPU but optically to any point on top of the die. Celestial AI’s Photonic Fabric is the representative. (For the technology itself and the denominator behind the “25x” claim, I laid it out in NVIDIA’s $2B Marvell Bet and Celestial AI’s “25x” Claim.) The core is letting the processor address, on top of the die-edge electrical HBM, optically connected HBM (O-HBM) as well [13]. One important positioning point.

This does not replace electrical HBM, it adds on beside it as a complement. You can free up the die edge to attach more electrical HBM there, or hang additional HBM optically. (For the structure of freeing the die edge to load more HBM, I covered it in detail in Copper Wall, Age of Light.) It pushes the capacity ceiling itself upward.

Path 3. CXL DRAM pooling (an electrical bypass, a candidate for later optical extension). Instead of buying more expensive HBM and GPUs to add capacity, this binds cheap commodity DRAM (DDR5) into a shared pool that multiple accelerators draw from. It is a slower tier than HBM, so it cannot stand in for HBM, but it substitutes for the cost of “buying more compute just to get capacity.” Strictly speaking, though, this path is not optics itself. XConn, which Marvell acquired, currently ships PCIe and CXL switching silicon (PCIe 5 / CXL 2.0 in production, PCIe 6 / CXL 3.1 sampling), and its role is near-range memory disaggregation [14]. Once the pooling radius reaches beyond the rack, the distance and power limits of electrical CXL can be complemented by optical I/O. So it is electrical for now, with optics as the next extension candidate.

In one line: Path 1 lays the road, Path 2 grows HBM along that road, and Path 3 routes around having to buy more HBM at all. (For how to cut the memory cost itself, How the Memory Tax Gets Solved takes a different angle on it well.)

Damnang’s Substack

How the Memory Tax Gets Solved

Memory got expensive and supply is short…

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a month ago · 60 likes · 5 comments · Damnang

Figure 1: The three paths to memory disaggregation. Path 1 optical I/O chiplet (optical, foundation) / Path 2 O-HBM (optical, HBM complement) / Path 3 CXL DRAM pooling (electrical bypass, optical as later extension). Show each path’s role, representative company, distance/latency zone, and whether it is optical

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Who, and When: Supply Chain and Investment Points

The three paths differ by company and by timing. This is where it splits from an investment view.

Independent vs consolidated. Path 1’s Ayar stays an independent company with NVIDIA and AMD as investors, tied into Taiwanese ASIC partners like Alchip and GUC and into TSMC packaging [11]. Paths 2 and 3, by contrast, Marvell gathered under one roof. It announced Celestial in December 2025 and closed it on February 2, 2026 ($3.25B base, up to $5.5B with milestones) [15][16], and it completed the XConn acquisition on February 10, 2026 [14]. (For the quarter where these two acquisitions first showed up in the numbers, I covered it in The Third Signal in May: Marvell Confirms.) So the optical memory fabric and CXL pooling consolidated into $MRVL, while the optical I/O chiplet layer remains in the independent camp (Ayar and others).

The layer underneath. Optical Paths 1 and 2 both need a light source (laser) to make the light and a foundry to print the PIC. Path 3’s CXL pooling is electrical for now, but as the pooling radius grows, an extension layer that meets optical I/O appears. Ayar’s SuperNova light source uses Sivers’ DFB laser, and TeraPHY runs on GlobalFoundries and TSMC processes [12]. This light-source, foundry, and packaging layer is the common ground that gets laid no matter which way the optical paths go. (For NVIDIA’s bets on this light-source and optical layer, see Coherent, Lumentum, Marvell, and Now Corning.)

Timing. This matters most. Marvell has guided that meaningful revenue from Celestial begins in the second half of FY2028, reaching a $500M annualized run rate in Q4 FY2028 and $1B in Q4 FY2029 [16]. XConn is earlier, with revenue beginning in Q3 FY2027, a $50M annualized run rate in Q4 FY2027, and $100M in FY2028 [14]. Both paths have a gap before revenue ramps in earnest, and optical O-HBM runs a step behind electrical CXL. Ayar likewise puts the real maturing of the optical I/O market at 2026 to 2028 [11].

Figure-Table 1: Supply-chain positioning of the three memory-disaggregation paths. Path / Optical? / Role / Representative / Ticker or Status / Revenue Timeline

Net of it, the path to unlocking capacity is not waiting on invention. A company stands on each path, Paths 2 and 3 gathered into $MRVL, and Path 1 left in the independent camp. The remaining variables are adoption speed and the different revenue timelines per path. Electrical CXL first, optics next.

How This Deal Moves the Clock (Author’s Inference)

From here on this is not what a primary source states directly but the author’s inference. Let me be clear about that going in.

The Micron-Anthropic deal locks in electrical HBM on a multi-year basis [1]. In the short run this is not favorable to optical disaggregation. If anything, it fixes electrical HBM demand in place. So the frame that “optics rode along on this deal” is wrong.

But from the capacity angle, the direction flips. A commitment to scale frontier models on a multi-year basis means hitting the constraint that memory must sit next to compute more often and harder. No matter how high you push HBM bandwidth, as long as capacity cannot be separated from compute, a workload that needs more capacity has to buy more GPUs alongside, and that pushes total memory prices higher through the structure where HBM eats about three times the wafer of DDR5 [9]. The stronger the electrical HBM lock-in, the greater the pressure to separate and add capacity cheaply, meaning the case for memory disaggregation grows.

The limits of this inference are clear. First, this is not a conclusion Micron or Anthropic stated, but the author’s inference drawn from the structure of the memory wall. Second, a stronger case does not automatically speed up adoption. There are separate gates of yield, latency validation, and customer qualification. Third, timing is the crux. The pressure builds now, but optical revenue is FY2028 and beyond, so this is a lag play, not a catalyst. The “clock” in the title is the hook, and the more precise word is “the case.”

Scenarios

Labels are qualitative only. No probability percentages.

Base Case. Electrical HBM stays the center of data center memory through 2026 and 2027. Multi-year deals like Micron-Anthropic keep coming, adjacent memory bandwidth keeps strengthening [4], and the sold-out posture holds [5]. Memory disaggregation begins showing up in revenue with electrical CXL (XConn) from FY2027 and optics (Celestial) from FY2028 [14][16], building share gradually as a lag play.

Alternative. Capacity pressure surfaces faster than expected. Of the three, CXL pooling (Path 3) gets adopted before optical O-HBM, at near range, serving as the first bypass [14]. In this case the optical I/O chiplet (Path 1) and O-HBM (Path 2) follow as the next step.

Downside. Capacity gets routed around without disaggregation. Per-stack capacity gains in HBM4E (48GB 12-high and the like) and model-side memory efficiency (quantization, offloading) delay the pain enough that the case for optics weakens and the revenue timeline slips further out [17].

What to Monitor

• The June 24 Micron earnings call: 2027 HBM visibility, ASP and price durability, margin hold, greenfield capacity comments, and the actual beat against a consensus that varies by source [6][7][8]. The stronger the shortage and pricing power, the more the capacity pressure shows up in the numbers.

• The quarter where Celestial and XConn figures get broken out in Marvell’s results. Whether the FY2027 (XConn) and FY2028 (Celestial) guides pull forward or slip is the speedometer [14][16].

• Customer qualification, tape-out, and volume announcements from the independent optical I/O camp like Ayar. Whether Path 1 moves first [11].

• Official adoption of memory pooling and disaggregation by hyperscalers. Whether the electrical CXL path (Path 3) or the optical path (Paths 1, 2) comes first.

• HBM4E capacity density, the DRAM price curve, and module configuration shifts like SOCAMM [10][17].

PhotonCap’s View

This deal has no optics in it. That is a fact, and the right move is to accept it as is. The frame that optics rode directly onto a memory deal is overclaim.

Here is the picture I see instead. The memory wall is a problem of access speed, and HBM solved it through adjacency while creating a capacity ceiling. Pushing that ceiling across distance is memory disaggregation, and it has three paths: optical I/O chiplet (optical), O-HBM (optical) [13], and CXL pooling (electrical, with optics as a later extension). Paths 2 and 3 are already gathered into $MRVL [15], and Path 1 remains in the independent camp. The order is electrical CXL first into revenue, optics following. This deal does not pull that clock forward directly, but it hardens the case for pulling memory off compute. My positions ($POET, $LWLG) do not map cleanly onto this memory-pooling set, so I have left them out of this article’s analysis.

Coming Next

This piece goes as far as the “necessity” of disaggregation. Why it is needed, who stands where. The next paid piece will go a step deeper into when optical memory actually becomes revenue, through which yield and validation gates, and the realistic roadmap per path. Necessity and feasibility are different convictions.

References & Sources

[1] Micron Technology, “Micron and Anthropic Announce Strategic Agreement to Scale Next-Generation AI Infrastructure”, 2026.6.22. Joint memory/storage design, multi-year supply contract, Series H investment, internal Claude adoption.

[2] TheStreet, “Bank of America strongly resets Micron stock price target”, 2026.6. $MU trading at record-high levels around the Anthropic deal, 800%+ one-year return.

[3] Introl, “The AI Memory Supercycle”, 2026.1. Memory wall definition. Bandwidth and latency of feeding data to compute as the bottleneck.

[4] Siemens, “HBM3e and HBM4: IC design guide for next-generation high bandwidth memory”, 2026.4. JEDEC JESD270-4 (2025.4), 2048-bit, 32 channels, over 2 TB/s per stack, up to 64GB/stack.

[5] Introl, “South Korea’s HBM4 Moment”, 2026.1. Rubin 288GB HBM4 across 8 stacks, about 22 TB/s. SK Hynix, Micron 2026 HBM volume sold-out guidance.

[6] Micron Technology, “FQ2 2026 Results and FQ3 Guidance” (SEC Form 8-K, Ex-99.1), 2026.3. FQ3 guide revenue $33.5B (plus or minus $750M), gross margin about 81%, non-GAAP EPS $19.15 (plus or minus $0.40).

[7] indmoney, “Micron Earnings Preview: HBM, AI Memory Demand & MU Stock Outlook”, 2026.6. June 24 report, consensus varies by source, revenue roughly $34B to $35.6B, EPS roughly $19.7 to $20.8. (Consensus estimate, varies by source.)

[8] Micron Technology (investor conference comments), “Micron IR Earnings Summary & Outlook (J.P. Morgan TMT Conference)”, 2026.5. Demand exceeding supply, tightness persisting beyond 2026, price as the core driver of revenue growth, lower process-transition productivity requiring greenfield wafer capacity.

[9] Tom’s Hardware (citing Micron management), “HBM is coming for your PC’s RAM”, 2025.12. Per Micron’s earnings remarks, HBM consumes about three times the wafer of DDR5 per bit at the same node, with the ratio widening for HBM4. (Micron CEO Mehrotra, FQ2/Q3 FY2024 call.)

[10] The Elec, “Nvidia Cuts SOCAMM2 Capacity in Half Amid LPDDR Shortage”, 2026.6.9. SOCAMM2 module cut from 192GB to 96GB, attributed to LPDDR shortage (originating from SemiAnalysis reporting, June 4). Not officially confirmed by the companies.

[11] DatacenterDynamics, “Optical interconnect startup Ayar Labs closes $500m funding round backed by Nvidia and AMD”, 2026.5. NVIDIA/AMD-backed $500M round (2026.3), TeraPHY optical I/O, Alchip/TSMC partners, independent.

[12] Gazettabyte, “Ayar Labs prepares to fulfil its optical input-output (I/O) vision”, 2026.2. TeraPHY 8 Tbps bidirectional, UCIe extended into optics, SuperNova using Sivers DFB laser, GlobalFoundries/TSMC processes.

[13] Optics.org, “Celestial AI lands $100M for optical interconnects”, 2023. OMIB, O-HBM, optical delivery to any point on the die. (Includes Celestial’s own claims.)

[14] Marvell Technology, “Marvell Completes Acquisition of XConn Technologies”, 2026.2.10. PCIe and CXL switching silicon. PCIe 5/CXL 2.0 production, PCIe 6/CXL 3.1 sampling. Revenue beginning Q3 FY2027, $50M annualized run rate Q4 FY2027, $100M FY2028.

[15] Marvell Technology, “Marvell Completes Acquisition of Celestial AI” (SEC Form 8-K/A, Ex-99.1), 2026.2.2. Acquisition closed.

[16] Marvell Technology, “Marvell to Acquire Celestial AI, Accelerating Scale-up Connectivity”, 2025.12.2. $3.25B base up to $5.5B, pooled memory appliances noted, revenue beginning 2H FY2028, $500M Q4 FY2028, $1B Q4 FY2029.

[17] TechTimes (reporting), “SK hynix Ships 12-Layer HBM4E Samples Ahead of Schedule”, 2026.6.19. 48GB 12-high HBM4E samples.

Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

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On June 9, an institutional-only SemiAnalysis note lit the fuse, and optics names dropped together. AAOI fell 14%, COHR 11%, LITE 8% [1][2]. The market’s logic was simple: “CPO volume slips to 2028 to 2029, so photonics is over.” Yet the very next day the same names bounced (AAOI +7%, LITE +5%, COHR +2%) [3], and in the same week NTT, SK, and Chunghwa Telecom launched a new $500M fund pointed at optical communications and light sources [4][5]. This piece lays out the four optical architectures, DSP, LPO, NPO, and CPO, in a way a non-specialist can absorb in one read, then maps where Lumentum, Coherent, AAOI, and Sivers actually sit on that ladder. The thesis is one sentence. Photonics is not CPO. CPO is one form factor among several, and the light source, substrate, and fiber sit inside every one of them.

Table of Contents

1. In the Same Week, Two Opposite Things Happened

2. Why “Photonics Equals CPO” Is the Wrong Equation

3. The Optical Architecture Ladder: DSP · LPO · NPO · CPO (Pluggable+DSP / LPO / NPO / CPO)

4. So Why Does This Matter for Investing

5. Form Factor by Form Factor: What Gets Removed, What Stays

6. The Copper-Light Boundary: Lane Speed Pushes the Line Inward

7. The Light Source Map: Lumentum · Coherent · AAOI · Sivers

8. Capital Votes on the Destination, Not the Quarter

9. Copper Runs Longer. That Is Not a Bear Case.

10. Scenarios and Monitoring

11. Closing: Look Far, Not at Tomorrow

The PhotonCap Series Behind This Piece

• Part 1: There Is No Such Thing as a “CPO Stock,” How the Market Misread SemiAnalysis

• NVIDIA’s $4 Billion Photonics Bet: Broadcom Wasn’t Wrong · COHR, LITE

• Coherent, Lumentum, Marvell, and Now Corning: NVIDIA’s 4 Photonics Bets · COHR, LITE, MRVL, GLW

• NVIDIA’s $2B Marvell Bet and Celestial AI’s “25x” Claim · MRVL, interconnect

• The Silicon Photonics Light Source War: Same Problem, Three Solutions · Sivers, QD Laser, Aeluma

Intro: In the Same Week, Two Opposite Things Happened

On June 9, optics stocks fell apart in a single session. AAOI led the way down 14%, with Coherent off 11%, Lumentum 8%, and Ciena 7% [1][2]. The trigger was an institutional-only note from SemiAnalysis. It reportedly said CPO (Co-Packaged Optics) volume timing is later than hoped, and outlets relayed summaries without confirming the original [1].

The story the market read was this: “CPO is late. CPO is photonics. So sell photonics.” The middle sentence is wrong, and the selling started from there.

That there is no such thing as a “CPO stock” is the argument I made in yesterday’s part 1. Today’s part 2 builds on it: draw the optical architecture once, and you can see why that middle sentence is wrong.

The same week ran the other way too. On June 10, the names that fell the day before simply bounced back. AAOI +7%, Lumentum +5%, Coherent +2% [3]. And that same day, at NTT headquarters in Tokyo, NTT, SK Telecom, Taiwan’s Chunghwa Telecom, and the Development Bank of Japan (DBJ) announced the IOWN AI Fund. Size $500M (about 760 billion won), with a management company, Catalight Capital, based in Silicon Valley and Tokyo. The stated investment scope names “Photonics Technologies,” “Light Source and Modulators,” and “optical communications” outright [4][5][6].

On one side, a “CPO is late, so sell the light” wave. On the other, telecom carriers and financial capital putting fresh money into “light.” Both in the same week. One of them is misreading the clock.

The June 9 selloff translated “CPO delay” into “sell photonics.” Whether that translation holds becomes a one-minute judgment once you know what the optical architecture actually looks like.

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Why “Photonics Equals CPO” Is the Wrong Equation

Start with an analogy. There is a power plant, and there are lamps that run on its electricity. Lamps come in types: ceiling fluorescents, desk lamps, recessed wall fixtures. CPO is the “recessed wall fixture.” It is fiddly to install, and the work can run late.

But you do not sell the power plant because the recessed fixtures are behind schedule. Fluorescents, desk lamps, and recessed fixtures all draw from the same plant. In CPO terms, the “power plant” is the light source, the substrate, and the fiber. Whatever form factor you choose, light has to be generated somewhere, modulated or routed through something, and carried somewhere.

Many of the names sold off on June 9 are closer to “power plant companies” than “fixture companies.” Lumentum and Coherent make lasers, transceivers, and materials, a layer that pluggable, LPO, and CPO all need. The plant stock fell on news that the recessed fixtures are running late.

This either-or, “CPO or copper,” is not new. Back in March, when Broadcom’s Hock Tan said on the earnings call that copper could carry the within-rack job and that CPO would arrive in time, not in 2026 or 2027, the market read it the same way, as a fight between a copper camp and an optics camp. As I laid out in NVIDIA’s $4 billion optics bet, Broadcom and NVIDIA were not in conflict but looking at different axes of time and distance. Inside the rack at 0 to 2 meters, copper is right for 2026 to 2027. Across clusters at 10 to 100 meters, optics is right for 2028 to 2030. This CPO delay panic is just the June version of that same frame.

So how do you tell “plant” from “fixture”? You learn the optical architecture ladder.

The Optical Architecture Ladder: DSP, LPO, NPO, CPO in One Pass

This ladder is best read along two axes. One is how close to the ASIC you put the optical engine. The other is where you restore the degraded electrical signal. LPO is a move along the second axis: it removes the module DSP and leans more on the host ASIC’s SerDes. NPO and CPO are moves along the first axis: they pull the optical engine toward the ASIC. The optical engine (the cluster of optics that makes and receives light) and who restores the signal, those two together are what name every form factor.

Why does that matter? Because the electrical signal coming out of the AI chip (ASIC) travels over copper wiring. The faster the signal goes (these days over 200G per lane in PAM4), the faster it degrades on copper. There are only two ways to deal with that. One is to attach a chip (DSP) that restores the degraded signal. The other is to pull the optical engine closer to the ASIC and cut the copper distance outright. The ladder is the process of shrinking the copper electrical run by reducing the DSP, pulling the optical engine toward the ASIC, or combining the two. Let us climb it.

Rung 1. Pluggable + DSP (today’s standard)

The optical engine sits inside a swappable module that plugs into the switch front panel. The 800G and 1.6T transceivers you usually hear about are this. Electrical signals from the switch ASIC travel across copper PCB to the front panel, and the longer that run, the more the signal degrades, so a DSP (Digital Signal Processor) inside the module restores it. It is the most mature and most proven approach.

• Definition: optical engine inside a pluggable front-panel module. Today’s 800G/1.6T standard.

• How it works: ASIC to copper PCB to front-panel module. The long run degrades the signal, so the module’s DSP restores it.

• Upside: standardized, hot-swappable (swap just the module on failure), long reach, the most mature ecosystem.

• Tradeoff: the DSP is power hungry, and each module has a power and thermal ceiling, so rising bandwidth hits a wall.

Rung 2. LPO (Linear Pluggable Optics)

Same pluggable form factor, but with the module’s DSP removed. The switch ASIC’s SerDes handles signal conditioning instead, and the module’s amplifier (TIA) and driver simply pass the signal through in linear mode. The DSP was the most power-hungry part, so removing it brings power and cost down together [7].

• Definition: same pluggable form factor, with only the module DSP removed, the “linear” version.

• How it works: signal restoration moves from the module to the switch ASIC’s SerDes. The module only passes through.

• Upside: power, cost, and latency drop with the DSP gone. Reuses existing pluggable infrastructure.

• Tradeoff: performance can vary by host platform, so interoperability is tricky. A practical bridge before CPO.

Rung 3. NPO (Near-Packaged Optics)

The optical engine moves off the front panel to sit next to the switch ASIC on the main board. The electrical run shortens, so loss and power drop. It is a midpoint before full CPO, a compromise that captures some of the benefit at lower packaging difficulty than CPO.

• Definition: optical engine pulled off the front panel to sit beside the ASIC on the board.

• How it works: shortens the electrical path to board level, cutting loss and power.

• Upside: some of CPO’s benefit at lower packaging difficulty. Easier to use the existing supply chain.

• Tradeoff: less efficient than full CPO, and a board-level electrical path still remains.

Rung 4. CPO (Co-Packaged Optics)

The optical engine is co-packaged on the same package as the switch or GPU ASIC, right beside it. The electrical signal barely moves, so power efficiency is best. The catch: lasers are heat sensitive and hard to place beside a hot ASIC, so the laser is pulled out into a separate module outside the package. That is the External Light Source (ELS). It is the most efficient, but packaging and yield are the hardest, so volume comes latest.

• Definition: optical engine co-packaged with the ASIC, the final rung.

• How it works: minimizes the electrical path. The heat-sensitive laser is split out into an external ELS.

• Upside: best power efficiency and bandwidth density. The copper electrical wiring nearly vanishes.

• Tradeoff: highest packaging, yield, and test difficulty, so volume comes last. This is exactly the rung SemiAnalysis called late.

The Whole Ladder in One Line

We climbed all four rungs, but the point is not the ladder itself. It is the shared foundation under all four rungs. Whether rung 1 pluggable or rung 4 CPO, light is made in a laser (the source), modulated on a substrate, and carried on fiber. Silicon is not an efficient light-emitting material in the first place (I covered this in detail in the earlier light source piece), so most commercial silicon photonics links bring in a III-V light source separately, as an ELS or through hybrid integration. So whether DSP is removed (LPO) or the engine relocates (NPO, CPO), those three layers, light source, substrate, and fiber, do not drop out of any form factor.

One more thing. This ladder is also a story about where light begins. Short distances (inside one rack) still favor copper, and from longer distances (rack to rack) light takes over. Which way that boundary moves over time is what actually sets the pace of the whole ladder. I unpack this in detail later, as copper demand versus light demand.

[Figure 1: The optical architecture ladder. Four form factors from pluggable+DSP to CPO, with the copper (electrical) line and the optical (light) line color-distinguished, the copper segment shrinking and the optical engine moving toward the ASIC up the rungs]

To restate it, what SemiAnalysis called late is rung 4, CPO. And not “CPO will not happen” but “large-scale volume timing slips,” a speed claim. Rungs 1, 2, and 3 keep selling in the meantime, and all four draw on the light source and fiber beneath them. So selling the entire optical layer on the single sentence “CPO delay” is a trade that fails to separate the form factor from the shared component layer.

So Why Does This Matter for Investing

That is the picture I can lay out for free. The architecture is a ladder, CPO is the top rung, and the foundation beneath is shared.

The real question starts here. Among the names that fell together on June 9, who is CPO-dependent and who is not? Who is the plant and who is the fixture? Was Lumentum’s drop justified, or was it a power plant swept up in fixture news? Where does the EML that AAOI makes hang on the ladder? Does a pure light-source company like Sivers fall with CPO if it slips, or is it actually safer?

And the direction of capital. Was it a coincidence that NTT and SK put $500M into optical communications in the same week, or are they looking at the destination of the whole ladder?

One preview before the paywall. That AAOI fell hardest on June 9 (down 14%) and bounced hardest the next day (up 7%) is no accident. It is because of the rung AAOI stands on in the ladder. Where that rung is, and by the same logic why Lumentum is a “power plant” and why Sivers is actually safer, I work through one by one just below.

Below, I lay out the form-factor comparison quantitatively, map the four light-source companies onto the ladder, and itemize the capital that actually flowed into photonics in the second week of June. AAOI is a pluggable overshoot, Lumentum is laser capacity, Coherent is a composite materials-and-transceiver exposure, Sivers is the purest light-source option. Same selloff, but not the same bet.

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Form Factor by Form Factor: What Gets Removed, What Stays

Let us lay the ladder back down, quantitatively. Put the four form factors side by side across DSP presence, optical engine location, reach, light source needed, and CPO-dependency, and the picture sharpens.

[Figure-Table 1: Form factor comparison matrix. Pluggable+DSP / LPO / NPO / CPO compared across DSP, engine location, reach, light source, CPO-dependency]

Read it like this. Follow the leftmost column (form factor) down, and look only at the rightmost column (CPO-dependency). Pluggable and LPO have the lowest direct CPO-dependency. They have their own market whether CPO is late or early, and if anything, when CPO is late, LPO and pluggable fill the gap longer. NPO straddles the middle, and CPO has the highest direct dependency. (Long term CPO could encroach on the pluggable socket, so read this as “low direct dependency,” not “zero.”)

The key is the reach column. On the Ethernet and switch side, like NVIDIA’s Spectrum-X, CPO and ELS make sense first in scale-out (rack to rack, longer distance) links. By contrast, scale-up (binding GPUs densely within a single rack) has short distances, so copper runs longer there for now. There is a separate push to bring optics into scale-up too: what Ayar Labs targets with NVLink Fusion is exactly this scale-up optical I/O, and it is the furthest-out and hardest rung. So “CPO delay” is precisely “delay in the large-scale timing of scale-out going optical,” plus the persistence of scale-up copper, plus the extension of LPO and pluggable in between. None of those three is a picture of photonics revenue disappearing.

If you do not know there are four rungs, the single sentence “CPO delay” sounds like it knocks down all four. In reality, when one rung is late, the three below it buy that time.

The Copper-Light Boundary: Lane Speed Pushes the Line Inward

For anyone seeing this selloff for the first time, let me bring up something from two years ago. In March 2024, when NVIDIA unveiled the GB200 NVL72, the optics market had exactly the same panic. NVL72 binds 72 GPUs inside one rack over NVLink, and it did that link in copper, not optics. On the fear that “binding the rack in copper cuts optical transceiver demand,” optics names fell in a heap [8]. That it was a misread is clear from the fact that the same names rose several times over in the two years since.

The key is that an AI data center has more than one kind of network. It splits into two.

Scale-up. Binding GPUs densely within a single rack (or a single NVLink domain). Distances are short (tens of centimeters to 1 to 2 meters). NVL72 handles this with an NVLink passive copper cable backplane [9]. Push a tray in and it mates straight into the copper backplane at the rear. Per NVIDIA, one NVL72 rack carries about 5,184 direct-drive copper cables, totaling 2 miles (3.2 km). Doing this in optics would have cost about 20kW more in transceivers and retimers alone, and putting that into copper freed the 20kW for compute, as Jensen Huang explained [8]. Over short distances copper needs no laser, no optical-electrical conversion, and no DSP, so it wins on power, cost, and latency.

Scale-out. Linking rack to rack and cluster to cluster. Distances are long. This is optical. But one decisive fact. Even though NVL72 switched scale-up to copper, scale-out optical intensity did not drop. The NVL72 rack still carries 400G/800G OSFP ports at one per GPU, the same ratio as the prior H100 generation [8]. Binding the inside of the rack in copper and shooting light out of the rack are different networks. One becoming copper does not make the other disappear.

That is the truth of the 2024 panic. The June 2026 CPO panic has the same structure. “One form factor (CPO) is late, so light shrinks” is the same misread.

So will copper hold scale-up forever? No. Here is where per-lane speed enters. How fast you send a signal per lane climbs from 100G to 200G to 224G, and the faster it goes, the shorter the distance copper can carry it cleanly. Passive copper (DAC) at 112G PAM4 topped out around 1.5m, and at 224G PAM4 the signal attenuates so badly it can barely travel an inch on a standard PCB before vanishing [10]. Attenuation, skin effect, and inter-symbol interference all hit at once [10]. That is the copper wall.

But copper does not retreat easily. The AEC (Active Electrical Cable) arrived, putting a DSP and retimer inside the cable connector head to regenerate the signal. AECs push past the passive-copper limit to extend reach up to 7m even at 224G [11][12]. Credo, MaxLinear, Astera Labs, and Amphenol are the players here. In March 2026 MaxLinear shipped a 224G scale-up retimer (Annapurna), formalizing the hybrid framing that “optics is essential for scale-out and longer distances, electrical is the advantage for scale-up” [10]. In other words, the very way copper holds scale-up is itself a new growth market, evolving from passive cable to active cable with retimer and DSP inside. Copper holding on means not “stasis” but “a different kind of silicon demand.”

[Figure 2: The copper-light boundary. The line between scale-up (copper) and scale-out (optical) marches inward as lane speed climbs from 100G to 224G, with bandwidth rising in both zones]

So the whole picture resolves like this. There is a boundary line between electrical and light, and on the distance axis it marks “past here, light is the advantage.” Each time lane speed climbs a generation, the distance copper can hold shrinks, so the boundary marches toward the die, inward. Light that once lived only outside the rack moving into the rack, onto the board, and finally into the package (CPO) is exactly this march of the boundary.

The architecture ladder drawn earlier is precisely this march. Pluggable+DSP has the boundary at the front panel, NPO pulls it onto the board, and CPO pulls it into the package. Climbing the ladder means removing the in-box copper electrical wiring and the DSP that restores it, and filling that space with light. What gets shaken in that process is not the light source but the DSP. LPO removing the module DSP threatens Marvell and Broadcom’s DSP revenue, not laser demand, and CPO removing the electrical wiring is the same.

Translated to investing, two things. First, copper holding scale-up longer is itself a growth driver for the AEC and retimer layer (Credo $CRDO, MaxLinear $MXL, Amphenol $APH, and others), and it does not cut scale-out optical demand. Second, what the June 9 selling confused is exactly this point. It bundled “copper/CPO timing” with “light demand.” In reality only where the boundary sits changes, while both copper-interconnect demand and optical demand rise together. It is not a picture of light shrinking but a picture of where light enters being pulled one rung inward every year.

Copper wins scale-up, light wins scale-out. And each time lane speed climbs, that boundary moves inward, eating into copper’s side, not light’s. In 2024 and again in 2026, the market read the direction of this line backwards.

The Light Source Map: Where Do Lumentum, Coherent, AAOI, and Sivers Sit

Now place the companies on the ladder. All four fell on June 9, but their positions on the ladder are completely different.

[Figure-Table 2: Light source company map. Lumentum / Coherent / AAOI / Sivers / POET across core layer, form-factor exposure, CPO-dependency, position]

Lumentum ($LITE). Makes lasers, datacenter transceivers, and components. Q3 FY2026 revenue was $808.4M, up about 90% year over year [13]. OCS (optical circuit switch) and CPO are still early: in its prior earnings update, management disclosed an OCS backlog well beyond $400M and an incremental CPO order deliverable in the first half of calendar 2027 [14]. The thing to see: most of Lumentum’s revenue comes not from CPO but from pluggable lasers and OCS. CPO is additive, not the body. If CPO slips, ELS revenue defers by that much while pluggable laser demand carries the company. NVIDIA’s $2B investment in Lumentum in March was made for exactly this laser capacity [15].

Coherent ($COHR). On top of lasers and transceivers, it owns materials like InP and SiC vertically. Q3 FY2026 revenue was $1.80B, with the datacenter and communications segment growing 41% year over year and making up 75% of the revenue mix [16]. It is partnered with NVIDIA on CPO-related products, anchored by a high-power CW laser made on its 6-inch InP line in Sherman, with next-generation product revenue expected to ramp from 2027 [16]. Coherent spans light source, transceiver, materials, and fiber/connector at once, so its exposure is the widest. Even if CPO is late, pluggable and materials are the safety net.

Applied Optoelectronics ($AAOI). Makes EML (externally modulated laser) chips and transceivers, and is one of the few EML makers with US domestic production. Q1 2026 revenue $151.1M (up from $99.9M a year earlier, +51%), with datacenter up 154% to $81.4M on a first volume 800G shipment to a hyperscaler. It guided Q2 to $180M to $198M and signaled a larger ramp through the second half [17]. EML is a component bolted firmly to rung 1 (pluggable). It is effectively unrelated to the CPO schedule, and the longer the EML shortage runs, the more the US domestic-production card stands out. The fact that it fell hardest at 14% on June 9 and bounced hardest at +7% the next day is no accident. It is the rung furthest from CPO taking the biggest hit on CPO news, a textbook overshoot.

Sivers Semiconductors ($SIVE). Makes InP DFB lasers, that is, the light source itself, as a pure play. It co-develops a CPO/ELS light engine with POET Technologies [18]. The light source is the foundation that rungs 1, 2, 3, and 4 all need, but by scale that light-source layer is occupied far more by Lumentum (ELS and InP capacity) and Coherent (6-inch InP high-power CW). What sets Sivers apart is that its entire business is the light source, so it is the purest, and therefore smallest, pure-play exposure to that layer. Even if CPO is late, the light source demand itself does not vanish, and how much of that delay Sivers absorbs into pluggable or LPO needs customer and product confirmation. If CPO arrives early, ELS demand pulls forward. If it slips, the broader need for external light sources remains, though the exact revenue path depends on customer design wins.

So the four companies that fell as one bundle on June 9 stand in completely different places on the ladder. AAOI on rung 1, furthest from CPO. Sivers under every rung. Lumentum and Coherent as the plant spanning rungs 1 through 4. The companies truly high in CPO-dependency are not these four but the ones selling the CPO switch itself, Broadcom and NVIDIA. And those two barely moved on June 9.

Capital Votes on the Destination, Not the Quarter

Better than saying “photonics is a buy” is showing where the money went. Here is the capital that flowed into photonics in the second week of June, itemized. I will keep the figures separate rather than summing them.

[Figure 3: Capital into photonics in the second week of June. IOWN Fund, Ayar Series E and NVLink, and NVIDIA’s four optical bets (COHR, LITE, MRVL, GLW) all converge on the shared foundation, not one rung]

IOWN AI Fund: $500M. Announced June 10 in Tokyo by NTT, SK Telecom, Chunghwa Telecom, and DBJ [4][6]. Per Yomiuri reporting, the initial plan was about 70 billion yen (about $440M) [5], firming to $500M (about 760 billion won) in the formal announcement [4]. The management company Catalight Capital is set up in Silicon Valley and East Asia, about 20 firms including Sony and Toshiba expressed interest as investors, and SK Hynix is on the list of interested investors [4]. The investment targets explicitly list “photonics-electronics convergence,” “Light Source and Modulators,” and “optical communications” [5][6]. IOWN is NTT’s 2019 concept of carrying data with light instead of electricity inside chips and across networks [5]. Telecom carriers and financial capital built a new fund treating “light” as the core of next-generation infrastructure. The timing happened to be the same week as the CPO selloff.

Ayar Labs: NVLink Fusion + $500M Series E. On June 3, the CPO pure play Ayar Labs joined NVIDIA’s NVLink Fusion ecosystem, making its products compatible with NVIDIA optics and SerDes to bring CPO into scale-up [19]. The announcement sits on top of a $500M Series E that NVIDIA participated in [19]. What stands out is that Ayar is going after scale-up. As we saw, scale-up is where copper runs longer for now. So Ayar’s bet is the furthest-out and hardest hand, which is itself evidence that photonics’ time axis sits not tomorrow but further out.

NVIDIA’s optical bets, now four. In early March, NVIDIA invested about $2B each into Coherent, Lumentum, and Marvell (Lumentum confirmed via NVIDIA newsroom) [15], and in May it added Corning on the fiber side. With Corning, through a multiyear commercial and technology partnership, Corning will grow its US optical connectivity capacity 10x and its fiber production by more than 50% [20], while NVIDIA’s stake is structured as an initial $500M plus warrants (15M common shares at a $180 strike) that, if fully exercised, would reach up to about $3.2B [21][22]. I covered all four together in this piece, and the Marvell bet on its own, from the interconnect angle, in this one. The meaning of the four reduces to one line: light source (COHR, LITE), interconnect (MRVL), fiber (GLW). All of it flows not into one CPO form factor but into the shared foundation under the ladder itself.

The three capital sources (the IOWN fund, Ayar, NVIDIA) share an obvious trait. All flowed not into one rung but into the foundation beneath: light source, optical communications, fiber, laser capacity. While the market fights quarter by quarter over whether CPO lands in 2026 or 2028, strategic capital is betting on a longer horizon: that light eventually replaces copper.

Selloffs trade the quarter. Strategic capital trades the destination. In the second week of June, the two moved in exactly opposite directions.

Copper Runs Longer. That Is Not a Bear Case.

To avoid confusion, let me be clear. The CPO skeptics are not without a point. Looking at packaging complexity, yield, test, and chiplet ecosystem maturity, it is entirely realistic that large-scale CPO volume runs later than the market expected in 2025. And in scale-up, copper will hold on longer than people think.

But those two things do not make a photonics bear case. The reason is in the ladder.

When CPO is late, LPO and pluggable buy that time. Both are photonics that use light source and fiber. When copper holds longer in scale-up, scale-out going optical proceeds longer and more gradually, not as one abrupt switch but across a long bridge, with NPO and LPO each generating revenue as midpoints. An attempt like Ayar’s to push CPO even into scale-up is a bet on the latest rung, which means not the end of photonics but a longer runway for it.

One sizing estimate to add: some see the CPO market going from $70M in 2024 to $8B in 2030 (estimate). That is over 120% annual growth, and the point is this curve still starts near zero. A curve starting from zero does not collapse on a single quarter. It just slips in time.

Scenarios and Monitoring

Qualitative scenarios at the sector level. No price targets on individual names.

Base. Scale-out going optical proceeds gradually, large-scale CPO volume defers to 2027 to 2028, and LPO, pluggable, and OCS carry revenue in between. Demand for the light source, fiber, and materials layer continues regardless of the form-factor transition.

Alternative. CPO volume lands sooner than the market expects (for instance, early adoption by a specific hyperscaler), and ELS demand pulls forward. In this case Lumentum and Coherent’s high-power CW/ELS revenue accelerates, and the pure light-source plays (Sivers, POET) see direct benefit.

Downside. AI capex itself slows, or copper (or LPO) dominates far longer than expected, delaying the optical transition. Even here, it is “transition delay,” not “demand disappearance.” Transceiver and OCS demand holds as long as AI traffic grows.

I narrow the monitoring points to five. First, the timing of hyperscaler CPO adoption disclosures (NVIDIA, Broadcom, Marvell switches). Second, LPO standardization and interoperability progress (this governs how much further CPO slips). Third, whether the EML shortage clears and the resulting utilization of AAOI’s US capacity. Fourth, the pace of OCS backlog converting to revenue (Lumentum’s per-quarter target). Fifth, which startups strategic capital like the IOWN AI Fund actually flows into.

Closing: Look Far, Not at Tomorrow

June 9 and 10 were days when the same names fell double digits and bounced back within a day. On days like that, price carries almost no information. What it carries is fear and relief trading places.

The real information is in the ladder. Photonics is a four-rung ladder, CPO is the top rung, and the light source, substrate, and fiber beneath are stepped on by all four. Selling the foundation on news that one rung’s volume is late is like dumping a stake in the power plant because the recessed fixtures are behind schedule.

And in the same week, telecom carriers and financial capital put fresh money into exactly that power plant. They traded not the next quarter but the next decade.

Copper clearly runs longer. But “runs longer” and “wins” are different statements. As traffic grows, copper hits the wall of distance and power, and beyond that wall is light. Trading whether the pace of light replacing copper is a quarter late or early is fine. Selling the direction itself is the mistake to avoid.

If you watched this selloff without knowing the optical architecture, what to sell and what to hold would have looked inverted. Once you have drawn the ladder once, you will not repeat the same mistake at the next selloff. That is the purpose of this piece.

References & Sources

[1] Seeking Alpha, “Applied Optoelectronics Leads Networking Stocks Down Following Report on CPO Rollout Delay”, Jun 2026.

[2] GuruFocus, “Applied Optoelectronics (AAOI) Shares Drop 14% Amid Bearish Report”, Jun 2026.

[3] 24/7 Wall St., “Applied Optoelectronics Jumps 7%, Lumentum Climbs 5%, Coherent Rises 2% as Optics Stocks Ride the AI Boom”, Jun 2026.

[4] BusinessKorea, “SKT, NTT Launch $500 Million AI Fund”, Jun 2026.

[5] UPI / Asia Today, “NTT, SK Group plan $440M AI optical network fund”, Jun 2026.

[6] TechNode Global, “NTT, SK, Chunghwa Telecom, DBJ team up for $500M AI fund”, Jun 2026.

[7] Flexoptix, “Introducing Linear Pluggable Optics (LPO)”, 2026.

[9] NVIDIA, “DGX GB200 Rack Scale Systems User Guide: Hardware (NVLink passive copper cable backplane)”, 2026.

[8] SemiAnalysis, “Nvidia’s Optical Boogeyman: NVL72, InfiniBand Scale Out, 800G and 1.6T Ramp”, 2025.

[10] MaxLinear, “MaxLinear Unveils Annapurna 224G Scale-Up Retimer to Extend Copper Connectivity in AI Data Centers”, Mar 2026.

[11] Credo, “Credo Expands AEC Active Electrical Cable Family with Second Generation HiWire LP SPAN AEC”, 2021.

[12] Molex, “Active Electrical Cable Solutions (AEC, 112G and 224G, up to 7 meters)”, 2026.

[13] Lumentum Holdings, “Lumentum Announces Third Quarter of Fiscal Year 2026 Financial Results”, May 2026.

[14] Lumentum Holdings, “Form 8-K, Second Quarter Fiscal 2026 Results (Exhibit 99.1: OCS backlog well beyond $400M; incremental CPO order deliverable in first half calendar 2027)”, Feb 2026.

[15] NVIDIA Newsroom, “NVIDIA Announces Strategic Partnership With Lumentum to Develop State-of-the-Art Optics Technology”, Mar 2026.

[16] Coherent Corp., “Form 8-K, Third Quarter Fiscal 2026 Results (Exhibit 99.2: revenue $1.80B, Datacenter & Communications 75% of mix, +41% YoY)”, May 2026.

[17] Applied Optoelectronics, “Applied Optoelectronics Reports First Quarter 2026 Results”, May 2026.

[18] Sivers Semiconductors, “Sivers Semiconductors Partners With POET Technologies”, Nov 2025.

[19] HPCwire, “Ayar Labs Joins NVIDIA NVLink Fusion Ecosystem to Bring Co-Packaged Optics to AI Factories”, Jun 2026.

[20] Corning Incorporated, “NVIDIA and Corning Announce Long-Term Partnership To Strengthen U.S. Manufacturing for AI Infrastructure”, May 2026.

[21] Corning Incorporated, “Form 8-K: NVIDIA Warrant Agreement (15M shares at $180, $500M aggregate)”, May 2026.

[22] Reuters, “Nvidia funds construction of Corning plants, in addition to equity investment (stake of up to $3.2B)”, May 2026.

Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

Contents

1. Introduction

2. How Chinese Optical Modules Became Number One

3. Value Chain Structure: Where Margins Diverge Between Modules and Chips

4. DSP and EML: Two Chokepoints

5. The Truth About Southeast Asian Factories: Tariff Avoidance or Real Manufacturing?

6. Can LPO/SiPh Change the Structure?

7. Closing

8. References & Sources

1. Introduction

As recently as 2016, only two Chinese companies (Accelink and Hisense Broadband) made the global top 10 optical module supplier list. By 2024, that number had grown to seven.[1]

The landscape flipped in less than a decade. Innolight posted 2024 revenue of RMB 23.86 billion (roughly $3.3 billion), claiming the global number one spot.[2] Eoptolink recorded approximately 175% revenue growth the same year, jumping to third place.[1]

According to multiple industry sources, these two companies are said to have captured roughly 60% of NVIDIA’s 800G optical module volume. The remaining 40% is split among U.S. suppliers like Coherent and Lumentum.[3]

Surface-level market share and actual value chain control are different things. China leads the world in module assembly, but the critical chips inside are mostly imported. DSPs (Digital Signal Processors) are effectively a duopoly between Broadcom and Marvell, while high-speed laser chips (EMLs) are held by Lumentum, Coherent, and Mitsubishi.

The question is straightforward. China dominates modules. So why do chip companies keep the excess profit?

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2. How Chinese Optical Modules Became Number One

The growth of China’s optical module industry breaks down into three phases.

Phase 1: Domestic market as training ground (early to mid 2010s)

It started with 4G/5G infrastructure spending by China’s three mobile carriers (China Mobile, China Telecom, China Unicom). According to LightCounting, the Chinese optical transceiver market alone ran at $2 to 3 billion annually, and that volume became the soil for Chinese manufacturers to build mass production capability.[4]

Think of it this way: Chinese module makers first built muscle in a massive domestic “practice arena.” They produced 100G and 200G modules at scale, accumulating yield and cost advantages. That foundation later became their ticket to overseas markets.

Phase 2: Riding the North American cloud wave (early 2020s)

The turning point came when U.S. hyperscalers (Google, Amazon, Microsoft, Meta) began aggressively building out 400G data centers. This is where Chinese suppliers’ strengths shone: pricing, fast lead times, and volume production capacity.

Innolight established itself as a core supplier to Google and Microsoft, while Eoptolink embedded deeply into the AWS supply chain. Overseas revenue ratios surged. In Innolight’s case, overseas revenue accounted for 86.8% of 2024 total sales.[2] Most of that was North America.

Phase 3: AI clusters changed everything (2023 to present)

The number of optical modules needed per GPU in AI training clusters jumped significantly. Traditional servers needed two to four transceivers each. AI training clusters require multiple 800G links per GPU. Transceiver demand now scales proportionally with GPU demand.

The datacom optical component market is projected to exceed $16 billion in 2025, growing more than 60% year over year.[3] TrendForce projects 800G and above transceiver shipments to jump from 24 million units in 2025 to roughly 63 million in 2026, a 2.6x increase.[5]

Not many companies can handle that volume. Innolight and Eoptolink securing roughly 60% (industry estimate) of NVIDIA’s GB200-related 800G orders is not just about being cheap. There simply aren’t many suppliers that can deliver at this scale on schedule.

Here is a quick look at the key players.

Innolight posted 2024 revenue of RMB 23.86 billion (roughly $3.3 billion), making it the global number one.[2] It is widely understood to have very high exposure to North American hyperscalers, and industry channel checks suggest its 800G market share is among the highest. The company is also actively investing in SiPh and CPO. Eoptolink recorded RMB 8.65 billion (roughly $1.2 billion) the same year, with a strong presence in the North American cloud supply chain. It holds a leading position in LPO technology, and its 33% net margin is unusually high for a module assembler.[1]

Huawei is the global number one in telecom, but is focused on non-U.S. markets due to export restrictions. It is developing SiPh in-house. Accelink is one of the few vertically integrated (IDM) players in China, covering everything from chips to modules across both telecom and data center markets.

Behind them, Hisense Broadband holds a full chain from optical chips to terminal devices, HG Genuine has secured cost advantages through in-house EML chips and SiPh solutions, and TFC Optical specializes in optical components and connectors, delivering net margins close to 40%. TFC also collaborates with NVIDIA on CPO.

Looking at H1 2025 results, Innolight posted revenue of RMB 14.789 billion (+36.95%) with net profit of RMB 3.995 billion (+69.4%). Eoptolink was even steeper: revenue of RMB 10.437 billion (+282.64%), net profit of RMB 3.942 billion (+355.68%).[6]

Those growth rates are impressive. But here is the important question: who in this value chain is actually capturing the most profit?

Key point: The growth of Chinese optical module companies came from playing the “plumber” role in AI data centers. They don’t design the building, but the building doesn’t run without the plumbing. The question is where the critical components inside that plumbing come from.

What matters is not shipment volume but which layer retains the profit. China assembles the 800G modules, but the highest excess margins go to whoever controls the DSP and EML. That is what we need to examine.

3. Value Chain Structure: Where Margins Diverge Between Modules and Chips

Break down a single optical module and you get four main components.

• Laser source (EML, VCSEL, or CW laser): The core component that converts electrical signals to light. Think of it as the “engine” of the optical module.

• Photodetector (PD): The receiver that converts light back to electrical signals.

• DSP (Digital Signal Processor): The brain that cleans up signals, corrects errors, and aligns timing. Think of it as a highway traffic control system.

• Optical components + PCB + packaging: Lenses, connectors, substrates, housings. Assembling these is the primary job of module companies.

This is where margin structures diverge sharply. Segment-level margins are not publicly disclosed, but company-level financials reveal the structural gap.

Starting with DSP chips: Broadcom’s company-wide GAAP gross margin is approximately 68% (FY2025). This figure includes the VMware software business, and the optical DSP segment margin is not broken out separately. Given the design IP-based, foundry-outsourced model, segment margins are presumably high, but exact figures are unavailable.

For laser chips (EML/CW): Lumentum’s company-wide GAAP gross margin was 28% in FY2025, rising to 34% by FY2026 Q1 as EML shipments surged. Coherent posted 35.2% for FY2025. Both companies mix optical components with industrial/materials segments, so the standalone EML chip margin could be higher or lower than the company average. InP epitaxy and processing require highly specialized fab technology.

Module assembly is the most transparent layer because Chinese module companies are publicly listed. Innolight posted 20 to 22% net margins in 2023 to 2024, and Eoptolink hit 33%, both all-time highs driven by the AI demand surge.[1] Meanwhile, TFC Optical, a component specialist, delivers net margins close to 40%. Even within the same optical value chain, the profit structures of components/chips and module assembly are clearly different.

One thing needs to be addressed here, though. Looking at 2023 to 2024 net margins, module companies actually outperformed chip suppliers. Eoptolink posted 33% and Innolight 22%, while Coherent and Lumentum ran at a loss or single-digit net margins on a company-wide basis over the same period. This looks like a contradiction, but it resolves once you separate the cycle from the structure. The current high margins at module companies come from temporary pricing power created by 800G capacity shortage. Demand is surging but only two or three companies can produce at this scale and schedule, giving module makers a pricing premium they would not normally have. Coherent and Lumentum, meanwhile, were weighed down by telecom weakness and M&A integration costs at the company level. That said, both are recovering fast as AI datacenter revenue kicks in. Lumentum posted +58% YoY revenue growth in FY2026 Q1, with GAAP gross margin climbing from 28% in FY2025 to 34%. Coherent improved non-GAAP EPS by +191% YoY in FY2025. Chip-side margin resilience is already kicking in. And the picture shifts further when the cycle normalizes. As 1.6T mass production ramps in 2026 to 2027 and second-tier players like Accelink and HG Genuine add capacity, module pricing will likely come under pressure quickly. Chip IP like DSPs and EMLs, by contrast, has a structurally limited number of alternative suppliers, giving these businesses stronger margin resilience through the cycle.

Selling the same 800G transceiver, the profit structure for a module assembler and a laser chip supplier look completely different.

Over the long term, what matters is not shipment volume, but where excess profit stays through the cycle. Module assembly has relatively lower barriers to entry. Even at the 800G/1.6T level, which requires sophisticated production capabilities, the structure of buying key components (DSP, laser) externally and assembling them is fundamentally “parts cost + assembly cost + margin.” As competition intensifies, margins compress. DSPs and EMLs, by contrast, have design IP and process know-how as their moats. With very few alternative suppliers, pricing power sits with the component makers.

Understanding this structure changes how you see the growth of Chinese module companies. Revenue and market share are dominant, but the highest-margin, hardest-to-replace layers in the value chain are still held by U.S. and Japanese companies.

There is one more variable missing here. Two components, DSP and EML. Look closely at the supply structure for these two, and what emerges is not just a margin gap but a question of who holds whose leash.

Key point: Chinese optical module companies are the best in the world at 800G/1.6T mass production. But the margin gap between upstream (DSP, EML) and downstream (module assembly) is structural. Module market share does not equal value chain dominance.

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4. DSP and EML: Two Chokepoints

4-1. DSP: The Irreplaceable Brain

The DSP is the brain of the optical module. It converts high-speed optical signals to digital, filters noise, and aligns timing. In 800G transceivers, the DSP accounts for a significant portion of total module power consumption and is the key determinant of module performance.

This market is effectively a duopoly.

• Broadcom: Sian2 DSP. The standard in NVIDIA’s supply chain. Used primarily by Innolight and Eoptolink.

• Marvell: Spica (800G) / Ara (1.6T) PAM4 DSP families. Adopted by hyperscalers including Microsoft and Google.[14]

There is currently no mature Chinese domestic alternative for DSPs.[7] The DSP ecosystem has high IP barriers and a closed architecture. The issue is not just whether you can design a chip. PAM4 (Pulse Amplitude Modulation 4-level) signal processing algorithms, FEC (Forward Error Correction) IP, and years of accumulated customer-specific optimization data are all barriers to entry.

What is notable here is that this DSP dependency itself is why Chinese companies are aggressively pushing LPO (Linear Pluggable Optics). LPO removes the DSP from inside the module and has the switch chip handle signal processing instead. Eliminating the DSP reduces power and cuts dependence on Broadcom/Marvell. More on this in Section 6.

4-2. EML: The Physical Bottleneck

The EML (Electro-Absorption Modulated Laser) is the light source of the optical module. It is the core device that converts electrical signals to light, and is the most commonly used laser type in 800G and above single-mode transceivers.

A serious bottleneck is forming here.

According to TrendForce, NVIDIA has strategically pre-allocated production capacity at major EML suppliers, pushing EML lead times out past 2027.[5] From NVIDIA’s perspective, this is a rational move to secure stable supply for its GPU cluster modules. But it has made EMLs harder for everyone else to get.

Five companies dominate the EML market: Lumentum, Coherent, Mitsubishi, Broadcom, and Sumitomo (though Sumitomo has higher exposure to DFB/VCSEL than datacenter EMLs). For 200G/lane EMLs (the next-generation spec required for 1.6T transceivers), Lumentum is the most aggressive front-runner, while Broadcom and Coherent have also officially presented 200G EML capabilities.[8]

Chinese companies are attempting EML localization. Zetta Semiconductor announced a mass-producible 100G PAM4 EML at OECC 2025, and followed up with a 200G per wavelength PAM4 EML at ACP in November of the same year.[9] Changguang Huaxin has been supplying 56G PAM4 EMLs since 2023. Accelink is the only domestic company producing 25G EMLs in-house.[2] But mass production at the 100G/lane and 200G/lane level still has a long way to go. The domestic localization rate for 25G and above high-speed optical chips in China remains below 15%.[7]

The bottleneck structure is clear. DSPs are an effective duopoly between Broadcom and Marvell, with no mature Chinese domestic alternative. EMLs (100G+) are supplied by roughly five companies, with a Chinese localization rate below 15% and mass production still in early stages. CW Lasers from Lumentum, Yuanjie, Shijia and others are in relatively comfortable supply as the technology is mature. VCSELs are led by Broadcom (including Lumentum OEM) and the Coherent (formerly II-VI) family, with Chinese companies attempting to enter.

CW lasers are in a comparatively better position. Their simpler structure and larger supplier base mean that using CW lasers as external light sources in silicon photonics modules, instead of EMLs, is emerging as an alternative to the EML shortage.[5]

Key point: DSP and EML are the two structural dependency points for the Chinese optical module industry. DSP is a Broadcom/Marvell duopoly. EML is a physical supply shortage. Neither bottleneck is likely to be resolved in the short term, and this is the background for Chinese companies aggressively pushing LPO and silicon photonics.

5. The Truth About Southeast Asian Factories: Tariff Avoidance or Real Manufacturing?

Chinese optical module companies have been moving production to Southeast Asia for some time. The direct trigger was U.S. Section 301 tariffs (25% on Chinese-origin products).[4]

Looking at current overseas production bases: Innolight operates Thailand as its primary base for North American shipments and has added a Mexico facility. Eoptolink also uses Thailand as its main base, with 1.6T volume ramp-up in progress there. Hisense has facilities in Thailand alongside a direct production site in New Jersey, U.S. CIG and Linktel have production bases in Malaysia.

The logic is straightforward. Chinese-origin products face Section 301 tariffs (25%) directly, while products made in Thailand or Malaysia may face different treatment depending on country-of-origin determination and whether substantial transformation is recognized. That said, producing in Southeast Asia does not automatically mean non-Chinese origin classification.

The reality, however, is not that clean.

Issue 1: Components still come from China and Japan

Thai and Malaysian factories “assemble” modules, but a significant portion of key components (ceramic substrates, optical subassemblies, PCBs) are imported from China or Japan. Ceramic substrates, for example, often come from Japan’s Kyocera or Germany’s Heraeus. For the finished product to qualify as Thai in origin, “substantial transformation” must occur in Thailand.

Issue 2: U.S. CBP is stepping up enforcement

U.S. Customs and Border Protection (CBP) is intensifying its crackdown on Southeast Asian transshipment. Investigations into country-of-origin fraud, where Chinese products are relabeled in Southeast Asia for export, are underway, with Vietnam and Malaysia as primary targets.[10]

As of 2026, enforcement has intensified further. The DOJ launched a dedicated trade fraud task force in 2025, and CBP country-of-origin fraud investigations have been increasing in frequency.[11]

Issue 3: The ambiguous boundary of “substantial transformation”

For optical modules, whether the work done at Thai/Malaysian factories qualifies as “substantial transformation” is a gray area. It is unclear whether simply placing components on a PCB and putting them in a housing counts as “transformation,” or whether optical alignment, burn-in testing, and calibration must also be included. CBP makes determinations on a case-by-case basis, so risk remains for module companies.

In practice, the Thai factories of Innolight and Eoptolink perform processes well beyond simple assembly. Optical alignment, high/low temperature testing, firmware loading, and final inspection all happen in Thailand, so the “substantial transformation” argument is not entirely weak. But with U.S. policy trending toward stricter enforcement, this remains a variable to watch.

HG Genuine’s approach is also interesting. It claims that 400G single-mode products using in-house EML chips or silicon photonics solutions achieve $25 to 30 in cost savings compared to competitors.[2] The strategy is to absorb tariff impact through a combination of chip self-sufficiency and overseas production.

Key point: Southeast Asian factory migration is largely motivated by tariff avoidance, but substantial manufacturing processes have been relocated as well. However, component origin issues and intensifying U.S. CBP enforcement remain risk factors from 2026 onward.

6. Can LPO/SiPh Change the Structure?

Tariff risk is a short-term variable. What changes this structure over the medium to long term is technology.

Three technology paths could alter the “assembly powerhouse, chip desert” structure: LPO, silicon photonics (SiPh), and CPO (Co-Packaged Optics). Each affects the value chain structure differently. The diagram below shows how light source architecture evolves across generations. Moving from Gen 1 (EML Pluggable) to Gen 2 (CW+SiPho) relieves the EML bottleneck. Moving to Gen 3 (CPO), the module itself disappears.

Figure 3: Light Source Architecture Evolution in Silicon Photonics

6-1. LPO: Eliminating the DSP

LPO (Linear Pluggable Optics) removes the DSP from inside the optical module and has the switch chip handle signal processing instead. The module becomes “dumber,” but power drops and cost comes down.

Why Chinese companies are pushing LPO hard is clear.

1. DSP cost makes up a significant portion of module BOM (bill of materials). Removing it improves cost competitiveness.

2. Module-level BOM dependence on Broadcom/Marvell decreases. (System-level dependence remains, but the chip the module maker directly purchases is gone.)

3. Both Innolight and Eoptolink are founding members of the LPO MSA (Multi-Source Agreement).

But LPO is not a complete solution.

LPO does not eliminate Broadcom/Marvell dependence. It moves the DSP function from inside the module to the switch ASIC. The company making that switch chip is still Broadcom or Marvell. Module-level BOM dependence drops, but system-level silicon dependence remains. LPO also only works over short distances (mainly intra-rack, a few to tens of meters). Longer reaches still require DSP-based retiming. Standardization is also incomplete, requiring per-customer interoperability validation.

6-2. SiPh: Reducing EML Dependence

Silicon photonics (SiPh) integrates optical circuits on a silicon wafer. It can leverage existing semiconductor CMOS processes, making it favorable for mass production.

In SiPh modules, CW lasers (continuous wave lasers) serve as the external light source instead of EMLs, and modulation is handled by ring modulators or MZI (Mach-Zehnder Interferometer) modulators on the silicon chip. CW lasers are structurally simpler than EMLs and have more suppliers, enabling a workaround for the EML bottleneck.[5]

SiPh penetration in the 800G market was about 10% in 2024 and is expected to reach 20 to 30% in 2025. Industry estimates suggest it could reach 30 to 40% in 1.6T once the technology matures.[12]

Chinese companies’ SiPh capabilities are also coming up fast.

• Innolight: Global number one in 800G SiPh module market share. SiPh mix above 40% in 2025.[13]

• Eoptolink/Innolight: Some Chinese brokerage analyses estimate SiPh chip self-sufficiency above 80%, though official confirmation is limited.[13]

• Accelink: Has SiPh subassembly capability through TOSA/ROSA vertical integration.

But SiPh foundries (wafer fabrication) are still centered in the U.S. and Europe. GlobalFoundries (GFS), Tower, and TSMC are the major foundries, and SiPh-dedicated foundry capacity in China is still at an early stage.

6-3. CPO: Questioning the Module Maker’s Reason to Exist

CPO (Co-Packaged Optics) places the optical engine inside the same package as the switch chip. The transceiver module disappears entirely, and optics move down to the chip level.

NVIDIA’s unveiling of its own CPO switch at GTC 2025 made this direction concrete. At the time of the GTC 2025 announcement, a 3.5x improvement in power efficiency over conventional pluggables was presented. NVIDIA’s current product page now claims 5x improvement.[14][15] Network resiliency improves 10x, resulting in 5x sustained application runtime. NVIDIA targets Spectrum-X Photonics for commercial availability in 2H26.

If CPO becomes widespread, the role of optical module assemblers fundamentally changes. Pluggable modules shrink, and optical engine plus chip packaging capability become what matters. This favors chip companies like Broadcom, Marvell, and NVIDIA.

That said, CPO is unlikely to replace pluggables quickly. It is currently applied only in specialized AI cluster environments. General-purpose data centers still prefer the flexibility of pluggables (easy swap, upgrade). Commercial deployment begins in 2026, but pluggable shipment volumes are unlikely to drop significantly over the next three years. CPO and pluggables will coexist for a substantial period.

Summary: How the Three Technologies Affect Chinese Companies

LPO favors maintaining “assembly powerhouse” status. Removing DSP cost lowers module cost. But it only partially addresses “chip desert.” The dependency shifts from the module-internal DSP to the switch chip, and it only works over short-reach links. SiPh also favors the “assembly powerhouse” direction. It leverages CMOS mass production capability and routes around the laser bottleneck by using CW lasers instead of EMLs. But SiPh foundries (GFS, Tower, TSMC) are overseas, so the form of dependency changes rather than disappearing. CPO is the opposite. It reduces demand for module assembly itself, making it unfavorable for Chinese module companies over the medium to long term. CPO is a domain led by chip companies (NVIDIA, Broadcom, Marvell).

In the end, LPO and SiPh are favorable for Chinese companies in the near term. SiPh in particular can route around the EML bottleneck while using CMOS production capability, which is precisely why Innolight and Eoptolink are investing heavily. But if CPO expands over the medium to long term, a structural shift that reduces the value-add of “module assembly” itself could arrive.

Key point: LPO and SiPh lower Chinese optical module companies’ DSP/EML dependence, but dependence on the top of the value chain (chip IP, foundries) does not fully disappear. CPO is the medium-to-long-term variable that could redefine the role of module companies altogether.

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7. Closing

In the span of a decade, Chinese optical module companies have claimed 7 of the top 10 seats and secured core supplier status in the AI demand segment. Thanks to the 800G capacity shortage, module companies are currently posting higher net margins than chip suppliers. When the cycle is good, even the plumber makes money.

But cycles do not last forever. As 1.6T mass production ramps and second-tier players add capacity, module pricing will inevitably come under pressure. DSPs, EMLs, and foundries, by contrast, have a structurally limited number of alternative suppliers, giving them stronger margin resilience when the cycle turns. Over the long term, excess profit stays not in assembly, but in chip IP.

Optical interconnects in AI data centers are moving closer and closer to the chip level, and that direction will redraw the division of roles between China and the U.S.

8. References & Sources

[1] 2024 Global Top 10 Optical Module Suppliers : LightCounting 2024 global optical module Top 10 rankings and Chinese company performance

[2] Optical Communications Industry Deep Dive : Chinese optical module company 2024 financials and technology overview (Chinese brokerage research compilation)

[3] Pluggables, Power, and Geopolitics: 800G/1.6T Optical Transceiver Battle : 800G market size, NVIDIA supply chain Chinese company share estimate (secondary analysis)

[4] LightCounting: Chinese transceiver vendors dominated the market : China domestic market size $2-3B, Southeast Asia factory migration background

[5] TrendForce: AI Data Centers Ignite Laser Shortage : 800G+ shipment projections, NVIDIA EML pre-allocation, CW laser as alternative

[6] Nvidia Orders Surge: InnoLight and Eoptolink Dominate 800G : Eoptolink H1 2025 financials (+282.64%), 1.6T product status (industry channel information)

[7] CIOE: DSP bottleneck and optical chip localization : DSP localization bottleneck, 25G+ optical chip localization rate discussion

[8] Top Silicon Photonics Stocks 2026 : EML market structure overview (secondary analysis)

[9] Zetta Semiconductor: 100G PAM4 EML Breakthrough : Mass-producible 100G PAM4 EML (OECC 2025)

[10] US Tariff Updates: China, Southeast Asia scrutiny : CBP transshipment crackdown, country-of-origin fraud investigation trends

[11] DOJ: Trade Fraud Task Force : DOJ/DHS trade fraud task force launch

[12] Optical Module Market Deep Dive : SiPh penetration projections (800G 20-30%, 1.6T 30-40%, secondary analysis)

[13] Optical Module Research Notes : Innolight SiPh mix estimates, company-level supply chain details (Chinese brokerage channel check)

[14] Marvell PAM4 Optical DSP Portfolio : Marvell PAM4 DSP product lineup (Spica, Ara, Nova, Perseus)

[15] NVIDIA Silicon Photonics: CPO Product Page : NVIDIA CPO 5x power efficiency, 10x resiliency improvement (current product spec)

[16] The Silicon Photonics Light Source War: Same Problem, Three Solutions (Small Cap): PhotonCap’s Article

Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

Contents

1. Intro: Why this paper matters

2. Background: quantum computers and ECDLP, from the basics

3. The Google whitepaper in detail: 1,200 logical qubits, 9 minutes

4. Bitcoin vs Ethereum: vulnerability structures are not the same

5. Quantum hardware platforms and the main players

6. The “dormant coin” problem and digital salvage

7. The state of the Post-Quantum Crypto ecosystem

8. Closing

9. References & Sources

   If you’d like to support my independent research and creative journey, please consider a “pledge.” Your support keeps the photons moving.

1. Intro: Why this paper matters

On March 31, the Google Quantum AI team published a whitepaper titled “Securing Elliptic Curve Cryptocurrencies against Quantum Vulnerabilities: Resource Estimates and Mitigations.”[1] Ryan Babbush (Director of Research, Google Quantum AI) and Hartmut Neven (VP of Engineering, Google Quantum AI) are the lead authors, with Justin Drake (Ethereum Foundation) and Dan Boneh (Stanford) among the co-authors.

Here’s why this matters. Up to now, the “quantum computers will break Bitcoin” narrative has floated around on vague timelines and unverified numbers. This paper is different. It provides concrete quantum resource estimates while making those estimates cryptographically verifiable through a zero-knowledge proof. The details of the attack stay hidden, but the credibility of the estimates is mathematically backed. In the field of quantum cryptanalysis, this kind of responsible disclosure is essentially a first.

The market reacted immediately. Quantum Resistant Ledger (QRL) +50%, Cellframe (CEL) +40%, Abelian (ABEL) +25%.[2] Bitcoin and Ethereum themselves moved only modestly. The price action reflects a very specific message: “Not dangerous right now, but whoever isn’t ready is going to have a problem.”

In this piece, I’ll walk through the technical substance of the paper, how Bitcoin and Ethereum differ in their quantum vulnerabilities, which companies are building the hardware (and which foundries they lean on), and what the PQC transition implies for the crypto value chain.

2. Background: quantum computers and ECDLP, from the basics

Most cryptocurrencies, Bitcoin and Ethereum included, rely on Elliptic Curve Cryptography (ECC). Specifically, the security backbone is the Elliptic Curve Discrete Logarithm Problem (ECDLP) defined over the secp256k1 curve.[1]

Put simply: generating a public key from a private key is easy, but inverting that operation to recover the private key from the public key is, for classical computers, effectively impossible. That asymmetry is what underwrites ownership in the system. “Only I can spend my coins” rests on that one-way math.

One thing worth clarifying. This asymmetry isn’t “mathematically impossible,” it’s “computationally infeasible.” Breaking 256-bit ECDLP on a classical computer would take longer than the age of the universe. But Shor’s Algorithm, introduced by Peter Shor in 1994, showed that a quantum computer can solve this problem in polynomial time.[1]

The question has always been “when.” Actually running Shor’s algorithm requires enough error-corrected logical qubits (stable qubits built from hundreds of physical qubits each), and the most advanced quantum processor today, Google Willow, has only 105 physical qubits.[3] That’s why the industry consensus has been “still far away.”

Timeline of ECDLP-256 quantum resource estimates

The Google paper just pulled that timeline in significantly.

Bottom line: the physical qubit count needed to break ECDLP-256 dropped from the prior best estimate of around 9 million to under 500,000, roughly a 20x reduction.

3. The Google whitepaper in detail: 1,200 logical qubits, 9 minutes

Resource estimates: two circuit variants

The Google team’s main result is two quantum circuit variants.[1]

The Toffoli gate count (Toffoli being the most expensive basic operation in fault-tolerant quantum computing) determines execution time. On a surface-code based superconducting qubit architecture, assuming a 10-microsecond error correction cycle reaction time, 70 million Toffolis take about 18 minutes, and 90 million take about 23 minutes.[1]

One more detail. Shor’s algorithm lets you precompute the first half of the calculation (the part that depends only on protocol parameters) and hold that “primed state.” Once a public key is exposed, you only run the second half. That brings the real attack time down to about 9 minutes.[1]

Bitcoin’s average block time is 10 minutes. At 9 minutes, the probability of a successful attack is roughly 41%.[1]

Verification through a Zero-Knowledge Proof

This is the most unusual part of the paper. The Google team did not publish the detailed structure of the quantum circuits. Instead, using the SP1 zero-knowledge virtual machine (zkVM), they issued a ZK proof that verifies “we possess a circuit of this size, and this circuit correctly computes point addition on the secp256k1 elliptic curve across 9,000 random inputs.”[1]

Why this approach? The paper explains it directly. The quantum cryptanalysis field has an odd culture. Developing and optimizing quantum algorithms is academically prestigious, but discussing the downstream consequences of those algorithms is often treated as taboo.[1] The Google team takes the position that it’s time to move past that. Keep the attack details private, but make the scale of the threat cryptographically verifiable. This is the first time the “Responsible Disclosure” principle from traditional security has been applied to quantum cryptanalysis.

Fast-clock vs Slow-clock: architecture determines attack type

The paper’s other key contribution is classifying quantum computer architectures by “clock speed” into two categories.[1]

Fast-clock CRQC (Cryptographically Relevant Quantum Computer): Superconducting, photonic, silicon spin qubits. Error correction cycles around 1 microsecond. Can solve ECDLP in minutes, making on-spend attacks (intercepting in-flight transactions) viable.

Slow-clock CRQC: Neutral atoms, ion traps. Fundamental operation speed 100 to 1,000x slower than fast-clock. Solving ECDLP takes hours to days, so only at-rest attacks (targeting dormant wallets with long-exposed public keys) are viable.

Don’t read this as “Fast-clock is the better quantum computer.” Fast vs Slow refers to the error correction cycle speed, not to qubit quality or scalability. Ion traps (Slow-clock) actually hold the world record for gate fidelity across all architectures, and neutral atoms have the edge in scaling qubit counts quickly.[1] Superconducting (Fast-clock), by contrast, has fast gates but limited qubit connectivity and requires millikelvin cryogenics. The paper introduces this distinction not to rank architectures, but to analyze what kind of attack the first CRQC will be able to execute.

Why does the distinction matter? Because the nature of the shock hitting the crypto ecosystem depends entirely on which architecture produces the first CRQC. The paper lays out two scenarios.[1]

Bottom line: The Google paper converts the old “someday quantum will be a threat” conversation into something concrete: “500,000 physical qubits, 9 minutes,” plus architecture-specific scenarios.

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4. Bitcoin vs Ethereum: vulnerability structures are not the same

When talking about quantum threats, lumping “all crypto is at risk” together is a mistake. Bitcoin and Ethereum have fundamentally different designs, and their quantum vulnerabilities differ accordingly.

Bitcoin: risk depends on the script type

Bitcoin uses the UTXO (Unspent Transaction Output) model. Coin ownership is defined by a locking script, and depending on the script type, when and how the public key gets exposed varies.[1]

Based on Table I of the whitepaper, here’s the vulnerability breakdown by Bitcoin script type.[1]

*Safe only if no address reuse. Any reuse writes the public key on-chain and converts Safe to Vulnerable.

The key points:

P2PK (Pay-to-Public-Key): The public key is written directly into the locking script. Vulnerable to both at-rest and on-spend attacks. About 1.7 million BTC is locked this way, including Satoshi-era mining rewards.[1]

P2PKH / P2WPKH: Only the hash of the public key goes on-chain. The public key is revealed when the coin is spent, so before the first spend, at-rest attacks can’t touch it. On-spend attacks are still possible.

P2TR (Pay-to-Taproot): Introduced by the 2021 Taproot upgrade, P2TR exposes the public key directly in the locking script. Privacy and efficiency gains, but a regression to P2PK-level exposure from a quantum security standpoint.[1] As of 2025, 21.68% of Bitcoin transactions used P2TR.[1]

Address reuse: Even with hash-based scripts like P2PKH or P2WPKH, if you spend part of the coins at an address and leave the rest, the public key ends up on-chain. At-rest immunity is gone from that moment. The paper notes that major exchanges like Binance, Robinhood, and Bitfinex reuse addresses heavily.[1]

Overall, about 6.9 million BTC (roughly 33% of total supply) is currently vulnerable to at-rest attacks.[1]

Ethereum: five attack vectors

Ethereum’s quantum vulnerabilities are far more complex than Bitcoin’s. If Bitcoin is a “digital ledger,” Ethereum is closer to a “world distributed computer,” and the attack surface is correspondingly larger.[1]

The paper classifies Ethereum’s vulnerabilities into five categories.[1]

The one that caught my attention most is Admin Vulnerability. Stablecoin issuers (USDT, USDC, etc.) protect minting authority with ECDSA-based admin keys. Break one of those keys and you can mint unlimited tokens, which would cascade into every DeFi lending market using those tokens as collateral.[4]

Another one worth noting is Data Availability Vulnerability. Ethereum’s DAS (Data Availability Sampling) mechanism depends on KZG commitments, which are vulnerable to on-setup attacks. Once a quantum computer recovers the “toxic waste” (the secret values that were supposed to be destroyed during the trusted setup ceremony), classical computers alone can forge data availability proofs from that point forward. The paper calls this attack “potentially tradable”, meaning a one-time quantum computation produces a reusable exploit that can be sold.[1][4]

Ethereum does have some advantages over Bitcoin here. The 12-second block time (vs Bitcoin’s 10 minutes) makes on-spend attacks much harder even for fast-clock CRQCs under current estimates. And the ecosystem already has substantial private mempool infrastructure like TEE-based BuilderNet (private mempool: submitting transactions directly to trusted block builders instead of the public queue).[1]

Bottom line: Bitcoin’s key variable is script type; Ethereum has five distinct attack vectors spanning the account model, smart contracts, PoS, and DAS. “Crypto is all at risk” is too coarse.

So what about traditional finance?

A natural question at this point: “If quantum computers break ECDLP, isn’t banking, SWIFT, and HTTPS all going down too, not just Bitcoin?” Fair point. This was the most common pushback from the crypto community after the paper dropped. CZ (Binance founder) posted on X that “all crypto has to do is upgrade to Quantum-Resistant algorithms. No need to panic,”[20] and crypto commentator Quinten Francois went further: “If quantum kills Bitcoin, it also kills the global banking system, SWIFT transfers, stock exchanges, military communications, nuclear command systems, every HTTPS website on earth.”[20]

Not wrong. TLS (web traffic encryption), SSH (server access), electronic passports, digital signature infrastructure all depend on ECDLP or RSA, and quantum computers threaten all of them.[1]

But here’s what the paper points out head-on. The upgrade dynamics are completely different.

Traditional finance systems are centralized. JP Morgan’s CISO makes a call, the security team swaps TLS certificates, and customers never need to know. Google started its PQC transition back in 2016 and has now published a timeline to migrate all authentication services by 2029.[1] NIST’s PQC standards (ML-KEM, ML-DSA) are finalized, and enterprise adoption roadmaps are rolling out.

Blockchains can’t do that. There’s nobody with a switch that flips the protocol. Changes require community consensus, and without consensus, you get a chain split. Think about how slow Bitcoin governance has been: Taproot alone took years of debate before activation.

And critically, traditional finance has mechanisms to reverse bad transactions. Hacked bank transfers can be recovered through dispute processes. Blockchains are designed around transaction irreversibility. Once assets move via a quantum attack, there’s no recovery path.[1]

Put plainly: quantum threats aren’t unique to crypto. But crypto is the most exposed, not because the cryptography is weaker, but because upgrades are structurally slow and there’s no recovery mechanism when things fail.

Bottom line: Traditional finance relies on the same cryptography, but centralized organizations can upgrade quietly and have transaction reversal mechanisms. Blockchains have neither. Same threat, different exposure.

Before moving to the quantum hardware side, it’s worth sitting with this structural asymmetry. Which architecture produces the first quantum computer changes the character of the shock the crypto ecosystem has to absorb.

5. Quantum hardware platforms and the main players

The Fast-clock / Slow-clock frame from the Google paper isn’t just theory. Which companies are building which architectures right now determines both the type and the timing of the threat crypto will face.

Fast-clock architectures (on-spend attacks viable)

Superconducting qubits

The most mature architecture. Josephson junction based superconducting circuits operating at ultra-low temperatures (~15mK).

Google Quantum AI (GOOGL): The authors of this paper. Processors manufactured at Google’s own fab in Santa Barbara. In late 2024, they achieved verifiable quantum advantage with the 105-qubit Willow chip.[3] Currently at the forefront of quantum cryptanalysis resource estimation.

IBM Quantum (IBM): Own fab at Yorktown Heights. Operating the 156-qubit Heron and 120-qubit Nighthawk processors. Provides cloud access through the IBM Quantum Network with 300+ participating institutions.[5]

Rigetti Computing (RGTI): Own Fab-1 in Fremont, CA. Accessible through AWS Braket and integrated with NVIDIA CUDA-Q.[5]

IQM Quantum Computers: Finland-based, manufactured at VTT cleanrooms. Core participant in EU quantum initiatives. Private.

Photonic qubits

Uses photons as qubits. Photons don’t feel heat or electromagnetic interference, so cryogenic constraints are relatively relaxed, and standard optical fiber allows chip-to-chip networking, which is a big advantage for modular scaling.

PsiQuantum (private, $7B valuation): Runs a dual foundry strategy. High-volume manufacturing of the 300mm Omega silicon photonic chipset happens at GlobalFoundries (GFS) Fab 8 in Malta, NY, on a commercial semiconductor process,[6] while 200mm SiPh development and production ramp runs in parallel at SkyWater Technology (SKYT)‘s Minnesota fab.[18] If GFS is the volume axis, SkyWater is the flexible custom-process axis based on its TaaS (Technology as a Service) model. SkyWater CEO Thomas Sonderman has gone as far as calling his company a “quantum foundry,” signaling just how actively they’re leaning into this business.[19] Breaking ground on data-center-scale quantum compute centers in Brisbane and Chicago. The $1B Series E was led by NVIDIA NVentures, BlackRock, and Temasek, and they’ve advanced to the final stage of the DARPA QBI (Quantum Benchmarking Initiative).[7] If you’re a PhotonCap reader, the GFS silicon photonics platform is familiar territory: PsiQuantum is that platform’s flagship quantum computing customer.

Xanadu (XNDU): Listed on Nasdaq/TSX simultaneously on March 27, 2026, via SPAC merger with Crane Harbor Acquisition Corp. $3.1B valuation.[8] AMD participated in a $275M PIPE, and Xanadu is in negotiations with the Canadian and Ontario governments for up to C$390M.[9] Chip fabrication runs on Tower Semiconductor (TSEM)‘s SiPh platform, where they’ve co-developed a custom SiN-based process and completed multiple tapeouts.[10] imec (Belgium) handles ultra-low-loss SiN wafer R&D, and Applied Materials (AMAT) collaborates on a 300mm process for superconducting TES detectors.[11][12] Target: build a quantum data center in Toronto by 2030.

The photonic quantum foundry landscape is interesting. PsiQuantum is GFS (300mm) + SkyWater (200mm), and Xanadu leans primarily on Tower’s SiPh platform. Foundries that compete in the data-center silicon photonics market are now splitting customers in the new quantum computing demand pool too.

Silicon spin qubits

The big advantage: compatibility with existing CMOS processes.

Intel (INTC): Tunnel Falls 12-qubit processor manufactured at Intel’s Oregon fab. They’re emphasizing CMOS process compatibility and trying to carry over large-scale production know-how to quantum chips.

Diraq (private): UNSW spin-out. Manufactures silicon spin qubit chips on GlobalFoundries (GFS)‘ 300mm process. Also participating in DARPA QBI.

Slow-clock architectures (at-rest attacks only)

Ion traps

Confine individual ions in electromagnetic fields and implement quantum gates with lasers. Gate fidelity is extremely high, but fundamental operation speed is 100 to 1,000x slower than superconducting.[1]

IonQ (IONQ): In 2025, became the first quantum computing company to surpass $100M in annual GAAP revenue.[5] Executed around $2.5B in acquisitions over 18 months, including Oxford Ionics ($1.075B), ID Quantique ($250M), and Capella Space ($318M).[5] Partnerships with NVIDIA, AWS, and AstraZeneca, and a roadmap targeting a CRQC with roughly 20,000 qubits by 2028. Self-manufactured (Maryland).

Quantinuum (private, filed S-1 for IPO): Honeywell subsidiary. Completed a $600M Series B at $10B valuation.[5] Partnerships with NVIDIA NVentures and Microsoft, and recently announced a 800x error reduction demonstration. Self-manufactured.

Neutral atoms

Arrays of individual atoms held by optical tweezers serve as qubits. The strength is rapid qubit count scaling.

QuEra Computing (private): Boston-based. Backed by NVIDIA NVentures, AWS, and Google. Targeting a 100 logical qubit system in 2026.[5]

Pasqal (private): Paris-based. NVIDIA CUDA-Q integration. Deployed at European HPC centers.

Atom Computing (private): Set a record of 24 entangled logical qubits in partnership with Microsoft.[5] Selected for DARPA US2QC.

Infleqtion (INFQ): Formerly ColdQuanta. Listed via SPAC merger in February 2026 at a $1.8B valuation.[5] Runs a dual revenue model combining quantum computing with defense and sensing contracts.

Summary: quantum hardware platforms, companies, and foundries

Here’s a consolidated view of the companies covered above, organized by architecture.

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One thing worth flagging from this table. The Fast-clock photonic and silicon spin players lean heavily on commercial semiconductor foundries: PsiQuantum-GFS/SkyWater, Xanadu-Tower, Diraq-GFS. The Slow-clock side (ion trap, neutral atom) mostly manufactures in-house. This isn’t a coincidence. Photonic and silicon spin architectures are compatible with existing CMOS/SiPh processes, while ion trap and neutral atom systems revolve around vacuum chambers and laser systems that have nothing to do with semiconductor fabs.

Cross-platform infrastructure: NVIDIA’s position

NVIDIA (NVDA) doesn’t build its own QPU (Quantum Processing Unit). Instead, it’s running through the entire quantum ecosystem on three axes.

First, NVentures (venture investment): In a single week in 2025, NVIDIA backed Quantinuum (ion trap), QuEra (neutral atom), and PsiQuantum (photonic) consecutively.[13] A portfolio strategy covering every major hardware architecture.

Second, CUDA-Q: A quantum-GPU hybrid programming framework. Lets developers program CPUs, GPUs, and QPUs from a single codebase.[14]

Third, NVQLink: A direct QPU-GPU connection architecture announced at GTC Washington in October 2025. Launch partners include 16 quantum hardware companies (IonQ, Rigetti, Quantinuum, QuEra, etc.) and quantum control system vendors like Keysight and Zurich Instruments.[14]

There’s an episode worth flagging. At CES January 2025, Jensen Huang said quantum computing was “15 to 30 years away from practical use.” A few months later at GTC, he publicly apologized and pivoted NVIDIA’s quantum strategy hard.[15] The surface reading is “Jensen changed his mind,” but personally I’m not sure that was a pure apology. The January comment cooled the whole quantum investment narrative, and a few months later NVIDIA shows up with NVQLink and NVentures investments, effectively broadcasting “even if quantum works, it runs inside the NVIDIA ecosystem.” Slowing the industry down while flexing leverage. Feels more like a calculated sequence than a change of heart.

Bottom line: The quantum hardware foundry/partner ecosystem is already deeply wired into the semiconductor value chain. PsiQuantum-GFS/SkyWater, Xanadu-Tower, Diraq-GFS, and NVIDIA’s cross-platform investment/infrastructure strategy are the key axes.

6. The “dormant coin” problem and digital salvage

The hardest quantum threat problem to solve is “dormant digital assets.”

PQC protects future transactions. But what about coins that have already been sitting on-chain with exposed public keys? Lost private keys, deceased owners, forgotten wallets.

More than 1.7 million BTC is locked just in Bitcoin’s P2PK locking scripts. Counting all script types, vulnerable dormant Bitcoin could reach roughly 2.3 million BTC.[1] At April 2026 prices, that’s tens to hundreds of billions of dollars.

Even if a fork introduces PQC protocols, these assets are “unfixable” fixed targets. A quantum attacker has no time pressure on them.

Community options

The paper lays out three options for the Bitcoin community.[1]

Do Nothing: Take no action. Quantum attackers eventually seize these coins, and a mass sell-off could destabilize the network economy.

Burn: Burn vulnerable dormant coins (make them unspendable). Clashes with Bitcoin’s core principle of ownership inviolability.

Hourglass: Attach an expiration timer to dormant coins. If they aren’t moved to a PQC address within a set period, they’re automatically burned.

Digital Salvage: a new policy framework

Here the paper introduces a genuinely interesting policy proposal: “Digital Salvage.”[1] Analogous to the legal framework for recovering treasure from sunken ships, classify quantum-computer-based recovery of dormant asset private keys as a regulated activity.

Because the legal status of such actions is currently ambiguous, there’s a real risk that nation-state actors or criminal organizations seize these assets first. The paper suggests a “legal backstop” structure: governments legalize salvage while simultaneously recommending that the Bitcoin community voluntarily burn vulnerable coins.[1]

Personally, I think this is the most controversial section of the paper. It collides head-on with Bitcoin’s “code is law” philosophy. But you also can’t ignore the reality that tens of billions of dollars in assets could end up in the hands of criminals or hostile state actors.

Bottom line: Dormant quantum-vulnerable Bitcoin is around 2.3M BTC. A “fixed target” that PQC migration can’t solve on its own. The community and policymakers have to choose from Do Nothing / Burn / Hourglass / Digital Salvage.

7. The state of the Post-Quantum Crypto ecosystem

So how is the response shaping up?

Ethereum Foundation: the 2029 roadmap

On March 24, 2026, the Ethereum Foundation launched pq.ethereum.org, formalizing the Post-Quantum Ethereum initiative.[16] This is the culmination of 8 years of work starting from STARK-based signature aggregation research in 2018.

The roadmap targets L1 quantum resistance by 2029 through 4 hard forks.[16]

The fact that co-author Justin Drake (Ethereum Foundation) participated directly in this paper is itself a signal of how seriously the Ethereum side treats the quantum threat.

Even after L1 protocol upgrades complete, thousands of already-deployed smart contracts, bridges, and L2 protocols each have to upgrade their code and rotate their keys independently.[4] That could take several more years.

Bitcoin: BIP-360

On the Bitcoin side, BIP-360 is under discussion. It would introduce a new script type called P2MR (Pay-to-Merkle-Root) that removes P2TR’s quantum vulnerability (direct public key exposure).[1] But this is mitigation against at-rest attacks only. Stopping on-spend attacks requires replacing the signature algorithm itself with PQC.

Bitcoin’s problem is its governance structure. There’s no central organization that can run a coordinated multi-year engineering program the way the Ethereum Foundation can. The last major cryptographic upgrade, Taproot, took years of debate before activation in 2021.[17] Bitcoin advocate Nic Carter has conceded that “elliptic curve cryptography is on the brink of obsolescence. Whether it’s 3 or 10 years, it’s over and we need to accept that.”[17]

PQC-native blockchains

Some blockchains are built on quantum-resistant cryptography from day one.

Quantum Resistant Ledger (QRL): +50% after the Google paper dropped.[2] Uses XMSS (eXtended Merkle Signature Scheme) hash-based signatures.

Abelian (ABEL): Lattice-based cryptography. +25%.[2]

Mochimo: PQC-dedicated blockchain.

Among existing blockchains, Algorand, XRP Ledger, and Solana have made experimental PQC deployments.[1] Notably, StarkNet uses hash-based SNARKs, which keeps it free from elliptic-curve-based vulnerabilities.[1]

Bottom line: Ethereum has a concrete 2029 roadmap in motion. Bitcoin’s governance structure makes a coordinated response harder. PQC-native chains like QRL and Abelian are starting to earn a market premium.

8. Closing

The core message of the Google Quantum AI whitepaper is straightforward. The resources needed to break cryptocurrency cryptography are far lower than we thought. And the gap keeps closing.

Bitcoin isn’t getting broken today. A 500,000-physical-qubit quantum computer doesn’t exist yet.

That said, it’s worth stepping back. The entity publishing this paper is Google Quantum AI. Google has one of the largest quantum computing research organizations and infrastructure bases in the world, and demonstrating the practicality of quantum computing is literally this team’s reason for existing. In other words, there’s no incentive for them to underestimate the threat. On the flip side, emphasizing the threat also helps justify quantum computing investment and drives PQC transition demand. Worth keeping in mind.

And the crypto ecosystem isn’t sitting still either. Cryptography is evolving in parallel with quantum hardware. NIST has already finalized PQC standards (ML-KEM, ML-DSA), the Ethereum Foundation has 8 years of PQ research behind it, and there’s strong mathematical backing that lattice-based and hash-based cryptography remain hard even for quantum computers. The quantum threat is real, but this isn’t a “one-sided race.” Attack and defense are co-evolving, and the outcome depends on who prepares faster.

The thesis the paper hammers home throughout captures this article’s conclusion: “The safest course of action for the cryptocurrency community is to begin preparing itself against quantum attacks immediately.”[1]

Distributed networks can’t update with a single switch. Banks can quietly swap cryptographic infrastructure, but blockchains are bound by transparency, immutability, and social consensus. Preparation takes years. Those years start now.

References & Sources

[1] Securing Elliptic Curve Cryptocurrencies against Quantum Vulnerabilities: Resource Estimates and Mitigations — Google Quantum AI original whitepaper (March 30, 2026)

[2] Quantum-resistant tokens jump 50% as Google flags risks to Bitcoin security — CoinDesk, coverage of QRL/CEL surge (April 1, 2026)

[3] Google Willow quantum chip — Google official blog, Willow 105-qubit processor announcement

[4] Google warns five quantum attack paths could put $100 billion on Ethereum at risk — CoinDesk, analysis of Ethereum’s 5 vulnerabilities (March 31, 2026)

[5] Quantum Computing Companies In 2026 — Quantum Zeitgeist, comprehensive company profiles (February 2026)

[6] PsiQuantum Announces Omega — PsiQuantum official announcement, Omega chipset + GFS Fab 8 manufacturing (February 2026)

[7] PsiQuantum Raises $1 Billion — The Quantum Insider, $1B Series E coverage (September 2025)

[8] Xanadu Becomes First Pure-Play Photonic Quantum Computing Company to Go Public — The Quantum Insider, Xanadu SPAC listing (March 27, 2026)

[9] Toronto quantum company Xanadu set to debut on TSX, Nasdaq in SPAC deal — Yahoo Finance Canada, Xanadu listing details (March 25, 2026)

[10] Xanadu and Tower Semiconductor Deepen Strategic Collaboration — Tower Semiconductor official press release, expanded SiPh collaboration (February 19, 2026)

[11] Xanadu and imec partner to develop photonic chips — imec official release, SiN wafer partnership (August 2021)

[12] Xanadu Announces A Quantum Computing Collaboration With Applied Materials — Canadian Manufacturing, TES detector 300mm process collaboration (May 2025)

[13] How is NVIDIA ‘Betting’ on Quantum? — The Quantum Insider, NVentures quantum investment analysis (September 2025)

[14] NVIDIA Introduces NVQLink — NVIDIA official newsroom, NVQLink announcement

[15] 2025 is the year of quantum computing — Constellation Research, Jensen Huang comments and quantum industry trends

[16] Ethereum Foundation Unveils Post-Quantum Threat Roadmap — The Market Periodical, pq.ethereum.org roadmap coverage (March 26, 2026)

[17] Watch out Bitcoin devs. Google says post-quantum migration needs to happen by 2029 — CoinDesk, Bitcoin vs Ethereum PQC response comparison (March 28, 2026)

[18] PsiQuantum Expands Development Engagement at SkyWater’s Minnesota Fab — SkyWater Technology IR, expanded PsiQuantum 200mm SiPh collaboration (May 2023)

[19] SkyWater CEO Calls Company ‘Quantum Foundry’ — EE Times, SkyWater quantum foundry strategy (November 2025)

[20] ‘Bitcoin cracked in 9 minutes’: BTC bulls scramble for post-quantum protection as Google drops bombshell paper — CoinDesk, industry reactions from CZ, Nic Carter, Eli Ben-Sasson, and others (March 31, 2026)

Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.