Crack The Market owns the substrates, materials, the European layer and the demand side. PhotonCap owns the foundries, the Asian ecosystem and packaging. Put the two together and one argument runs through the entire piece: the optical transition is consensus, the scarce asset is the capacity to fabricate the PIC, and the scarcer asset is the wafer it is fabricated on.

Six companies sit on that map, and the merchant suppliers among them are being paid, or asked to be paid, before they build. Tower’s customer advances and deferred revenue stood at about $320m at the end of June, and STMicroelectronics says customers are asking for long-term agreements with cash advances, per Investing.com’s transcript.

Seen from the packaging bench, the step that paces co-packaged optics (CPO), where the optical engine sits inside the switch package, comes after the wafer is made. In TSMC’s flow the driver die is stacked onto the photonic die with SoIC-X, a solder-free bond made copper pad to copper pad that cannot be reworked, and Nvidia uses only known-good engines, so each engine is screened before it is mounted. TrendForce lists optical engine yield and advanced packaging capacity beside silicon photonics fabrication among the limits on the CPO ramp. That bond, and the optical test that follows it, is the step PhotonCap watches most closely.

Executive Summary

• The market has spent 2026 pricing the lasers. It has not yet mapped the layer that turns those lasers into links: the six foundries that can fabricate a silicon photonics PIC at scale. The layer is not unknown, it is unmapped, and that has created mispricing.

• Three mispricings fall out of the map. STMicroelectronics is a merchant PIC supplier at roughly Tower’s scale, yet it does not appear on most foundry maps. GlobalFoundries’ claim to be the largest pure-play photonics foundry has already been overtaken by Tower on revenue. TSMC is usually modelled as a merchant foundry, but sells photonics only through its own SoIC bonding line.

• Scarcity has already turned into prepayments. Tower took $290m in a single quarter to reserve 2027 capacity. STMicroelectronics is signing long-term agreements with cash advances. Soitec is signing multi-year reservation agreements with eight of its roughly ten major Photonics-SOI customers.

• The layer splits by form factor, not technology. Pluggables are a merchant market, with three suppliers taking prepayments. Co-packaged optics is a captive market, with one supplier allocating bonding slots. Near-packaged optics is the contested middle, and it will determine where much of the value lands from 2028.

• 2028 is when the capacity wave arrives. Four merchant 300mm expansions are due to come through around the same period. On our base-case arithmetic, Tower’s Japan programme alone exceeds the industry’s 2030 wafer requirement. The risk is therefore wafer pricing, not fab capacity, and Tower’s CFO identifies it as the largest variable in its model.

• Every one of those fabs leads back to the same substrate supplier. Soitec holds roughly 95% of 300mm Photonics-SOI and has guided the business to 2.5-3x last year’s level. Every 300mm expansion in this piece is, ultimately, a Soitec order.

• The bottlenecks are not equally scarce. Our ranking, from hardest to substitute to easiest, is the substrate, InP lasers, SoIC bonding, merchant wafer starts and finally the epitaxy tools.

• The conclusion is simple: the scarce asset is the capacity to fabricate the PIC. The scarcer asset is the wafer it is fabricated on.

Before this deep dive, I recommend reading some of our other write ups on the AI & Technology megatrend, and PhotonCap’s pieces that this collaboration builds on:

• The investment case for the substrate every foundry in this piece buys from, and why the Photonics-SOI monopoly is tighter than the layer it feeds. Soitec: The Photonics Monopoly, Now At A Price That Works

• The laser layer, where capacity is revenue and Nvidia has bought the right to ration it. This piece covers the chips that make the light. Today’s piece covers the chips that carry it. Coherent & Lumentum: The Laser Duopoly That Rations the Supercycle

• The IDM that turns out to be the third merchant PIC supplier at Tower’s scale, with its datacenter numbers raised twice since. STMicroelectronics: Photonics, Satellites and Silicon Carbide

• The European and US photonics stacks mapped end to end: Europe owns the tools and substrates, America owns the lasers, the silicon and the systems. The European Photonics Supercycle and The US Photonics Supercycle

• PhotonCap’s piece on the first pricing signal in this cycle, which appeared at the foundry before the laser, and the starting framework for today’s map. Everyone Saw a Laser Shortage. The Money Went to the Foundries First.

• PhotonCap on the fabless PIC designer Credo bought for $750m, and the foundry that makes its chips. A $750M Fabless Chip Company, and the Foundry That Makes the Chips

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Crack The Market

The Silicon Photonics Foundry Layer: Who Can Actually Make a PIC

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7 days ago · 2 likes · Ozeco and PhotonCap

Table of Contents

1. Before we start: the vocabulary, and why this layer matters

2. The thesis

3. The map: who can fabricate a PIC today

4. Tower: the merchant leader, from 200mm PH18 to 300mm Japan

5. GlobalFoundries: 300mm monolithic scale, and what it ceded to TSMC

6. TSMC COUPE: quasi-captive through SoIC bonding

7. STMicroelectronics: the merchant PIC supplier the maps leave out

8. UMC, Samsung, Intel and the entrants

9. The European specialty layer

10. The layer beneath: substrates, InP and epitaxy

11. Who designs into which fab

12. Capacity arithmetic 2026-2028

13. Merchant versus captive: where the value lands

14. Where the thesis breaks

15. Names by layer

16. Conclusion

1. Before we start: the vocabulary, and why this layer matters

Every dollar of AI capex terminates in a requirement to move photons. That was the line in Coherent & Lumentum: The Laser Duopoly, and it is the reason this piece exists. The market has learned the laser story, the transceiver story and the Nvidia co-packaged optics story. It has not learned who fabricates the chip that sits in the middle of all three. This section is the ten-minute primer so that the rest of the piece can move at full speed.

The chip: what a PIC is

A photonic integrated circuit (PIC) is a silicon die that routes, modulates and detects light instead of electrons. Inside a modern AI transceiver it does three jobs: a waveguide carries the light, a modulator imprints the electrical data stream onto the continuous light coming from the laser, and a photodetector (usually III-V and germanium on silicon) turns received light back into current. Building it on standard silicon tooling is what the industry calls silicon photonics (SiPh).

The PIC is never alone. It sits beside an electronic integrated circuit (EIC), the analog front end: a driver for the modulator and a transimpedance amplifier (TIA) for the detector. A 3nm digital signal processor (DSP) sits alongside, and some of the newest DSPs build the driver in. The PIC also needs a laser, because silicon does not emit light. That laser is built on indium phosphide (InP), with its layers grown as stacked crystal films (epitaxy). In SiPh it sits beside the PIC as an always-on (continuous-wave, CW) source, and in parallel designs one laser feeds two to four lanes. An electro-absorption modulated laser (EML) puts laser and modulator on one InP chip, one per lane, and still ships in 200G-per-lane 1.6T modules. Fewer lasers per module is the main reason SiPh keeps winning parallel sockets (section 11).

The PIC and the chips around it ask very different things of a fab. A 3nm DSP prints its finest layers with extreme ultraviolet (EUV) scanners. A silicon waveguide is about half a micron wide, and its finest details run to about 140nm, printed with 193nm deep-ultraviolet light. The analog SiGe chip in a pluggable stays on mature nodes such as ST’s 55nm B55X. What the PIC needs is uniformity rather than small features: a ring modulator drifts off its colour of light when its width is a few nanometres wrong, so each ring carries a small heater. Otherwise a PIC runs down an ordinary CMOS line with a few photonics-only steps added: modulator implants, germanium detectors, silicon nitride and trenches to hold the fibre. GlobalFoundries runs Fotonix on the 45nm process it uses for digital chips, and Tower is repurposing its Arai fab for 300mm SiPh. So PICs come off lines that are largely paid for, with no EUV. That is why mature-node foundries such as Tower, GlobalFoundries and UMC can lead the PIC layer, and why TSMC’s advantage in photonics is bonding and packaging rather than lithography.

The wafer: what sits under the PIC

A SiPh PIC is not built on a plain silicon wafer. It needs a silicon-on-insulator (SOI) wafer with a thick buried oxide so that light stays confined in the top silicon layer. This grade of wafer is called Photonics-SOI, and as Ozeco set out in Soitec: The Photonics Monopoly and PhotonCap covered in The Wafer That Used to Roll Around My Lab Is Now an AI Data Center Bottleneck, it is made almost entirely by one company. Wafer size matters: 200mm lines are the legacy base of the industry, 300mm lines carry 2.25 times the die per wafer and are where every expansion in this piece is going.

The factory: foundry versus IDM, merchant versus captive

A foundry manufactures chips designed by other companies. A fabless company (InnoLight, Credo, Lightmatter, Ayar Labs) designs the PIC and buys wafers from a foundry. An IDM (STMicroelectronics, Intel, Samsung Electronics) designs and manufactures its own chips, and may also sell manufacturing to others. A process design kit (PDK) is the rulebook a foundry hands its customers, and it is the reason switching foundries is slow: a PIC designed for one PDK has to be redesigned for another, and requalified, which takes six to twelve months.

Merchant capacity is sold to any qualified customer. Captive capacity is reserved for one ecosystem, either because the foundry owns the design or because the chip only works inside that foundry’s packaging flow. The distinction is the spine of this piece, because the merchant foundries and the captive one are exposed to different customers, different form factors and different pricing.

The form factors: pluggable, NPO, CPO

Optics reach a switch or a GPU in one of three ways. A pluggable transceiver is a module the size of a USB stick that slots into the front of a switch, today at 800G and 1.6T, tomorrow at 3.2T. Near-packaged optics (NPO) moves the optical engine onto the board next to the switch chip but keeps it removable. Co-packaged optics (CPO) bonds the optical engine onto the same package as the switch or GPU, which saves power and reach but makes the engine part of the chip package rather than a component. The foundry that makes a pluggable PIC sells a wafer to a module maker. The foundry that makes a CPO engine sells a packaging slot to a chip designer. PhotonCap covered the different architectures in DSP, LPO, NPO, CPO

Image Source: DSP, LPO, NPO, CPO

The stack, top to bottom

Why we are looking at this layer now

Three things changed in 2026 and none of them was about lasers:

• Foundries started taking prepayments. Tower booked $290m of customer prepayments in a single quarter to reserve 2027 capacity. Soitec is signing multi-year capacity reservation agreements with eight of its roughly ten major Photonics-SOI customers. STMicroelectronics says a significant number of customers are asking for long-term agreements with cash advances. In semiconductors, customers only pay for capacity that does not yet exist when they believe it will not be there otherwise.

• Silicon photonics became the majority platform. SiPh crossed half of AI optics units in 2026 and is headed to between roughly 73% and 84% by 2030, depending on which modulator wins at 400G per lane. Every one of those units needs a PIC, and a PIC needs a fab that can make one.

• Every foundry announced a 300mm expansion at once. Tower in Japan, GlobalFoundries in New York and Singapore, STM at Crolles, UMC in Singapore, Samsung Electronics in South Korea. They all land in 2027 and 2028.

The layer is not unknown. Tower has tripled, Soitec has tripled, and PhotonCap wrote the first piece on the foundry pricing signal in June. What the layer is, is unmapped. Nobody has written down who can fabricate a PIC today, on which platform, at what wafer size, for which customers, with what capacity, and what sits underneath it. The consequence of a missing map is mispricing: an IDM that is a merchant PIC supplier at Tower’s scale is counted as a chipmaker, a foundry that calls itself the largest pure-play has been overtaken, and a foundry that is functionally captive is modelled as merchant. That is what this piece sets out to fix.

2. The thesis

The optical transition is becoming a consensus. The scarce asset is the capacity to fabricate the PIC, and that capacity sits in five fabs run by four merchant foundries and one quasi-captive one, all of which are expanding at once into 2028.

Five claims we intend to defend, each with a number behind it:

1. Merchant SiPh is a three-horse race, not a two-horse one. Tower runs at a SiPh run-rate above $680m (Q2 2026) heading to $1bn in Q4. GlobalFoundries guides to more than double its 2025 base of over $200m. STMicroelectronics, absent from every foundry map we have read, is modelled by the sell-side at roughly $800m of SiPh revenue in 2026 and $2bn in 2027. On the headline number STM out-earns both. On a wafer-comparable basis it sits at Tower’s scale and level with GlobalFoundries’ 2028 target. Either way it belongs on the map and is not on it.

2. The binding constraint is wafer starts today and packaging tomorrow. Tower’s Fab 7 runs above its 85% utilisation model. GlobalFoundries says it is “chasing supply”. STM says capacity is the only constraint. Once 300mm capacity lands in 2027 and 2028 the constraint moves to BiCMOS EICs, InP lasers, and optical wafer test and fibre attach.

3. CPO does not route through the merchant foundries. TSMC COUPE fabricates for Nvidia, Broadcom, Ayar Labs and Marvell (Celestial), and it only monetises inside TSMC’s own 3DFabric flow: SoIC bonding and optical test for today’s switch engines, CoWoS once optics move beside the GPU for scale-up from 2028. GlobalFoundries, Tower and UMC are betting on pluggables and NPO carrying the volume through 2028. GlobalFoundries itself says CPO is a relatively small contribution by 2028.

4. 2028 will see four merchant 300mm expansions collide. Tower Arai (ready Q4 2027) and its second Japan fab (Q4 2028), GlobalFoundries Malta, STM quadrupling SiPh capacity by 2027, UMC’s Singapore shells, with Samsung’s foundry service arriving from 2027 on top. Demand has to absorb all of them or wafer pricing, which Tower’s CFO names as the single largest sensitivity in its model, gives back the margin it has just taken.

5. Everything above routes through one substrate supplier. Soitec holds roughly 95% of 300mm Photonics-SOI and sells to GlobalFoundries, TSMC, Tower, STM and imec. Every 300mm expansion in this piece is a Soitec order, and Soitec has just guided Photonics-SOI to 2.5 to 3 times last year’s level. The layer beneath is a tighter monopoly than the layer this piece maps.

What we are not claiming: that the foundry layer captures the most value in the stack (the laser layer’s pricing power is at least as strong), or that today’s contracted revenue survives a 2022-style capex reset intact.

3. The map: who can fabricate a PIC today

Six companies fabricate datacom PICs at production scale. Only three disclose SiPh revenue, and none disclose SiPh wafers per month. The table is what filings, transcripts and disclosed customer relationships support as of September 2026. Blanks are gaps, not zeros.

Table A. Platform and model

Table B. Scale, capacity and customers

Below this tier sit X-FAB (200mm XPH90 with Ligentec SiN and TFLN, NRE stage, product revenue 2027-28), Silterra (Malaysia, 200mm), SMART Photonics (InP, Netherlands) and Intel (in-house, little merchant traction). Section 9 covers them.

Two things jump out:

• First, GlobalFoundries’ “largest pure-play SiPh foundry” claim from the AMF acquisition no longer holds on revenue: Tower’s Q2 2026 run-rate is more than 1.5 times GlobalFoundries’ full-year 2026 guide.

• Second, STM does not appear in any sell-side foundry map, and on its headline numbers it out-earns both merchant leaders in 2027.

4. Tower: the merchant leader, from 200mm PH18 to 300mm Japan

Tower is a merchant foundry, building silicon photonics (SiPh) chips that customers design. Its 200mm PH18 and 300mm PH45 platforms are both in high-volume production for 400G to 1.6T modules. PH18DA bonds indium phosphide (InP) onto the silicon for on-chip lasers and modulators, and NewPhotonics began volume shipments of these photonic ICs (PICs) on 17 September. Tower also makes SiGe drivers and TIAs, the fast analog chips on either side of the optics, in volume at 100G and 200G per lane.

At 100G and 200G per lane the driver and PIC are separate chips, so one foundry for both is mostly a supply convenience. At 400G per lane the driver has to sit on the modulator to cut parasitics, and Tower already offers wafer bonding to stack SiPh and SiGe wafers. Owning both processes and the bond then becomes, in PhotonCap’s view, a performance moat, though no stack customer is named yet.

Growth is moving to 300mm in Japan. By Q4 2027 Arai joins Fab 7 with 300mm SiPh and bonding, and CEO Russell Ellwanger expects “all of the growth” in SiGe and SiPh to be on 300mm from sometime between 2027 and mid-2028. We covered the expansion in The More Silicon Wins, the More InP Sells: Why UMC and Tower Both Expanded 300mm on the Same Day. PH18 to PH45 is a real port: new lithography and etch tools mean waveguides, couplers and doping are re-characterized and the module requalified. We expect most customers to move at the 3.2T, 400G per lane boundary, when they tape out a new PIC anyway. Moving a PH45 design from Fab 7 to Arai is close to a copy.

A bonded laser is patterned by lithography aligned to the waveguides, so it needs no active alignment and can be tested at wafer probe. A bad one cannot be swapped out, though, so laser yield, which is unpublished, multiplies into PIC yield. External CW lasers can be screened and replaced, so switch co-packaged optics (CPO) keeps them outside. We expect the two to coexist by application. Integration wins where an engine needs many lasers at moderate power, in DR8 pluggables and serviceable near-packaged optics (NPO) engines like NewPhotonics’. It also spares module makers a CW laser that has been short all year (see Everyone Saw a Laser Shortage. The Money Went to the Foundries First.). With no 300mm laser flow disclosed, that edge stays tied to 200mm PH18DA for now.

A silicon Mach-Zehnder modulator (MZM) passed 420 Gb/s per lane with Coherent in March. PhotonCap’s read is that in production it carries 400G only in pluggables with a DSP, the digital chip that cleans up the signal, and that is where we expect Tower’s first 400G volume. Above 200 GBd in PAM4 a carrier-depletion MZM runs short of bandwidth, so the link leans on DSP equalization and a high-swing SiGe driver. Linear-drive engines, including linear NPO and CPO, have no DSP, so they turn to PH18DA’s InP modulators, with TFLN, which Tower has in development, later in the decade.

DustPhotonics is covered in A $750M Fabless Chip Company, and the Foundry That Makes the Chips. Nvidia is a named 1.6T module collaborator, but no Tower release we checked says Tower makes its PICs. Nvidia’s switch engines are TSMC COUPE-based CPO for its own switches, while NPO engines like NewPhotonics’ serve other switches, ASICs and operators who want swappable engines, so today the two complement each other. At 400G per lane we expect them to compete for hyperscalers’ scale-out ports, CPO on power and NPO on serviceability (section 6).

SiPh reached a $680m annual run rate in Q2 2026, aiming for $1bn in Q4, and customer advances and deferred revenue rose to about $320m by June from under $30m at end-2025. Company gross margin, which Tower does not split out for SiPh, reached 30% from about 22% a year earlier. Contracts cover about $1.3bn of 2027 SiPh revenue, and Ellwanger said the capacity beyond them is not all booked, “but it’s spoken for”. Q3 results in November, against a $520m guide, are the next check.

5. GlobalFoundries: 300mm monolithic scale, and what it ceded to TSMC

GlobalFoundries builds silicon photonics in Malta on Fotonix, a 300mm process that puts 45nm-class SOI CMOS and photonic devices on one wafer, so the driver chip (EIC) and photonic chip (PIC) can share one flow, though GF also supports a bonded EIC. CEO Tim Breen says 200G per lane is in volume production and 400G has been demonstrated.

PhotonCap thinks the modulator type and the digital logic decide whether 45nm monolithic is good enough for a CPO engine. A silicon Mach-Zehnder modulator (MZM) needs a large swing: GF’s 200G MZM at OFC 2026 takes about 1.8 V·cm (voltage times length to fully switch it), several volts for a few-millimeter arm. That suits a 45nm SOI driver (the OFC paper itself used an off-chip one, as PhotonCap noted in [OFC 2026] Part 1 of 5: 300mm SiPh Foundry: Who Is Actually Ready?), and on the receive side monolithic removes the photodiode-to-TIA bond, where GF has shown a 100 GHz TIA. Micro-rings need less swing but a thermal lock loop per ring, logic that is cheap at an advanced node and costly at 45nm. TSMC’s COUPE hybrid-bonds an advanced-node EIC onto the PIC with little added capacitance (Section 6), erasing most of monolithic’s parasitic advantage. So Fotonix fits MZM pluggables and receivers, and COUPE fits ring-based CPO. The first switch engines went that way: Nvidia’s ring-based engines are built on COUPE (Section 6), and Broadcom’s Tomahawk 6 Davisson puts COUPE-based engines on the package substrate. Even GF’s own ring-based engine, SCALE, puts its EIC on “single-digit advanced nodes”.

SCALE, PhotonCap thinks, aims at a different market. Its 50G and 100G multi-wavelength rings fit scale-up, and GF calls it the first platform ready for the OCI MSA, the open scale-up optics spec. At those lane rates its microbump-class pads, below 45um pitch, are enough. Buyers of custom scale-up engines want a second source, and GF adds a detachable fiber plug and wafer-level optical test. So we see SCALE chasing those engines rather than TSMC’s switch engines.

With no disclosed in-house InP laser growth, GF relies on SMART Photonics laser dies flip-chipped into etched silicon pockets, a service generally available in 2H27. We read this as a process choice with a time cost. Flip-chip lets GF attach pretested lasers and the customer choose the InP vendor, at the cost of sub-micron alignment on every die. In CPO that matters less, since leading engines use external lasers, field-replaceable on Davisson. In pluggables Tower and NewPhotonics already ship laser-integrated PICs in volume (Section 4), about a year ahead of the SMART service.

For 400G per lane GF’s March blog names Pockels (field-driven) materials: thin-film lithium niobate (TFLN), barium titanate (BTO) and electro-optic polymers. We think TFLN reaches a 400G product first, even though BTO is already offered for today’s pluggables. Lithium niobate has the longest telecom reliability record, and AMF brought TFLN and polymer 400G modulator work into GF, per Gazettabyte (trade press), so we expect that product from AMF’s Singapore line.

Beyond switch CPO on the substrate, CoWoS-class integration beside a GPU or XPU arrives with scale-up optics, due on Nvidia’s NVLink in 2028 (Section 6). Breen put NPO in 2027 and CPO in 2028, which we read as matching that wave more than a GF-specific delay.

GF guides 2026 SiPh revenue to “more than double”, mostly from pluggables today, and a July letter of intent points to a $300m Commerce award for SiPh wafers, materials and packaging. Ozeco reads GF as a pluggable foundry with a government-funded materials roadmap, a business that lasts as long as pluggables do.

6. TSMC COUPE: quasi-captive through SoIC bonding

Public disclosures name one maker for the switch CPO engines shipping in 2026: TSMC. Its 2025 annual report says COUPE reached 200 Gbps “with several customers in 2025” and targets CPO volume production in 2026. COUPE uses SoIC-X, TSMC’s solder-free 3D stacking, to bond the electrical die (EIC) face-down onto the photonic die (PIC). Its modulator is a 200G micro-ring, a tiny resonant loop tuned to one wavelength. Nvidia’s Quantum-X Photonics and Broadcom’s Tomahawk 6 Davisson both use COUPE engines, with external lasers.

CoWoS places chips side by side on a silicon interposer, as GPUs sit next to HBM. TSMC’s 2024 plan put COUPE into CoWoS in 2026; by April 2026 the milestone read COUPE on substrate, with CoWoS-based CPO for ultra-high-end switches still in development. Today’s switches don’t need the interposer, since Broadcom uses substrate-level packaging and Nvidia solders its Spectrum-X engines onto the module substrate. CoWoS pays off when the engine sits beside a GPU or XPU for scale-up optics, the links inside one accelerator system; Nvidia plans CPO on NVLink ports in 2028. PhotonCap separated those two races in TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM. The CoWoS queue belongs to a later generation, XPU scale-up and TSMC’s ultra-high-end switch package; today’s switch engines wait on SoIC bonding.

We see the PIC wafer as the least scarce input, since photonics runs on mature nodes with few mask layers. Downstream, a hybrid bond at a few microns of pitch cannot be reworked, so both dies are tested before bonding and each engine is probed optically, ring by ring. Engine yield multiplies EIC, PIC, bond and coupling yields, and only the first two are ordinary wafer-fab problems. TSMC’s K.C. Hsu likewise put the bigger challenge in lasers, fibers, connectors and testing. The bond stays in TSMC’s fab; assembly and test can go outside, as SPIL does for Nvidia. That split is what we mean by quasi-captive.

Pre-bond probing, done on one face of the wafer with electrical needles and optical fibers, is where we think most test revenue sits today. FormFactor expects 2026 CPO revenue to “significantly exceed the $20 million level”, per an Investing.com transcript of its Q2 call. Advantest is developing high-volume SiPh test with OpenLight. In a COUPE-style stack the electrical contacts end up on one face and the surface-coupled optical ports on the other, so confirming an engine works before it reaches a costly switch package means probing both faces. Teradyne introduced Photon 100 at OFC in March 2026, a year after a double-sided cell with ficonTEC for hybrid-bonded wafers, and PhotonCap’s read is that double-sided probing becomes a required step once engines ship in volume. SoIC bonding and engine-level optical test share third place in our chokepoint ranking for CPO because a bonded engine cannot be reworked and a bad one must be caught before it reaches the switch package.

TSMC says COUPE supports both grating couplers (light exits the chip surface) and edge couplers (light exits the die’s side), and can now test edge couplers at wafer level. In PhotonCap’s experience, edge couplers win on loss and bandwidth but were hard to test, since the facet exists only after dicing. With that fixed we read the two as splitting by application, edge coupling for TSMC’s next generation and gratings for Nvidia’s surface-normal engines.

Nvidia’s Quantum-X engines sit in sealed, socketed subassemblies, and in Nvidia’s 2025 launch description the lasers are the field-replaceable part. NPO, near-packaged optics, puts a swappable engine beside the ASIC instead, and NewPhotonics began volume shipments of laser-integrated Tower PICs for it on 17 September, with 6.4T NPO chipsets slated for the first half of 2027. At today’s 200G per lane we see the two as complementary: Nvidia’s CPO is tied to its own switches, while NPO serves other switches, custom ASICs and operators who want swappable engines. At 400G per lane we expect them to compete for scale-out ports, the switch network that links racks, CPO on power and NPO on serviceability. On pluggables TSMC is the least proven answer: the 2024 plan to qualify COUPE for pluggables in 2025 has produced no volume product, and nothing public shows TSMC selling bare SiPh wafers to module makers.

The money sits inside SoIC and packaging revenue, with no separate SiPh line. TSMC’s $60-64bn capex guide puts 10-20% in a bucket for “advanced packaging, testing, mask making, and others”.

7. STMicroelectronics: the merchant PIC supplier the maps leave out

STM is not in any foundry map we have read, and on its headline numbers it out-earns both merchant leaders in 2027. On a wafer basis it is a merchant PIC supplier at Tower’s scale. Ozeco covered the company in STMicroelectronics: Photonics, Satellites and Silicon Carbide and the datacenter numbers have moved twice since.

The numbers. Datacenter revenue was raised on 2 June 2026 to roughly $1bn for 2026 and roughly $2bn for 2027, from “nicely above $500m” and “well above $1bn” only months earlier. The CFO at a September conference put roughly 80% of 2027 datacenter revenue in the MDRF segment, which is the connectivity flow (SiPh PIC, BiCMOS EIC, STM32 MCU), and 20% in power and thermal. Optical was roughly $0.3bn in 2025 at above 40% gross margin.

• Sell-side models put SiPh alone at $150m in 2024, $350m in 2025, $800m in 2026, $2.0bn in 2027 and $2.5bn in 2028, then flattening towards $3.5bn by 2030.

• Orders above $1bn for 2026 and above $2bn for 2027 were secured before the June raise. Q2 book-to-bill was “significantly above 2” in Comms Equipment & Computer Peripherals, more than half of Q2 bookings were for 2027, and the backlog covers 4.5 to 5 quarters.

• Comms Equipment & Computer Peripherals grew 50% year on year in Q2 and is guided to roughly 60% in Q3 and 90% in Q4.

The platform. PIC100 is a silicon-only 300mm platform at Crolles, 200G per lane, in high-volume manufacturing since Q1 2026 for 800G and 1.6T. STM has been investing in SiPh at Crolles since 2014 and is the only large European IDM with a 300mm SiPh line at scale. The EIC is STM’s own BiCMOS B55X, also at Crolles, where STM already holds more than 30% EIC share. The control-plane MCU is the STM32, where STM claims an oversized share in 800G and 1.6T. Three chips in every pluggable from one fab is impressive, and it is why the AWS agreement (multi-year, multi-billion, announced 19 February 2026, with warrants on up to 24.8m shares at $28.38 vesting on purchase volumes) covered PICs, EICs, MCUs and power together. The node is undisclosed in every document. Whether PIC100 sits on Soitec Photonics-SOI is not stated by STM, but STM is on Soitec’s customer list.

Capacity. “We are not right now gated by capacity expansion” on SiPh. SiPh capex is fungible with MCU on 300mm, “an increase in slicing” rather than a new shell, which is the structural advantage of running photonics inside a large 300mm logic fab.

• Crolles will reach 15,000 wafers per week and go above it. Crolles plus Agrate can reach 20,000 300mm wafers per week at full build-out before 2028.

• STM plans to quadruple SiPh capacity by 2027. 2026 net capex is at the high end of $2.0-2.2bn, explicitly rebalanced towards optical interconnect.

• The tighter bottleneck is BiCMOS, with 12-18 month equipment lead times. 300mm lets STM add SiPh capacity without customer re-qualification. Management flags a pocket of OSAT constraint.

Contracting. A “significant number” of customers are asking for long-term agreements “locking capacity, volumes, pricing and cash advance for many”, running one to three years. This is the same prepayment mechanism PhotonCap identified at Tower, appearing at an IDM that no one classifies as a foundry.

Concentration. STM says datacenter revenue is “pretty consistent with market share distribution between hyperscalers”. Sell-side work puts AWS at no more than roughly 30% of datacenter revenue in 2027 and has STM engaged with more than 80% of the AI optical ecosystem. STM also supplies Chinese AI datacentres through InnoLight and other module makers. The 30% figure is a 2027 target, not today’s mix.

What is missing. No laser sourcing comment anywhere, which implies STM ships un-lasered PICs and the module maker attaches the CW laser. No CPO revenue or timing: “we have all the ingredients, including packaging, this will be driven by our customers.” No node. And one sell-side model already flags a moderation in photonics growth beyond 2027 that AI power has to offset. STM’s SiPh number is an IDM number, PIC plus EIC plus MCU at IDM pricing, and it has to be put on a wafer-revenue basis before it can be compared with Tower and GlobalFoundries. That is what we do later in the piece, in Section 12.

8. UMC, Samsung, Intel and the entrants

At UMC, silicon photonics starts with iSiPP300, a 300mm process licensed from imec in December 2025 and built around ring modulators and filters (small circular waveguides that resonate at one channel’s wavelength), GeSi electro-absorption modulators and 3D packaging modules. The first volume product on the Singapore 300mm line is a customer design, and the release doesn’t tie it to the imec process. On 14 July UMC and SILITH announced the first mass-production delivery of 300mm PICs for SILITH’s 1.6T platform at 200G per lane, qualified by a leading cloud infrastructure customer, and the two are now building a 400G-per-lane platform on silicon Mach-Zehnder modulators (MZMs).

Alongside it, UMC has thin-film lithium niobate (TFLN), a crystal film whose refractive index shifts directly with voltage, which gives high bandwidth at low drive voltage. HyperLight’s TFLN chiplet platform is qualified in volume at Wavetek, a UMC subsidiary, on 150mm wafers, with 200mm capability added. On the Q2 call, per Investing.com’s transcript, CEO Jason Wang said UMC is working on 400G per lane for a customer’s 3.2T design on TFLN, which could be combined with UMC’s silicon PIC through its advanced packaging.

PhotonCap expects silicon MZMs and TFLN to coexist at 400G per lane for a while. Silicon MZMs should keep the volume DSP pluggables on cost and CMOS manufacturability, as the Tower and Coherent 420 Gb/s demo suggests (Section 4), while TFLN gets in first as a chiplet next to the silicon PIC where low drive voltage and high bandwidth matter most.

From 2027, when its filing says the platform opens for general customer use, UMC joins GF, Tower and ST as a 300mm SiPh line for any customer’s designs, so wafer size alone doesn’t differentiate it. What it has on top is the combination of a 300mm SiPh line, a separate TFLN manufacturing line (on 150mm and 200mm wafers, not 300mm) and in-house packaging inside one group, which no other merchant foundry here offers today. Ozeco’s read is that UMC becomes the first real alternative source of 300mm PIC wafers once its P4 cleanroom in Singapore ramps in late 2027 to early 2028, and the sign to watch is a second named SiPh customer beyond SILITH before then. UMC raised 2026 capex from $1.5bn to $2.0bn in July with no SiPh split. SiPh wafer capacity and revenue are undisclosed, and UMC guides its Q3 dollar ASP to “remain firm”.

Samsung’s 300mm platform, per SemiVision Research’s summary of its OFC 2026 paper (secondary), uses a 305nm top silicon layer, a 400nm SiN layer, PN-doped modulators and germanium photodiodes. PhotonCap doesn’t see 305nm as a unique porting barrier, but it does mean more redesign for thickness-sensitive devices such as rings and grating couplers. The Elec reported in September that in-house PIC wafer test was still under way, with foundry service from 2027.

Intel has the longest SiPh volume record here, from a platform that integrates lasers on the die at wafer scale: over 8 million PICs and over 32 million on-chip lasers, mostly in its own pluggables.

In China, CanSemi has a 300mm 90nm SiPh platform at trial production and has not named a datacom module customer.

9. The European specialty layer

Europe has one volume SiPh fab (STM’s Crolles), one volume substrate supplier (Soitec), and a set of 200mm specialty platforms that serve a different market: low-loss silicon nitride, heterogeneous integration, InP, high-mix. Though Europe has no pluggable PIC foundry today. This is consistent with Ozeco’s framing in The European Photonics Supercycle and The US Photonics Supercycle: Europe owns the tools and substrates upstream, America owns the lasers, the silicon and the systems.

Three observations on Europe’s positioning:

• X-FAB is the only listed European specialty name with a credible volume path, and its photonics is optionality for 2027-28 rather than pricing power today. The share price moved on the silicon carbide and SiPh narratives before the revenue.

• SiN and TFLN are the next curve, not the current one. LightCounting has TFLN barely visible in 2026 and appearing from 2027 in DWDM. That is where Ligentec with X-FAB and UMC’s TFLN line compete, not where Tower and GlobalFoundries earn today.

• The European layer’s real weight is upstream. Soitec substrates and Aixtron epitaxy tools, which the next section covers, and STM, which is the only European name in the volume tier.

10. The layer beneath: substrates, InP and epitaxy

A foundry’s capacity build is only realised on top of its materials supply, and the materials layer is more concentrated than the foundry layer it feeds.

Soitec: the wafer under every 300mm expansion

Soitec does not make chips. It makes the engineered substrates that other people build chips on, and in photonics that makes it the single point every foundry in this piece passes through.

• Smart Cut is roughly the entire SOI market. Soitec holds roughly 80% of SOI overall and roughly 95% of 300mm Photonics-SOI, on which the industry is standardising.

• Every major SiPh foundry, GlobalFoundries, TSMC, Tower, STM and imec, buys Photonics-SOI from Soitec. The company now talks about “around ten major Photonics-SOI customers”, up from the five it referred to earlier this year.

• Photonics-SOI was slightly above $100m in FY26 (March 2026). On 2 September 2026 Soitec raised the FY27 Photonics-SOI outlook to 2.5 to 3 times the FY26 level, so $250-300m, with Q2 FY27 at roughly three times last year’s quarter (about $75m) and the first half at roughly 2.3 times. Group Q2 revenue growth was raised to around 50% from “more than 30%”. Soitec expects multi-year capacity reservation agreements to be in place with eight of its roughly ten major Photonics-SOI customers within weeks, on top of the prepaid reservations already in the commitment book (up to €1.1bn of future sales at 31 March 2026).

• The 300mm Photonics-SOI line in Singapore qualified for high-volume manufacturing six months early. As of the FY26 results management said no expansion was needed and fab loading was around 50% against the 60-70% needed for leverage. The September update did not change that, which means the 2027-28 foundry ramps are being absorbed by existing Soitec capacity for now.

In Soitec: The Photonics Monopoly Ozeco built the TAM on $1,300 per 8-inch-equivalent wafer held flat and 8-inch-equivalent Photonics-SOI wafers rising from 65k in 2025 to 406k in 2030, a 44% CAGR, for roughly $528m of datacenter Photonics-SOI revenue by 2030. The September guidance says wafer volumes roughly triple in a single year. At that pace the 2030 endpoint of the framework arrives in 2028, which is the same year the four foundry expansions land. The two series are consistent, and both say the substrate order book leads the fab order book by about a year.

Second-source risk is the one thing to keep watching. Shin-Etsu (licensee since 1997, shareholder), Siltronic (licensee 2004) and GlobalWafers (licence terminated 2025, shipping 300mm SOI, stated intent to serve photonics) are the candidates. Ozeco’s model drifts Soitec’s share from 95% to 80% by 2030 with six to twelve month qualification cycles. Lithium-niobate-on-insulator for beyond-1.6T modulation is in development at Soitec, which is the bridge to the TFLN layer.

InP: the laser’s bottleneck, and now the foundry’s

200G per lane EML supply and most of the CW laser and photodetector chain run on InP substrates and epitaxy. In Coherent & Lumentum Ozeco argued that in this layer capacity is revenue, and the numbers since have followed the capacity ramps exactly.

• Coherent grew InP output 80% year on year in the June quarter, doubles capacity by the end of the September quarter and again by end 2027, almost entirely on 6-inch, which gives more than four times the die per wafer at roughly half the cost per device. Four InP fabs: Fremont, Sherman (first 6-inch, ultra-high-power CPO lasers), Järfälla and Zurich.

• Lumentum’s two Japanese 4-inch fabs are fully allocated, capacity is up roughly 40% in three quarters, Greensboro is native 6-inch with first revenue early 2028, and the company holds more than 50% EML share at 100G and 200G.

• Nvidia put $2bn of equity into each in March 2026 with multi-year purchase commitments and capacity rights. Lumentum’s CEO said Nvidia could take all remaining capacity.

• Substrates: Sumitomo Electric (targets more than double capacity 2023-28), AXT (not yet on 6-inch, China-domiciled manufacturing), JX, Freiberger. Epiwafers: IQE, now under a multi-year minimum-commitment agreement with Tower, and VPEC.

• Industry consensus has light sources tight through 2027 and balanced in 2H28.

The point for the foundry map: Tower’s integrated-InP strategy, now in high-volume production with NewPhotonics, pulls the laser bottleneck inside the foundry gate, while GlobalFoundries, STM and UMC leave it with the module maker.

Aixtron: the tool under the epi

Aixtron holds roughly 90% of MOCVD for optoelectronic epitaxy and is the only commercial platform for InP CW and EML layers, with an 18-24 month switching cost. Epitaxy is 40-60% of laser wafer cost. After the Nvidia deals management guided 60-120 InP tools a year at €3-3.5m each, €180-420m against a roughly €100m 2025 base. The G10 tool on 6-inch raises output per run 1.5-2.5 times plus a 33% yield gain, which means fewer units for the same capacity, and that is the risk in the tool count.

Chokepoint ranking

Ranked by substitutability and lead time:

1. Soitec Photonics-SOI. No qualified 300mm second source, six to twelve month qualification, order book leading the fabs by a year.

2. InP epi and 6-inch substrates. Tight to 2027, balanced in 2H28, and now being locked by foundries as well as laser makers.

3. SoIC hybrid bonding and engine-level optical test (CPO only). Cannot be reworked, single supplier, and the step that gates switch engines today.

4. Merchant SiPh wafer starts. Tight today, four expansions landing 2027-28.

5. MOCVD tools. Constrained by unit count, not by share, and eased by the 6-inch productivity gain.

11. Who designs into which fab

The foundry map only matters if we can say who is designing into each fab. This is the table that does not exist anywhere else, and it is assembled from disclosures where they exist and attributions where they do not. Each row carries its evidence grade: D disclosed by one of the parties, A attributed by industry research or trade press, I our inference.

Three observations:

• Tower’s customer list is the broadest and the best confirmed, and it got two more confirmed names in the last five months (DustPhotonics through PhotonCap’s April piece, NewPhotonics through Tower’s own release). That is why its contracted revenue is the cleanest signal in the layer.

• The CPO customers are all at TSMC, and the ones that started at GlobalFoundries (Ayar Labs, and the Nvidia and Broadcom leading edge) left. GlobalFoundries’ customer list is now a pluggable and quantum list.

• Credo matters more than its size suggests. In Credo: When a De-Rating Is a Gift Ozeco set out the FY27 optical target above $600m across DSPs, PICs and ZeroFlap transceivers, with ZeroFlap at 100k units a month exiting the year and two merchant 1.6T PIC design wins for FY28. All of that PIC volume now lands on Tower’s 200mm lines, which is a second reason to read Tower’s “spoken for” capacity as real.

Only silicon photonics modules need a SiPh wafer; EML modules (laser and modulator on one indium phosphide chip) and VCSEL modules do not. LightCounting’s forecast has AI optical modules growing from about 36m units in 2025 to about 130m in 2030, with the SiPh share rising from 38% to 84%. That takes SiPh modules from about 14m to about 110m, twice the market’s growth.

The reason is mostly the laser. An EML-based 1.6T DR8 (eight parallel 200G fiber lanes each way) needs eight 200G EMLs, while a SiPh DR8 can run off as few as two high-power CW (always-on) lasers, each shared by four lanes. Some designs use four. In PhotonCap’s view, the 200G EML has been the tightest part of the optics supply chain through the 1.6T ramp, on yield and capacity. The saving holds only in parallel designs like DR8. A 2xFR4 module, four wavelengths on each of two fibers, still needs one laser per wavelength, and there EML holds on.

PhotonCap reads 84% as an upper bound that needs silicon to hold the next lane speed. The public series is lower: CIC, in InnoLight’s prospectus, ends at 73% of datacom optical revenue in 2030. Tower and Coherent have run 400G per lane through a silicon modulator, but Coherent also showed a 400G differential EML and InnoLight a 200G per lane TFLN modulator, a candidate for the next speed. If 400G per lane goes to EML, unit share likely stalls near 73% or below. TFLN bonded onto a silicon PIC still starts on a SiPh wafer, though.

PICs per module and good die per wafer are not disclosed, so as an explicit assumption we use two PICs per 1.6T module (transmit and receive) and about 1,000 known-good dies per 300mm wafer, as section 12 does. Then 110m modules in 2030 need about 220k wafers a year, roughly 18k wafers per month (wpm). One die per module, as in some 1.6T designs, halves that; 500 good dies per wafer, plausible for a larger die, doubles it to about 37k wpm. These two inputs decide whether 2027-28 capacity looks tight or oversupplied; section 12 makes that comparison.

CIC puts InnoLight at about a fifth of the 2025 optical interconnect market, with an unnamed 14% player that matches Eoptolink by our reading. Both are Chinese, yet every PIC foundry named for them is outside China. If a US rule ever targets suppliers by nationality, module share would shift to non-Chinese makers, and the PIC wafer would move only if those makers use a different foundry.

12. Capacity arithmetic 2026-2028

No foundry discloses SiPh wafers per month, so the arithmetic has to be done in revenue run-rates and the few physical numbers that exist. Treat the numbers as orders of magnitude.

Putting STM on a wafer basis. STM’s $2bn of 2027 SiPh revenue in sell-side models is an IDM number: PIC plus BiCMOS EIC plus MCU at IDM pricing. Two chips of the three are silicon photonics, and a merchant foundry would sell only the PIC wafer. Using the module bill-of-materials split (two PICs at roughly $70 in a 1.6T module against a $341 total, and the EIC and MCU at a similar combined value) and applying a foundry wafer margin rather than an IDM chip margin, roughly 40-50% of ST’s SiPh line is PIC value, and roughly 60-70% of that PIC value is what a foundry would book. On that basis STM’s 2027 SiPh revenue is roughly $0.6-0.8bn on a Tower-comparable footing, which puts it level with GlobalFoundries’ 2028 exit run-rate but behind Tower’s 2027 contract book. The headline claim in section 2 survives in the softer form: STM is the third merchant supplier at Tower’s scale, not a hidden number one. That is still a claim no map makes.

The sum. Merchant SiPh revenue on that comparable basis (Tower, GlobalFoundries, STM wafer-equivalent, UMC) runs from roughly $1.5bn in 2026 to roughly $2.8bn in 2027, against a SiPh wafer SAM that GlobalFoundries’ own slide puts at roughly $0.7bn in 2026 rising to roughly $6.5bn by 2032. The 2026 numbers do not reconcile: the merchant tier is already booking about twice the wafer SAM the industry slide shows for the year. Either the SAM slide is stale (it predates the Tower and STM raises) or it counts only the PIC die at a lower price point. Both are plausible and neither changes the conclusion that the 2028 capacity is priced for a demand curve that must keep steepening.

The physical cross-check. Tower’s Japan minimum of 20-25k wpm on 300mm is equivalent to 45-56k 200mm wafers a month on the 2.25x conversion. Soitec’s 2025 base of roughly 65k 8-inch-equivalent Photonics-SOI wafers a year, about 5.4k a month across all customers, says the whole industry ran on a small fraction of what Tower alone plans to add. The September guidance closes part of that gap: Soitec’s FY27 volumes roughly triple, so the run-rate is heading towards 15-20k 8-inch-equivalent wafers a month by early 2027, and at the same growth rate reaches the equivalent of the Japan programme alone by 2028. What the two series say together is that Tower’s Japan capacity is not all SiPh in its first two years, and that Soitec’s “no expansion needed” line will be tested by the end of 2027.

The demand-side cross-check. Section 11 does the arithmetic: about 110m SiPh modules in 2030, two PICs per module and about 1,000 good dies per 300mm wafer come to roughly 18k wpm industry-wide, in a range of 9-37k depending on those two inputs. On the base case, Tower’s Japan minimum alone exceeds the whole industry’s 2030 wafer need. Add GlobalFoundries, STM and UMC, and the risk in 2028 is overcapacity rather than shortage, unless PIC counts per module or die sizes rise at 3.2T.

13. Merchant versus captive: where the value lands

The layer splits by form factor, not by technology. Pluggables are a merchant market with three suppliers taking prepayments. CPO is a captive market with one supplier allocating packaging slots. NPO is the contested middle.

The mechanism. PhotonCap’s June framing stands: pricing power belongs to the layer where customers put down prepayments, and in 2026 that is the merchant foundry and the substrate, not the laser. What this piece adds is that the mechanism has a shelf life set by two dates: the 2027-28 arrival of four 300mm expansions, and the point at which CPO volume moves the optical engine from a merchant wafer sold to a module maker into a TSMC 3DFabric slot sold to a switch vendor. GlobalFoundries’ own numbers say pluggables carry it to the $1bn run-rate and CPO is small until then. Tower’s say all 300mm growth after mid-2028 is SiPh. Both are betting that pluggables and NPO outlast the merchant capacity wave.

Value capture by layer, 2026-28. Highest and most durable: Soitec, single-source substrate, prepaid reservations with eight of ten major customers, no expansion needed. High but time-limited: Tower (contracted 2027, prepaid, 67% incremental gross margin) and STM (LTAs, accretive margin, but AWS concentration and a post-2027 flattening in the models). Medium: GlobalFoundries (scale and government co-funding, but mobile drag and lost CPO customers). Optionality only: UMC, X-FAB, Samsung. Indirect: TSMC, whose photonics value shows up in SoIC today and CoWoS later, and ASE and Amkor, whose value rises with CPO. The laser layer sits alongside rather than inside this map and is at least as constrained.

14. Where the thesis breaks

1. Wafer pricing in 2028. Tower’s CFO: the selling price per wafer is the largest variable in the model and “the selling price is just 100% reflection over the margin”. Four 300mm expansions and a share-hungry UMC land in 2027-28. If demand does not keep steepening, the eight points of gross margin Tower added in a year (30% in Q2 2026 against about 22% a year earlier) come back out.

2. The 200mm to 300mm requalification. Tower’s customer base was built on PH18 on 200mm. The growth is on PH45 and Arai on 300mm. Every PDK change is a redesign opportunity for the customer to dual-source at GlobalFoundries, STM or UMC. STM says 300mm lets it add capacity without requalification. Tower’s transition is the reverse case.

3. CPO goes captive faster than pluggables grow. If Rubin Ultra and Tomahawk 6 pull scale-out optics into COUPE engines faster than expected, and the 400G per lane contest between CPO and NPO (section 6) goes to CPO, the merchant tier’s 2028 capacity is built for a market that moved. Industry forecasts have two-thirds of 3.2T ports on CPO by 2030.

4. The contract book is thinner than it looks. Tower’s $1.3bn is contracted. The other third of 2027 capacity is “spoken for”. GlobalFoundries names no SiPh customer directly. STM’s LTAs are volumes and pricing, and hyperscalers have cancelled optics orders before (2022-23). A capex reset turns prepaid capacity into overcapacity, and Tower’s prepayments cushion it least where the capacity is newest.

5. Soitec risks losing the monopoly earlier. GlobalWafers is shipping 300mm SOI and wants photonics. A six to twelve month qualification at any of the four merchant foundries during a capacity build is exactly when a second source gets qualified. Ozeco’s model drifts share to 80% by 2030. The risk is that it happens by 2028.

6. The InP constraint does not ease. If 6-inch InP at Coherent and Greensboro slips, the CW laser supply that SiPh pluggables depend on stays rationed by Nvidia’s capacity rights, and merchant foundry wafers ship without light sources. Tower’s IQE agreement and its in-house laser integration are the only foundry-level hedges in the map.

7. TFLN and SiN arrive early. LightCounting has TFLN barely visible in 2026 and appearing in 2027 DWDM. UMC has a TFLN modulator in production and a hybrid PIC in risk production Q2 2027. GlobalFoundries’ government money funds BTO and TFLN modulators. If 400G per lane needs non-silicon modulators, the platform advantage shifts to whoever integrates them first, and the 200mm specialty fabs re-enter the volume story.

8. Israel concentration. Tower’s SiPh base is Migdal HaEmek until Japan scales, and management cites geopolitical neutrality as a reason for Japan.

9. Our own measurement risk. The revenue series are not like-for-like until STM is put on a wafer basis, and the Soitec wafer count against Tower’s Japan capacity only reconciles with the September guidance. Publishing before both are pinned down would repeat the sell-side’s error of counting the layer without measuring it.

15. Names by layer

Scenario mapping, extending PhotonCap’s June table:

• The base case (demand overhang through 2027) favours Soitec, Tower, STM and GlobalFoundries in that order of signal quality.

• CPO acceleration favours TSMC, ASE and SPIL, Amkor and the test names, and is a relative headwind for Tower and GlobalFoundries.

• A capex reset is cushioned by contracted revenue at Tower and STM and hurts UMC, X-FAB and Samsung most, with Soitec’s 50% loading the least exposed to overbuild.

16. Conclusion

The optical transition is becoming consensus, and the market has started to price the lasers. What it hasn’t fully mapped yet is the layer that turns those lasers into links.

Today, only six companies can fabricate a datacom PIC at scale. Three are already taking prepayments. One sells only through its own bonding line. All six are building 300mm capacity, and most of that capacity lands within the same eighteen-month window.

And underneath every one of those fabs sits the same substrate supplier.

In the base case, the merchant foundries and Soitec capture the scarcity through 2027. From 2028, the question becomes whether pluggables and NPO can keep enough volume in the merchant tier to absorb all the capacity being built, or whether co-packaged optics eventually pulls that manufacturing inside TSMC’s walls.

The scarce asset is the capacity to fabricate the PIC.

The scarcer one is the wafer you fabricate it on.

Disclaimer

This article is an independent technical analysis published by PhotonCap and Crack The Market (Ozeco), based on an engineering perspective. All content is derived from publicly available information and is intended solely for educational and informational purposes. In other words, nothing in this material should be construed as a recommendation to buy, sell, or hold any specific securities. Please note this carefully. The author may hold positions in the securities mentioned herein and reserves the right to trade such securities at any time without prior notice. Readers should conduct their own thorough review and research before making any investment decisions.

• The final prospectus SK hynix filed with the SEC for its US listing in July, and the 21 filings it has made since, never once mention “hybrid bonding” or “DRAM on logic.” Yet at the keynote of a forum the same company held in September, we heard that since this spring customers had started asking, almost as if on cue, for a structure that bonds DRAM onto a logic chip.

• If this structure grows, the companies that buy hybrid bonders could change. It is a second source of demand that opened up while HBM bonding adoption slipped twice, a year each time, going by a bonder maker’s own timeline, and it is not yet settled whether the bonder purchase orders will go to memory makers or to foundries.

• At the SK hynix Global Forum roundtable on September 18, the speaker said the slowdown in how fast HBM stack counts rise is a fact, but that it probably isn’t permanent. In effect, the question has moved from “how high do we stack” to “where do we stack.”

• The difficulty with this structure lies in both design and process. Depending on whether the logic die goes on top or on the bottom, heat and power pull against each other; the DRAM needs a lower bonding temperature; and bonding whole wafers means the bad dies get bonded too.

• Interestingly, when I lined up the public cases one by one, the line that decides who does the bonding turned out to lie somewhere other than foundry versus memory maker. My lead is that knowing that line lets you gauge who will buy the bonders, and that no matter who bonds or how, the XXXXX sector before and after bonding can’t be left out.

Contents

1. The Question of Whether 4-High or 8-High Is Enough

2. Is Stack Height Taking a Break?

3. Checking Against the Last Map

4. DRAM Comes Back on Top of Logic

5. Why the Bonding Is Hard

6. Who Stacks It

7. What to Watch on the Equipment Side

8. Closing

9. References

1. The Question of Whether 4-High or 8-High Is Enough

At the afternoon packaging roundtable of the SK hynix Global Forum, held in the US on September 18, HBM stack height came up in the later part of the Q&A. An audience member asked what the panel made of the recent talk that 4-high or 8-high HBM is optimal.

The speaker answered that a SemiAnalysis post from the previous week laid it out well. Its analysis is that as token counts grow, the sweet spot between bandwidth and capacity moves toward lower stack heights, and the speaker agreed with that analysis, saying the company’s own memory-systems people already know this. The speaker added that the steady rise in stack counts should be seen as having slowed a little, that this is simply where things stand for now, but that it probably isn’t permanent. The same answer went on to 3D stacking, putting DRAM on top of logic.

I read that answer as a sign that the question has moved. Since the speaker admitted the slowdown and denied that it is permanent, the question left is less how high to stack HBM than where to stack DRAM.

The official wording runs a little differently. In a post on the TSMC event published on September 28, the SK hynix newsroom wrote that HBM keeps raising its stack count and bandwidth with every generation, which makes close ties with packaging essential [1]. Put the company’s public wording next to the roundtable answer, and the picture is roughly of a company that isn’t giving up the stack-count race but is separately looking for what comes next.

The event was an invitation-only session that doubled as recruiting, so I didn’t get the slides. As in parts 1 and 2, every fact that carries a source number was checked against public material, and anything I only heard in the room is flagged as such. In part 1 I wrote that part 3 would be about who stacks and who buys the bonders. If DRAM goes on top of logic, who buys the bonders? Even if a memory maker supplies the DRAM, there’s no guarantee it also does the final bonding, and following the public stacking cases turns up some clues. After part 2’s 2.5D, this is the 3D story of stacking upward.

2. Is Stack Height Taking a Break?

Let’s start again from SK hynix’s public roadmap as laid out in part 1, SK hynix’s Four Packaging Paths: Where Is the Fight After HBM?. The roadmap slide shown again in the August 23 Hot Chips talk (its footer credits ISMP 2024) put 8-high and 12-high in mass production, 16-high in parallel development with improved MR-MUF and hybrid bonding, and 20-high and above at the research stage with hybrid bonding alone [2]. MR-MUF is SK hynix’s current method: it stacks chips with small bumps between them and then fills the gaps with a liquid protective material. Hybrid bonding joins copper pads directly, with no bumps.

The case for lower stacks was made by SemiAnalysis in a September 13 post [3]. Going by the free section, the gist is that in decode (the part of inference that generates tokens one at a time), cost per unit of bandwidth and cost per token are lowest at 4-high. Bandwidth per HBM4E stack is the same regardless of height, and by their own model, 8-high and 12-high cost a little over 10 percent and about 26 percent more, respectively, at the system level than 4-high, while throughput rises by 10 percent at most [3]. These are calculations for a specific rack and model, so I’d be careful about generalizing.

NVIDIA has published few official numbers so far. What NVIDIA has stated directly is only that Rubin uses up to 288GB of 12-high HBM4 per GPU [4]. For the next generation, Rubin Ultra, TrendForce reported in early August that NVIDIA had widened its evaluation to include 8-high HBM4E as well as 12-high and 8-high HBM4, and that the final spec had not been set [5]. Taiwan’s Commercial Times, citing a Morgan Stanley supply-chain survey, expected the spec to be set before the end of the third quarter [6], but as of September 28 I found no confirmed announcement or report. A figure of 192GB per GPU is also going around, but it is SemiAnalysis’s own reporting, and NVIDIA has never confirmed it [3].

In the roundtable talk, thickness came up first. The explanation was that within today’s thickness spec, 16-high and 20-high are close to the limit; going to 20-high or 24-high may need new technology, and another route is a large-area package that fills out capacity with more HBM stacks per package. Simply raising the stack count is a matter of setting an internal process baseline and qualifying it, the speaker said. With large-area packages, though, problems that never showed up in small packages surface in the bigger ones, and TSMC’s approach differs from other companies’, so each one has to be matched separately. We also heard that the DRAM die thickness in MR-MUF stacks started at 50 micrometers, which even people inside the company were skeptical about at the time, and is now close to 30 micrometers. If part 1’s 0.9x cut in chip thickness is the step for one generation, from 12-high to 16-high, this is progress built up over several HBM generations.

Here’s my view. SemiAnalysis’s 4-high logic is a calculation aimed at inference, and specifically at cost per token in decode, and the original piece itself acknowledges up front that pre-training is far more sensitive to capacity [3]. The speaker also said bandwidth and capacity trade against each other, so large capacity will be needed at some point. So I think that on the unit cost of decode alone, lower stacks win, but that capacity-hungry workloads could split off into a separate product line that uses taller stacks. Measured against the path laid out in part 1, the move to 16-high with existing methods has slowed a little, which is the opposite of 20-high and above being pulled forward.

3. Checking Against the Last Map

On September 17, when I ranked hybrid bonding equipment companies by score in [Investment Map] 22 Listed Companies in the Hybrid Bonding Value Chain, I judged that the stretch before memory adoption would be long and put a 1.5 weight on two scoring axes, logic and delay. Only eleven days have passed, so none of the dated checkpoints has come due, but when I pulled together the timing records behind that judgment again, they fit into a single table.

Starting with the 2024 records: an SK hynix packaging executive reportedly said at a November 2024 conference that hybrid bonding would be used from HBM4E, at a time when HBM4E mass production was planned for 2026 [7]. There was also an October report that Samsung Electronics had shown, at a 2024 conference, a roadmap applying hybrid bonding to HBM4 for mass production in 2026 [8]. Bonder maker BESI wrote in its 2024 Investor Day deck that memory adoption had slipped a year, to 2026 [9], and in this June’s deck it named 16-high HBM4E as the first insertion generation and wrote that a leading customer is preparing for high-volume manufacturing in 2027 [10].

Here’s where things stand now. Tom’s Hardware reported on the August Hot Chips talk that hybrid bonding would have a hard time making it into HBM4E, but according to the same article, the Hot Chips presenter didn’t name a target generation, and the company has not yet decided which product gets it first [11]. Two days later, a column by an Inha University professor published in the SK hynix newsroom judged that full adoption is most likely to come with HBM4E or HBM5 [12]. Market research firm Counterpoint expects SK hynix’s full-scale hybrid bonding production in 2029-2030, when HBM5 arrives [13]. Samsung said on its January earnings call that it plans partial commercialization at the HBM4E stage [14], and a July report said the company internally sees large-scale production becoming possible in 2030 [15].

Hybrid bonding in HBM moved from 2026 to 2027, and wider adoption is now projected for 2029-2030. Table comparing each company’s 2024 roadmap with where it stands in September 2026

Put in a table, the records show that the 2026 both memory makers were naming in 2024 has become, in BESI’s reckoning, a leading customer’s 2027 production. BESI’s August deck kept that sentence and only added the word “Anticipated” to the title of its first-insertion slide [16]. The 2029-2030 date for wider adoption is a projection from market researchers like Counterpoint. Because the two numbers come from different forecasters and different products, they’re hard to tie into a single production schedule, but they point the same way: the gap between first use and wide adoption is getting longer. I spent a good while digging through 2024 conference coverage to fill this table, and the window when both companies were naming the same 2026 turned out to be shorter than I expected.

In my September 17 piece I read the Hot Chips talk as saying existing methods would carry through HBM4E. A guest column in the same company’s newsroom saw HBM4E or HBM5 as the likely entry point, and BESI is talking about a leading customer producing 16-high HBM4E in 2027. BESI’s third-quarter results on October 22 should give the first clue as to how those two line up. I’m leaving the 1.5 weight as is. When I pulled the evidence together again, the case that the gap to wide adoption is lengthening came out even firmer, so I’d say the call that the delay stretch would be long was right, to a degree.

4. DRAM Comes Back on Top of Logic

The roundtable speaker recalled that when the first generation of HBM was being developed, the structure the customer originally brought was 3D, but it ran too hot, so the design fell back to 2.5D. I mentioned this in part 1, and the reason that picture has come back is energy per bit. On a slide AMD showed in its ISSCC 2023 keynote, moving one bit of data costs about 12 picojoules for a memory module (DIMM), about 3.5 picojoules for HBM on an interposer (an intermediate substrate that holds the chip and the HBM side by side), and about 0.2 picojoules when chips are hybrid bonded one on top of the other [17]. In the panel discussion, too, we heard that trimming the energy spent on the interface circuitry (PHY) that DRAM and logic use to exchange signals under an agreed spec would raise efficiency. On the customer side, it’s just as the keynote remark in part 1 put it: since this spring, customers have started asking for this structure almost as if on cue.

At TSMC’s April symposium, SK hynix put 3D Stacked DRAM on Logic, which stacks DRAM vertically right on top of a logic chip, on its roadmap and wrote that it is particularly well suited to on-device AI [18]. The company’s public materials that I checked through September 28 give no year for this structure. The final prospectus filed with the SEC for the July US listing and the 21 Form 6-K filings since then don’t use the words “hybrid bonding” or “DRAM on logic” either; there is only a broad sentence about investing in custom base dies and advanced stacking techniques for next-generation HBM [19][20].

On why DRAM on logic is hard, the roundtable explanation was more concrete than the public material. From HBM4, SK hynix makes the base die on TSMC’s logic process, and it stacks the core DRAM on top with its own stacking technology, MR-MUF [21][22]. The speaker said this is closer to a minor change, moving a base die the company used to design itself onto a foundry design.

DRAM on logic is a different matter. According to the speaker, DRAM so far hasn’t used the low-k dielectric found in logic wiring (an insulating film with lower permittivity to cut signal delay); the process design changes completely depending on whether the logic die faces up or down; and the concepts behind aluminum pads and the layers that use low-k are different too, so there’s no way to know what problems will come up. We also heard that this only works if you open up information with your partners, down to the recipe level.

This much can be drawn from public material. In the paid section, I first walk through why this structure is hard from an engineer’s point of view, then put the public cases where DRAM has been bonded, or was announced to be bonded, onto logic into one table and compare who made the logic with who did the bonding. In the “who bonds” column of that table, only the SK hynix cell is empty, and how that cell gets filled will decide where the bonder purchase orders go. After that, I also lay out which process I’m watching instead of the bonders.

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Both answers went the same way. The point was that Samsung and Intel overlap with TSMC in their core business while SK hynix doesn’t, and that this is what makes it a good partner. The speaker said the company won’t go where it would overlap with TSMC, and has no plan to become a foundry just because its base dies are doing well. On the Indiana question, the speaker answered that the company doesn’t have the capability to do it right now, that it’s preparing step by step, and that you need the technology before you can even negotiate.

Those questions came up because, early in the roundtable, the speaker had said the company has been preparing a CoWoS-L class 2.5D package for two years. Last week, in [Investment Map] 22 Listed Companies in the Hybrid Bonding Value Chain, I went through twenty-two companies in the hybrid bonding value chain. If hybrid bonding is about stacking chips upward, 2.5D is about spreading them out sideways. Let me give you the conclusion first. For now, the line’s purpose is to find out firsthand under what conditions the company’s HBM fails inside customers’ packages, and the place to do that work is the R&D testbed in Indiana. That’s the answer I heard. Commercialization comes after that.

Contents

1. What I Heard and What I Checked

2. Where Part 1 Left Off

3. What Has Been Built So Far

4. Why Build It: Two Purposes

5. The Weight of Yield, and Shift-Left

6. The Work That Overlaps with Indiana

7. Closing

8. References

1. What I Heard and What I Checked

The event was an invitation-only session that doubled as recruiting, so I didn’t get the slides. That’s why every number and fact in this piece that carries a source number was checked against public material, and anything I only heard in the room is flagged as such. A good part of the talk overlaps with the slides an executive from the same company presented publicly at Hot Chips 2026 on August 23, so the broad outline can be checked against that public presentation [1].

The audience questions ended up focused on the TSMC relationship, but there’s something to look at before that: how far the in-house 2.5D has actually come, and why it’s being built. The idea that the relationship had gone bad was the questioner’s guess. The company never said so.

2. Where Part 1 Left Off

In Part 1, SK hynix’s Four Packaging Paths: Where Is the Fight After HBM?, I laid out four paths in advanced packaging, filed silicon bridges and 2.5D under Path 4, drew the map and left the rest for later. In August 2024 the company’s vice president in charge of packaging development was reported to have said in a lecture that the silicon interposer underneath 2.5D was close to a “chicken rib,” something of little use yet hard to throw away [2]. In December 2025 came a report that the company was pushing to build its first 2.5D production line in the US, and the company’s response was that nothing specific had been decided [3]. In May this year a Korean outlet reported that it was pursuing 2.5D packaging cooperation using Intel’s EMIB (Intel’s approach of burying a small silicon bridge in the package substrate to connect chips) [4], and the word 2.5D doesn’t appear even once in the official groundbreaking release of August 28 [5]. That release introduced the Indiana fab as an HBM production line plus an advanced packaging R&D testbed.

But at this roundtable, what came out was that the company has been preparing its in-house 2.5D for two years and that the Indiana fab will take the technology first. Going by public material alone, this is a company that called the interposer a chicken rib, said nothing had been decided about a US 2.5D line, and left 2.5D out of its groundbreaking release. Meanwhile, behind the scenes, it had been building a test vehicle, and this time the specs came out in some detail.

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TL;DR

• SK hynix is the HBM leader and its stock is up more than fivefold in a year. Yet at a roundtable of the company’s Global Forum in the US on September 18, a packaging development executive said there isn’t much time left to get by on memory packaging technology alone, and I took him at his word.

• The reason he says so is that the three walls, scaling, memory, and heat and power, are really one problem. Push bandwidth and power goes up, push power and heat goes up, and making devices smaller can no longer break that loop.

• So gaps open in the memory hierarchy, and packaging splits four ways to fill them: HBM extension, VFO, heterogeneous stacking, and chiplets with 2.5D. The fight after HBM happens in packaging platforms more than in memory chips.

• While matching the listed suppliers of each path against filings and earnings materials one by one, interestingly, I think I found something. Korean companies that all get filed under “test and inspection” posted opposite results in the second quarter.

• My lead: whichever of the four paths wins, you still have to screen parts before you bond them, so the money goes to test and inspection first.

Contents

1. The Roundtable on the Afternoon of September 18

2. The Three Walls Are One Problem

3. The Gaps in the Memory Hierarchy

4. The Four Path Map (Paywall)

5. Which of the Four Comes First

6. Where the Money Goes: Test and Inspection

7. Same Test and Inspection, Different Second Quarter

8. Closing: Base, Alternative, Downside

9. References & Sources

1. The Roundtable on the Afternoon of September 18

SK hynix shares have risen more than fivefold over the past year. At the September 18 close its market cap sat in the $970 billion range, with $1 trillion in sight [1]. Few would argue that this is the number one company in HBM (high bandwidth memory, the AI memory made by stacking DRAM dies vertically and placing them right next to the GPU).

From a packaging development executive at that company, I heard in person that there isn’t much time left to get by on memory packaging technology alone. It was at the afternoon roundtable of the Global Forum SK hynix held in the US on September 18. It was a recruiting event, so I went in casually, but the afternoon roundtable turned out to be the most technical session of the day. The talk ran under 40 minutes and the questions went on for more than an hour. They never stopped.

Everyone seemed unsure what to make of it. Even so, people were interested enough that they kept trying to speak up just to get a chance to ask a question.

It didn’t sound like false modesty. Right after came a self-diagnosis that the company lacks knowledge of logic (compute chip) devices and logic packaging. Public material carries the same temperature. At the SK hynix Future Forum held in Icheon on September 8, the vice president in charge of advanced packaging development said that 3D technology is changing even the technical boundary between the fab and packaging [2].

Late in the roundtable the speaker raised one point that he prefaced as his personal view. Today the package is built around the GPU and HBM fits itself to that. But the value of the HBM inside a package has passed that of the GPU die, and structurally HBM has also become the part most likely to break, so shouldn’t the package be built around HBM instead? (The value comparison is a number I haven’t verified myself.) At first I was taken aback. It means a memory company wants to lay out the GPU package on its own terms. The first thing that came to mind was whether TSMC would sit still for that, and someone in the audience asked exactly that. The speaker himself drew a line and said the company doesn’t have the capability to do it right now. Part 2 covers this separately.

Why would the company doing best in HBM be uneasy? If I boil down the answer I heard into one sentence, the fight after HBM happens in packaging platforms more than in memory chips. On September 17, in [Investment Map] 22 Listed Companies in the Hybrid Bonding Value Chain, I mapped twenty-two hybrid bonding equipment companies. After this session I realized that map covered only one of four paths. This piece is the first of three and maps all four. Part 2 is 2.5D, which spreads sideways, and Part 3 is 3D, which stacks upward.

One thing up front. The event was a closed, invitation-only session and I didn’t receive the slides. So every number and fact in this piece that carries a [number] has been rechecked against public material, and anything I only heard in the room is flagged as such. Fortunately, a large share of the talk overlaps with the slides the same company’s packaging executive presented publicly at Hot Chips 2026 on August 23 [3][4].

2. The Three Walls Are One Problem

The talk opened with three walls. The scaling wall, where making devices smaller no longer lifts performance the way it used to. The memory wall, where memory can’t feed the compute chip the data it needs in time. And the heat and power wall, which appears when you try to close that gap with power.

The memory wall has come up many times in this series. As I wrote in July in Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains, compute speed jumps every generation while the speed of pulling data out of memory, the bandwidth, doesn’t keep up. So I won’t repeat it at length here. The space goes to what was new to me this time, the other two walls and the way the three interlock. HBM is the current answer to the memory wall. It stacks DRAM and connects the layers with copper pillars drilled vertically through the silicon (TSVs), which multiplies the lanes data can travel on. Going by the HBM4 numbers on the Hot Chips slides, one cube has more than 20,000 TSVs and a little over 16,000 tiny solder bumps (microbumps) on its underside, and bandwidth exceeds 2 terabytes per second [4].

But the only ways to raise bandwidth are to add lanes or to run each lane faster, and both eat power. In the panel discussion at the event, the executive in charge of system architecture put it as “buying bandwidth with power.” The same Hot Chips talk has a slide saying that with bandwidth doubling every two generations, the thermal burden carried by existing process and packaging has grown 2.2 times [5][4], and another chart where HBM power consumption rises each generation and crosses the system limit line at HBM4 [3].

This matters because of where the heat is generated. At the very bottom of an HBM sits the floor chip that exchanges signals with the GPU (the base die). It draws the most power, and heat-sensitive DRAM is stacked layer upon layer directly above it. The iHBM that SK hynix unveiled in May targets this spot. It names the region of the base die that faces the GPU as the hotspot and adds one more exit path for heat inside the package, cutting thermal resistance by more than 30 percent. It applies from HBM5 onward, and the press release stressed design compatibility with the customer’s existing SiP (system in package, several chips bundled in one package) environment [6].

Then why not improve the devices and cut power? That’s the scaling wall. The voltage that drives DRAM has already come down to around 1 volt and has almost no room left to fall, according to the explanation in the room. So starting with HBM4, SK hynix decided to make the base die on TSMC’s leading-edge logic process instead of its own DRAM process [7]. The Hot Chips slide also labels the base die position “Logic Foundry” and gives power efficiency as the reason [3]. The DRAM cell side is in a similar place. At the VLSI symposium in June last year, SK hynix’s CTO said it is hard to keep scaling with the current structure at the 10 nm class and below, and put on the roadmap a new structure that builds the cell upright together with wafer bonding that places the circuit part under the cell [8].

That was long, so to sum it up a little: raise bandwidth to get over the memory wall and power goes up, power goes up and heat hits the DRAM, and the road to fixing that through device scaling is blocked. Push on one wall and the wall next to it gives way. So the road that remains is how you stack the chips, where you place them, and what you connect them with, which is to say packaging.

One more thing attaches here. It also isn’t a problem that can be solved inside the HBM package alone. On the panel it was said that reducing heat inside the HBM package has hit its limit and that it now has to be solved at the SiP level, GPU included. In public material, a Hot Chips slide says the same. Memory used to go in at the last step of system assembly, but in advanced packaging for AI, HBM goes in at the first step of assembly and the reliability burden has grown as a result [3]. The same speaker is reported to have said that HBM’s own performance isn’t enough and that the GPU, packaging and foundry all have to be optimized together with the customer [9].

The Hot Chips numbers in this piece are values I read directly from the slide images instead of from article text. Opening the slides again one by one, I found wrong numbers mixed into secondary outlets’ summaries. That story comes in chapter 4.

3. The Gaps in the Memory Hierarchy

Once the walls become a packaging problem, the next question is what goes where.

Fifteen years ago the memory hierarchy was simple. SRAM inside the compute chip, DRAM outside it, storage behind that. HBM was a new tier that squeezed in between SRAM and DRAM, and now more gaps are visible on either side of it. In its FMS 2026 keynote in August, SK hynix said competitiveness is no longer decided by a single memory product but by where each tier is placed and how the tiers are connected to reduce data movement [10].

Start between HBM and SSD. That’s where HBF (high bandwidth flash) goes. The idea is to stack NAND with TSVs the way HBM does and deliver SSD-class capacity with bandwidth close to DRAM, and SK hynix and Sandisk published the first standard specification in August. Up to 512 gigabytes, NAND stacks of 8 and 16 layers, and three bandwidth grades from 0.4 to 3 terabytes per second [11]. I covered HBF in January in HBF (High Bandwidth Flash) and Optics: The Missing Link in AI Infrastructure. Between DRAM and storage goes CXL pooled memory, where several servers share memory, and there were live demos at the same event [10].

The newest gap is between SRAM and HBM. It’s 3D stacked DRAM, which places DRAM directly on top of the logic chip. SK hynix introduced this structure publicly at the TSMC symposium in April [12], and at the Future Forum in September it set three directions: widening the data bus as far as it will go, cutting transmission distance to the extreme, and using a logic foundry process for the DRAM peripheral circuit [2]. In July it was reported that the San Jose office had started hiring engineers to co-design the logic die with a US customer [13].

The reason to go up at all lies at the edge of the chip. HBM sits side by side with the GPU and connects through wiring that runs along the chip’s edge. Edge length is fixed, so placing memory alongside limits how many lanes you can add. That was the explanation in the room. Put the memory on top and the entire contact face becomes the lane.

The gaps SK hynix is trying to fill in the memory hierarchy and the packaging each gap needs. Tier, product, disclosed stage and source in one table

Everything up to here is within what anyone can see in public material. Each gap needs different packaging, so packaging splits into four paths, and each path has different companies selling equipment and materials. Is there a seat that gets paid on all four paths? The slide below is the starting point.

SK hynix Hot Chips 2026 slide “Advanced PKG Future Direction”. Three stages: 2D (package to package on board), 2.5D (die to die on interposer), 3D (die on die).

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• Lumentum’s OCS (optical circuit switch) revenue went from zero to more than $100 million a quarter in one year, counting from August 2025 when it recognized its first OCS revenue.

• And yet an OCS is a million times slower than an electrical switch. It doesn’t convert light into electricity and only turns its direction with mirrors, so half the transceivers and the switch chip drop out of the spine tier.

• Google has used these mirrors for a decade in two places, the spine and the TPU pod, and per its paper cut capex by 30% and power by 41%.

• Two Google papers give an arithmetic that could explain why vendors these days all seem to converge around 300 ports, as if by agreement. In patent gazettes and company materials I also found traces of a hyperscaler outside Google and a company from an adjacent industry entering this market.

• To note only the direction up front, I think today’s MEMS mirrors are enough for training, and so I think the contest for the next generation of SiPh switches lies in size and integration more than in speed.

Abstract

Lumentum’s OCS (optical circuit switch) revenue went from zero to more than $100 million a quarter in one year, counting from August 2025 when it recognized its first OCS revenue. And yet this product is a million times slower than an electrical switch. In February I wrote a piece introducing how OCS works and who the players are, and this time I wanted to layer cost and demand on top of it. So this article follows two threads. The first is how much removing the electrical conversion really saves, and whether a mirror that moves in ms (milliseconds) is enough for AI training. The second is how far this demand spreads beyond Google and how high the market forecasts have climbed. While lining up the sources, interestingly, I think I found something. Two Google papers give an arithmetic that could explain why vendors these days all seem to converge around 300 ports, as if by agreement. And while digging through patent gazettes and company materials, I also found traces of companies that looked far removed from OCS entering this market. To note only the direction up front, I think today’s MEMS mirrors are enough for training, and so I think the contest for the next generation of SiPh switches lies in size and integration more than in speed.

Contents

1. $100 Million a Quarter in One Year: Lumentum’s OCS Numbers

2. From Port N to Port M: What a Switch Does, and OEO

3. Where Google Put the Mirrors

4. The Cost Arithmetic of Removing OEO

5. Is a Millisecond Mirror Enough?

6. Loss Budget and Port Count: Why 300 Ports

7. Where a Slow Mirror Is Enough, and Where It Falls Short

8. After MEMS: A Question of Size and Integration

9. A Company Crossing Over from an Adjacent Industry

10. Demand Outside Google

11. Market Size Forecasts and Listed-Company Exposure

12. Conclusion and the Dates to Check

1. $100 Million a Quarter in One Year: Lumentum’s OCS Numbers

On its August 11 earnings call, Lumentum said its guidance for the current quarter (FQ1 27) includes the company’s first “triple-digit” OCS revenue quarter. The unit is millions of dollars, so that means more than $100 million in a quarter, and the CEO added that it would come in “meaningfully above” that level [1]. The guidance came after OCS shipments doubled quarter over quarter in the prior quarter [1].

When was this product’s first revenue? On the August 2025 call, Lumentum said it recognized its first OCS revenue with shipments to two hyperscale customers [2]. So it took one year to go from zero revenue to $100 million a quarter. Connecting the dots in between through the disclosures looks like this. The February results release this year carried the sentence that OCS backlog had gone “well beyond $400 million” [3], and on the May call the company referred to a multi-year, multi-billion dollar purchase agreement and said it has three customers, two of which make up the majority of the volume [4]. On the August call it confirmed that the plan for $400 million of OCS revenue in the second half of this year is “tracking,” though it “would not say tracking ahead” [1].

Lumentum OCS disclosure timeline, from first revenue in August 2025 to the $100 million quarter guided for September 2026

I should note one thing I couldn’t confirm. The “multi-billion dollar agreement” from the May call exists only as a CEO remark, and I couldn’t find a separate disclosure even after going through the IR press release list and the SEC 8-Ks. The company has never said who the customer is either. In this article I accept only that the agreement exists and leave the customer’s name in the realm of estimation.

LITE closed at $893.61 on September 17, with a market cap in the $80 billion range and a one-year return of no less than +430% [5]. Most of that rise was made by the laser and transceiver cycle, and I covered that story in Lumentum’s First $1B Quarter: FQ4 2026 Earnings Analysis. In A Conversation with Lumentum, which I put out with Aurelion Research in July, Lumentum IR was asked about the company’s core competencies and ranked InP lasers first and MEMS and optical switching second, saying this side would become another pillar. Those aren’t verbatim remarks. They’re carried over from Aurelion’s meeting notes. Today I pull out only OCS from all of that. It’s the product the company calls a “key growth driver,” yet there doesn’t seem to be much explanation in the market of why this thing actually sells.

2. From Port N to Port M: What a Switch Does, and OEO

I’ve been interested in MEMS optical switches for a long time. Optical switches that work well already exist, but they are bulky, their insertion loss is unnecessarily high, they are expensive, and they operate in a more complicated way than you’d expect. Optical switches are essential not only in data centers but all the way to the lab. As port counts grow and systems get more complex, a switch is essential equipment, so I have high expectations for this optical switch and OCS market.

If you reduce what a data center does to its simplest form, it’s a repetition of sending data that came in on port N out on port M. With tens of thousands of servers, the combinations of N and M become astronomically many, and the equipment in the middle that decides the route is the switch. Until now this job has been done by electrical switches, more precisely packet switches. A packet switch receives data in small bundles (packets), reads the address on each one, and sends it to the destination port.

But the long links inside a data center are already optical fiber. To read the address of a signal that arrived as light, you first have to convert it to electricity (optical to electrical), process it on a chip, and then convert it back to light to send it out (electrical to optical). This is called OEO conversion for short. Every pass through a switch means two transceivers (optical-electrical conversion modules) and a switch chip drawing power, plus the cost of that equipment. With three tiers, this conversion repeats several times on every path.

An OCS skips this conversion. It doesn’t convert light into electricity. It only turns the direction of the light, as light, and sends it from port N to port M. The most proven approach tilts hundreds of tiny mirrors made with MEMS (micro-electro-mechanical systems) to reflect the light. The principles and the introduction by approach are in Mapping the AI Landscape with Light: How OCS Transforms the Data Center Physical Layer, which I wrote in February, so I won’t repeat them here.

A packet switch converts light to electricity and back to light, while an OCS only redirects the light with two mirrors

What an OCS can’t do needs to be made clear instead. An OCS can’t read a packet’s address. It never converts the light to electricity, so that’s only natural. So an OCS is closer to equipment that lays down a circuit, saying “for the time being, port N and port M are tied together directly,” than to equipment that changes the route for every packet. Think of how a telephone operator used to plug in the cords. This difference keeps mattering later on.

Something in this picture changed as we moved to AI data. Unlike web traffic, AI training traffic is mostly decided before the job starts, in terms of who talks to whom and how much, and once decided, the same pattern repeats for hours. The volume is far larger too. If the amount of light that has to be delivered here and there inside the N x M matrix goes up while the pattern stays predictable, the reason to place expensive equipment that reads the address of every packet at every tier shrinks. I see this point as where OCS demand starts.

3. Where Google Put the Mirrors

The first to lay down OCS at data center scale was Google. In a 2022 SIGCOMM paper, Google disclosed its in-house OCS called Palomar. It has 136x136 ports (128 in use plus 8 spares), switching time on the order of ms, insertion loss (the amount of light lost passing through the switch) of 2dB in the worst case, and total system power of 108W, and the paper says tens of thousands were built and deployed over the past decade [6].

First is the top tier of the data center network, the spine. The Jupiter network paper from the same year reports the results of removing the packet switches in the spine tier and replacing them with OCS. The body of the paper states a 30% reduction in capex and a 41% reduction in power [7], and around the same time Google summarized it on its official blog as 30% higher throughput, 40% less power, 30% less cost, and 50x less downtime than the best known alternatives [8].

The other place is inside the TPU supercomputer. According to the 2023 TPU v4 paper, 64 chips are grouped into one block (a cube), and 64 cubes are connected by 48 OCSes to make a pod of 4,096 chips. Because the OCS decides with mirrors which face of which cube attaches where, the same hardware can produce a differently shaped topology (connection structure) for each job. The number I paid the most attention to in this paper is the passage saying OCSes and optical components are less than 5% of system cost and less than 3% of system power [9].

The cube-to-OCS connectivity figure from the TPU v4 paper. Source: Jouppi et al., ISCA 2023

This structure is unchanged in the latest generation. In its Ironwood (TPU v7) post last November, Google Cloud said the cubes are connected by an OCS network and that the largest configuration, the superpod, is 9,216 chips, or 144 cubes. It also explains that when one cube fails, the OCS management software optically bypasses that cube [10].

But why was it Google, of all companies, that went first? Reading the papers, the reasons overlap. In a typical Clos architecture the spine tier has to be pre-built at the scale of the whole building, and the Jupiter paper explains that this ties data center bandwidth to the speed available when the spine was deployed [7]. Google tried to avoid this problem by swapping the spine for mirrors that don’t care about speed, but there was nothing suitable to buy. According to the Apollo paper, the largest commercial OCS Google knew of at the time had a few tens to hundreds of duplex ports, and for the first several years of deployment it used an outside vendor’s product but decided on internal development because reliability and quality were hard to maintain at scale [6]. Software comes on top of this. An OCS can’t read packets, so someone has to decide centrally which ports to tie together and when, and Google already had its own SDN (software-defined networking) controller called Orion, along with traffic engineering [7]. One company held the need, the hardware and the software all at once. And having used it in production for nearly a decade [6] before publishing the numbers in papers, the perception that “OCS means Google” was bound to form.

That was long, so to sum it up a little, Google has used OCS for a decade for two purposes, as “cost-saving equipment” and as “topology reconfiguration equipment,” and the numbers for both uses are public in papers. That’s why any talk of the OCS market has to start with Google.

4. The Cost Arithmetic of Removing OEO

The money an OCS saves can be counted from structure alone, without knowing the price tags.

In a leaf-spine structure built with packet switches, for data from server rack A to reach rack B, it goes up from leaf switch A to a spine switch and comes down to leaf switch B. One transceiver at each end of the optical link going up and one more at each end of the link coming down add up to four transceivers and one pass through a spine switch chip. Put an OCS in the spine position, and the light from leaf A’s transceiver reflects off the mirrors and goes straight into leaf B’s transceiver. That’s two transceivers and zero passes through a switch chip. In that tier the transceivers are halved and the spine chip disappears altogether. Look at the orange path in the figure below.

Transceiver count on a leaf-spine path versus an OCS path. Four versus two

This is where the 30% capex and 41% power reductions in Google’s Jupiter paper come from [7]. The power gap per box is large too. One Palomar is 108W [6], and Lumentum claims its 64-port product, the R64, is under 150W with 80% less power than a packet switch doing the same job [11]. The 80% is a vendor claim, so it’s hard to take at face value, but the power to tilt a mirror and hold it there and the power of a chip processing tens of Tbps differ by orders of magnitude to begin with, so there seems little reason to doubt the direction.

The item I consider more important in the cost arithmetic is the depreciation period. A packet switch bought in the 400G generation has to be replaced when moving to 800G and 1.6T, because the chip has to process that speed. A mirror doesn’t know whether the light it reflects is 400G or 1.6T. Change only the transceivers and the OCS stays in service. The Apollo paper makes this point as well. The optical switching layer becomes part of the building, like the power and cooling infrastructure, and capex can be amortized over the lifetime of the building, measured in decades, far longer than the few years of equipment life [6]. The Jupiter paper wrote that the 40G, 100G and 200G generations were incrementally mixed in on the same structure [7]. That said, the public papers don’t confirm how many generations an individual Palomar unit was reused across. The arithmetic that equipment replaced every 3-4 years and equipment used for 10 years differ two to three times in annual cost at the same price holds on that premise.

So here is how I read the “less than 5% of system cost” number [9] in the TPU v4 paper. It’s a trade where, in a supercomputer worth hundreds of billions of won, less than 5% of the money buys topology reconfiguration and failure bypass. If, when one chip dies, the pod keeps running minus one cube instead of stopping entirely, 5% is cheap even as an availability insurance premium. This calculation has a limit, though. The 5% and 3% are based on Palomar, which Google built itself, and there’s no public source that redoes the calculation at the price of buying from outside vendors.

5. Is a Millisecond Mirror Enough?

The cost logic is this clear, but one question arises here. A mirror that is tilted mechanically moves in ms. An electrical switch processes packets in ns (nanoseconds). Equipment a million times slower is sitting in the middle of the most expensive computers in the world. Is this a sufficient speed or an insufficient one, and what could the answer be?

This question matters because the market’s next stage depends on it. This year alone, big money went into startups building SiPh (silicon photonics) based fast switches. iPronics announced a $125 million Series B with NVIDIA participating on September 2 [12], and nEye took an $80 million Series C in April, with Alphabet’s CapitalG and Microsoft’s M12 on the investor list [13]. One thing these companies put forward is switching speed tens of times to, at the high end, more than ten thousand times faster than a MEMS mirror. If the ms mirror is already enough, who is this speed being sold to? And if it isn’t enough, Lumentum’s $100 million quarter becomes revenue from a transitional product.

Google wrote down its own answer to this question in one paragraph of the Apollo paper.

The paragraph in the Apollo paper on ms switching and the future opportunity for faster switching. Source: Urata et al., SIGCOMM 2022

But while preparing this article and digging through patent gazettes and company materials, things I didn’t expect turned up. On September 17, the US Patent Office published an application in which a hyperscaler other than Google describes a design that ties 10 buildings together with OCS. That’s quite a different picture from the conventional wisdom that nobody besides Google takes OCS seriously. One company that made chips for autonomous-driving LiDAR has turned the same chip toward OCS and opened a product page. I’ll name the companies in the paid section.

The paid section below starts with the loss of light, which is the cost an OCS pays, and the arithmetic that could explain why 300 ports of all numbers, then continues through the reading of the Apollo paragraph, the technology after MEMS and the identity of the companies above, and on to demand outside Google, the market forecasts, and which listed company has the larger OCS exposure.

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• BESI grew its second quarter orders 129 percent year over year and still fell 46 percent from its June 15 all-time high to the September 14 close, and that drawdown is the price put on the signal that the adoption clock for memory hybrid bonding keeps sliding back.

• One of the decisive blows was SK hynix’s remark at Hot Chips on August 23, which said that through HBM4E it stays on the existing method and hybrid bonding starts at 20-high, so on SK hynix’s schedule a window of close to three years opens as the delay window, from HBM4E mass production in 2027 to 20-high HBM5 in 2029 or later.

• But what slipped is hybrid bonding on the HBM side, while logic is already shipping hybrid bonding products with Apple M5 Pro, AMD MI455X and Intel Xeon 6+, and most of the hybrid bonders BESI sells today are for logic and CPO, so the market priced in only the memory delay and the logic revenue is unchanged.

• I measured, stock by stock, which direction and how far each of the 22 listed companies in the hybrid bonding value chain moved against its index on this year’s four delay shock days, March 6, July 6, July 23 and August 24, and interestingly, I think I found something. The stocks that rose on the shock days and the top stocks on this map, scored on five axes, barely overlap.

• My lead is that during the three-year delay window, the money goes first to the steps before and after the bonder rather than to the bonder.

Contents

1. June 15 and September 10

2. Why I Am Drawing This Map

3. Background One: The 775 Micrometer Envelope

4. Background Two: Logic Is Already Shipping on Hybrid Bonding

5. What the Three Memory Makers Each Said

6. 22 Companies and Five Layers

7. The Five Axes

8. Measured: Delay Shock Sensitivity

9. The Ranking, and What Happens When You Overlay Sensitivity

10. Company Cards

11. Catalyst Calendar: The Next 12 Months

12. Checking the Earlier Call

13. Closing

14. References & Sources

1. June 15 and September 10

BESI printed an all-time intraday high of 328.40 euros on June 15 [1], and three days later at its Investor Day it raised its 2030 revenue target range from 1.5-1.9 billion euros to 1.7-2.2 billion euros [2][3], and then it fell 46 percent from that peak in three months. The September 10 close was 184.10 euros [4], and on September 14, as I was finishing this piece, it came down once more to 175.95 euros [5].

The results numbers do not explain this drawdown. In the second quarter results on July 23, revenue was 249.9 million euros, up 69 percent year over year, and orders were 292.9 million euros, up 129 percent. Hybrid bonding customers went from fifteen at the end of last year to twenty-one [6]. Yet the stock fell more than 7 percent that day. As Morgan Stanley pointed out, the reason was reportedly that there was no hybrid bonding order from a memory customer [7]. If that happened even on a day it put out order numbers like those, then what decides this stock’s day is news about when memory hybrid bonding arrives, more than the quarterly numbers. If you have held BESI or are watching it now, you will have seen the share price shake every time that news comes up, and what I was more curious about than the size of the drawdown was what the days this stock fell hard had in common.

Of the days this year when BESI fell more than 5 percent in a single session, four were all about the same subject. On March 6, the day TrendForce relayed a Korean report that JEDEC members were discussing raising the HBM package thickness from 775 to 825 or 900 micrometers, the stock fell 17 percent on a closing basis [8][4]. On July 6, the day ZDNet Korea wrote that 16-high HBM discussions were not active and that HBM4E would also be mainly 12-high, it fell 7 percent and change [9][4]. July 23 was results day, and the three days from August 24 were the Hot Chips digestion period. In this article I will call these four days the delay shock days. Section 8 attaches the moves of the twenty-two stocks on these four days. On those four days, how many of the twenty-two stocks went the opposite direction from BESI?

BESI daily close in 2026 with the four delay shock days and event ledger. June 15 intraday high 328.40, September 14 close 175.95

One thing needs correcting here. The market says a lot that “JEDEC relaxed the thickness spec, so hybrid bonding got pushed out,” but the only thing that is actually fixed is HBM4’s 775 micrometers. A value raised from 720 to 775 by member consensus in early 2024 was carried into the HBM4 standard (JESD270-4) published last April [10][11]. 825, 900 and 1,000 micrometers are all numbers that Korean media reported as “under discussion” in March, April and July this year, and the finalization is said to come in the second half of next year [12]. JEDEC decided nothing new in August or September.

So what happened at the end of August? A customer spoke, rather than a standard. At Hot Chips 2026, Jaesik Lee, vice president at SK hynix America, said the company goes with advanced MR-MUF through HBM4E and is preparing hybrid bonding for 20-high and above [13]. 12-high HBM4 is in mass production and 16-high is in customer qualification [14][15]. Three days later KBC Securities cut its 2030 estimates in a note titled, in effect, “the memory industry is not warm on hybrid bonding yet.” The gist of that note was that Micron has no roadmap at all, Samsung is solving bandwidth through the base die, and Nvidia is speccing toward lower stack heights [16]. If the spec discussion showed the direction, the customer’s remark nailed down the timing.

The September 14 decline was different in nature. On Saturday the 12th, Anthropic’s Dario Amodei posted that the pace of capability gains in frontier models should be slowed, OpenAI’s Altman and xAI’s Musk agreed, and Altman said an IPO this year would be too much [5]. On Monday the Philadelphia Semiconductor Index fell 6 percent, SK hynix 7 percent, Samsung Electronics, Micron and Applied 5 to 6 percent, and BESI 7 percent. That was an AI investment sentiment shock unrelated to hybrid bonding, and I did not include it in this article’s four shock days. Still, that day shows well that BESI is not a stock that moves on this one subject alone.

2. Why I Am Drawing This Map

I held BESI from February and recently sold all of it. I made a profit. But after selling, watching this drawdown, I felt I needed to look at hybrid bonding more systematically.

Companies like BESI and ASMPT do not only bond HBM. There are countless places that need bonding, like silicon photonics and optical interposers. So I think one should not judge hastily on a single event.

In May I covered seven bonding equipment companies in 7 Bonding Equipment Companies Behind HBM4 and CPO: AI’s Real Bottleneck Lives in Assembly. In that piece I set the JEDEC HBM4E thickness relaxation as the downside scenario and wrote that if the relaxation became real, MR-MUF and TC-NCF would be extended one more generation and hybrid bonding would be pushed past HBM4E. That scenario became real through customer remarks first, without the spec being finalized. Section 12 checks the items I set out then, one by one.

There are two reasons I am drawing the map again. One is that the delay window is not short. On SK hynix’s terms, HBM4E mass production is talked about for 2027, and 20-high HBM5 is talked about for 2029 and later [17][18]. The question is where the money that was riding on hybrid bonding goes during a window of close to three years. The other is that the number of challengers grew in the meantime. ASMPT is sampling a second generation hybrid bonder, Hanwha Semitech’s tool went into SK hynix for evaluation, Semes’s tool went into Samsung, and China’s Naura unveiled a D2W bonder in March. On the front end side, Applied sells an integrated line bundled with BESI, and TEL, SUSS and EV Group hold the wafer-to-wafer side.

The questions are these. Whether the hybrid bonding clock slipping a generation is confirmed, and whether that delay is already in BESI’s 46 percent. Then, where the money goes during the delay window. I answer by splitting 22 companies into five layers.

3. Background One: The 775 Micrometer Envelope

HBM is made by stacking several DRAM dies. The numbers 8-high, 12-high and 16-high are that die count. But there is a ceiling on the stacked height. It is a component that sits side by side with the GPU, so its height has to match the GPU die, and the JEDEC standard sets that height. HBM3E was 720 micrometers, and HBM4 raised it to 775 [10]. Whether 12-high or 16-high, it has to fit inside this envelope.

To fit more dies into the same envelope, each die has to get thinner. By SK hynix’s explanation, at 16-high the core dies are ground to around 50 micrometers and the gap between dies is cut to half of 12-high [13]. The number 775 itself is a ceiling that came from logic wafers being 775 micrometers thick. But the way the dies are joined to each other becomes the problem. Today’s HBM places small solder bumps between the dies and presses them together with heat and pressure. This is called TC bonding, and SK hynix uses MR-MUF, which fills liquid molding material over it, while Samsung uses TC-NCF, which inserts a film. The two methods differ in how heat escapes. In MR-MUF the liquid molding material fills the space between dies and pulls heat out sideways as well, while in TC-NCF the film stays between the dies. That is why SK hynix compared the thermal paths of the two methods side by side in its Hot Chips slides, and it used that as the argument that its own method holds up to 16-high [13]. Because there are bumps, each layer gets thicker by the bump height, and because the bump pitch is around 30 micrometers, the number of signal lines is limited too.

Hybrid bonding removes the bumps. Copper pad meets copper pad directly, the dielectric films between them are bonded at room temperature, and then the stack is heated above 200 degrees so the copper bonds to copper. With no bumps the layer gets thinner, the pitch can shrink below 18 micrometers, and because copper touches copper directly, heat escapes well. Those are the numbers SK hynix cited at Hot Chips. With hybrid bonding at 20-high, the core die can be kept 24 percent thicker than with MR-MUF, and thermal resistance, read off the slide graph, is about 35 percent lower than TC-NCF and around 25 percent lower than its own MR-MUF [13]. Two days later the company newsroom’s tech note wrote that microbump pitch is around 20 micrometers while copper direct bonding goes below 1 micrometer, and that full adoption is most likely at HBM4E or HBM5 where stacks exceed 20 layers [19].

SK hynix Hot Chips 2026 presentation slides, 16-high customer qualification and the 20-high hybrid bonding plan

So why not use it at 16-high, and start at 20-high instead? SK hynix’s judgment is that 16-high fits under 775 micrometers with the existing method if the die and the gap are roughly halved. Grinding dies thinner and making bumps smaller is cheaper and more certain on yield than standing up an entirely new process. BESI itself said on the second quarter call that the hurdles on the memory side are cost and yield [20]. At 20-high that arithmetic breaks. Grind the dies thinner and they warp and crack, and the bump pitch cannot shrink further. That is why JEDEC members are discussing growing the envelope itself to 825, 900 or 1,000 micrometers, and if the envelope grows, 20-high can also go on bumps, so hybrid bonding gets pushed out one more generation. This is where the thickness discussion connects directly to bonder company share prices.

The story of stacking HBM higher is, in the end, one branch of the contest over where to add AI memory capacity. The bigger picture of whether to put it beside the GPU, stack it above, or place it far away over optics was covered in August in Beside, Above, or Beyond: The AI Memory Capacity Race and Where Optics Fits. This article looks only at one process in the “stack it above” branch, the one that joins layer to layer.

4. Background Two: Logic Is Already Shipping on Hybrid Bonding

This is the part the market tends to miss. Saying hybrid bonding got pushed out is an HBM story, and it is not a story about hybrid bonding as a whole.

TSMC’s SoIC is hybrid bonding. 3 nanometer chip stacking entered volume production in 2025, and the bond pitch shrinks from 6 micrometers in 2025 to 4.5 micrometers in 2029 [21][22]. The M5 Pro that Apple released this March is the first consumer product that joins a CPU die and a GPU die with SoIC [23], and the MI455X that AMD announced in July stacks eight 2 nanometer compute dies on 3 nanometer dies with hybrid bonding [24]. Intel attached twelve 18A tiles with 9 micrometer pitch Foveros Direct in the Xeon 6+ Clearwater Forest it launched in June [25][26]. Only Nvidia is not there yet. Rubin goes on bumps on CoWoS-L, and reports say SoIC starts with Feynman in 2028 [27].

Hyperscaler ASICs come in too. Broadcom said it started shipping the 2 nanometer 3.5D XDSiP compute SoC for Fujitsu’s MONAKA in February, and it is extending the same face-to-face hybrid bonding platform to other AI XPU customers [28]. The release of MONAKA itself is in 2027.

This is where BESI’s revenue comes from. As of the end of last year, cumulative orders for hybrid bonding systems passed 150 units, and the company said six integrated production lines built with Applied, with 30 BESI bonders, were installed at one “leading logic customer” [29]. The Investor Day material states the customer mix is “skewed to logic currently” [2]. The same material lists AMD, Intel and Apple as logic customers in production, and Broadcom ASIC and Nvidia Feynman on the roadmap [3]. So the hybrid bonders BESI sells today are mostly for logic and CPO, and memory is at the level of a few evaluation tools. The late August plunge was a reaction to news that something not yet in revenue would be later still.

BESI 2026 Investor Day slide on hybrid bonding customer mix and 2030 targets. Source: Besi, 2026-06-18

CPO is also logic side hybrid bonding. TSMC COUPE is a structure that joins the electrical chip and the optical chip with hybrid bonding, and the April OFC piece OFC 2026 Part 3 of 5: Packaging: Glass Substrates to 3D Hybrid Bonding covered why that structure beats bumps. BESI placed CPO as one of three axes alongside logic and memory at its Investor Day [2]. The same material states that COUPE-type electro-optical chip hybrid bonding is already at the production stage, so BESI’s hybrid bonder demand is already running on two tracks, GPU stacking and CPO.

That was long, so to sum up a bit: hybrid bonding’s 2026 revenue is logic, and the timing of volume adoption in memory, which was the growth story for 2027 onward, has been pushed back. SK hynix points to HBM5 and later, and only Samsung leaves open the possibility of earlier adoption at HBM4E. The market priced only the second, and the first is intact.

5. What the Three Memory Makers Each Said

But the three memory makers did not say the same thing. This is where the second axis of this map splits, so I write it in a little detail.

SK hynix is the clearest. MR-MUF through HBM4E, hybrid bonding from 20-high [13]. Research continues, though. In February it reportedly ordered one Kinex inline tool, the Applied and BESI bundle, for a development line at somewhere between 15 and 20 billion won [30], and in April Hanwha Semitech’s second generation hybrid bonder reportedly went in as an evaluation cluster [31]. Internal verification of 12-high hybrid bonded HBM was declared complete by the responsible team lead at an April conference, with the caveat that yield is better than two years ago but the economics are not there yet [32]. To sum up, the picture is buying the tools but mass producing from HBM5.

Samsung Electronics was, by contrast, the side pushing ahead. It sent hybrid bonded HBM4 samples to Nvidia, and in the May ECTC paper HCB lowered the thermal resistance of the HBM stack itself by about 19 percent versus TCB, with the improvement growing to 22 to 29 percent under higher pad density [33][34]. According to a July report by The Elec, it decided to build a mass production line of about 50 D2W hybrid bonders at Pyeongtaek P5 and put BESI at the top of the list, but at about 6 billion won per tool, double the competitors, negotiations over structural changes and price are reportedly dragging on [35]. Move-in from the end of this year, and the internal target for large-scale mass production is 2030. What Samsung emphasized at Hot Chips was the base die and side cooling rather than hybrid bonding [14]. Samsung’s official statement on hybrid bonding is actually on the January fourth quarter results call. It applied HCB to HBM4, delivered samples to major customers in the prior quarter, and plans partial commercialization at the HBM4E stage. On the same call it also said customer demand for 16-high HBM4 is very limited, so mass production is unnecessary [36]. At SEMICON Taiwan on September 1, it laid out a roadmap of HBM5 in 12-high, 16-high and 20-high with mass production around 2028, and zHBM from 2029 onward [37]. If 20-high HBM5 is 2028, that matches the timing of the P5 line. The Samsung packaging roadmap seen in July in TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM sits on that extension.

Micron did not show a hybrid bonding roadmap at Hot Chips. It went as far as saying there is a good path to 16-high and a lot of work remains beyond that, and its slide merely listed liquid cooling, hybrid bonding, and solder and side mold changes side by side as candidate answers to the thermal problem [38]. It said in its results release that HBM4E goes to a TSMC base die in 2027 [39].

One more variable attaches on the buyer side. In early August TrendForce wrote that Nvidia had begun widening its evaluation of the HBM configuration for the 2027 Rubin Ultra, from the original 12-high HBM4E to 8-high HBM4E and HBM4 [40]. The reason given was that next year’s HBM bit supply cannot keep up with demand. If the largest customer moves toward lower stacks, the point at which 16-high is needed itself moves back, and then the point at which hybrid bonding is needed moves back further. That report was three weeks before Hot Chips. On September 9, KLA also said at the Citi conference that some HBM customers are moving from 12-high to 8-high configurations because of memory price pressure [41]. The same story, from an equipment maker’s mouth.

Put the three companies on one line and it reads: SK hynix deferring, Samsung negotiating, Micron silent. The sentence BESI wrote at its Investor Day, “first memory production in 2027, starting with 16-high HBM4E,” [3] does not match these three lines. The only company that could keep that sentence in 2027 is Samsung, and Samsung is cutting the price right now.

Top of BESI’s Q2 results release, orders of 292.9 million euros and 21 hybrid bonding customers. Source: Besi, 2026-07-23

The 292.9 million euros in orders and the twenty-one customers in the capture above are as far as the picture goes from public sources, and the market saw those numbers and still pulled the stock down more than 7 percent that day. So the next question is how the other companies bundled under the same theme as this one took the same delay news, and from here on it is a picture you only see by overlaying public sources on each other. In the paid section I place the 22 companies in five layers around the bonder, score them on five axes, and on top of that attach, stock by stock, how far each one actually moved against its local index on the four delay shock days. The scores are my judgment, so I measured separately how the market actually saw it and overlaid that, and one axis is the signature of this map, measuring company by company whether a hybrid bonding delay is a gain or a loss. So the question becomes this. Whether the stocks that rose on the days the bonder fell are sitting in a position that keeps gaining through the three-year delay window. To give you one line in advance, the number one on this map is the stock that fell 46 percent, and number two is a company that sells no bonders at all.

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Contents

1. The September 1 Call and 30 Meters

2. The 10 to 30 m Skeptics’ Case

3. How Far MOSAIC Actually Sent Data

4. The Hyperlume Patent and the Fiber Variable

5. Fig. 4f in the SK hynix Paper

6. What Decides the Economics

7. Exposure by Ticker

8. Closing

1. The September 1 Call and 30 Meters

When I wrote in early July that five listed companies had crowded into microLED interconnect, $CRDO was near $257. The September 14 close is near $150, with a market cap in the $28 billion range [1]. It lost more than 40% in a little over two months, and over the same stretch the microLED news actually got better. That gap is why this piece exists.

On the September 1 call for the first quarter of fiscal 2027, Brennan put this into his prepared remarks. ALCs (Active LED Cables, active optical cables that use microLEDs instead of lasers as the light source) use micro emitters to carry the reliability and power advantages of copper out to 30 m, the company will demonstrate them at OCP in October, and first revenue stays in fiscal 2028 [2]. In the Q&A he went one step further.

“Key difference there is we will extend the length to 30 meters.” ... “I think that is just step 1 for ALCs and the micro emitter technology. A next natural step forward on that is to apply that to what comes with the scale up opportunity.” [2]

The 30 meters and step 1 passage from the Credo Q1 FY2027 call transcript

Revenue for the same quarter was $479 million, more than double a year earlier [3], and the full-year target of more than $600 million in optical revenue stood as before on the call [2]. So the first thing to check off is that the company pulling back its ALC schedule was at least not the cause of this drawdown.

He said the same thing at the Goldman Sachs conference on September 10. The company has been looking at micro emitters for three years, the promise is to take the 7 m of an AEC (Active Electrical Cable, a copper cable with a signal-restoring chip inside) out to 30 m while keeping the same reliability and power efficiency, and the cable is 75% smaller by volume than a 7 m AEC at 200G per lane [4].

So why does the number 30 m matter? Today the scale-up wiring (the links that bind GPUs together as one machine) ends in copper inside the rack. Going beyond the rack to a row takes 10 to 30 m, and until now that range has belonged to laser optics. Credo’s product page targets exactly this range [5]. And 30 m is exactly the distance the skeptics have said dispersion blocks.

2. The 10 to 30 m Skeptics’ Case

The original form of the objection is a 2022 IEEE Spectrum article. LED light is incoherent, so dispersion restricts it to about 10 m, one line [6]. That line still gets quoted a lot. In March this year Network World covered the Microsoft result and quoted Neil Shah of Counterpoint, who granted the power advantage but argued that chromatic dispersion limits reach, that dedicated cabling and rack changes cost money, and that adoption is hard without NVIDIA and AMD [7]. A December IEEE Computer Society piece is more technical. microLEDs have a wide divergence angle that makes fiber coupling hard, dense multicore fiber brings crosstalk between channels, and dispersion is only acceptable under 30 m [8].

Some terms need sorting here or the rest gets confusing. People lump this together as “interference between colors,” but three different things are going on. Chromatic dispersion is light of different wavelengths traveling through glass at different speeds, so a pulse with a broad spectrum spreads out front to back the farther it goes. Modal dispersion is light inside a thick-core fiber splitting into several paths and arriving at different times. Spatial crosstalk is light from a neighboring channel leaking into yours. Today’s wide-and-slow microLED designs, MOSAIC and Avicena’s LightBundle, do not stack colors onto one fiber the way WDM (wavelength division multiplexing, one fiber carrying separate channels by color) does. They send hundreds of emitters down separate cores in parallel, so colors colliding with each other was never the problem. The problem is chromatic dispersion from the fact that one microLED’s emission spectrum is far wider than a laser’s, not interference between WDM channels.

How much wider? By the Microsoft paper’s numbers, a laser linewidth is under 1 pm and a microLED’s is over 10 nm [9]. A full ten thousand times. Anyone can calculate how much that hurts. The material dispersion of fused silica at 450 nm is about -770 ps/(nm·km) (my own calculation from Malitson’s 1965 refractive index equation [10]). Assume a 25 nm spectral width and send it 50 m, and the pulse spreads by about 960 ps. At 2 Gbps one bit is 500 ps, so the smear is about two bits long. Cut the distance to 20 m and it is about 385 ps, inside one bit. One more thing to note here. Data center lasers sit in the near infrared at 850 nm or 1,310 nm, and the same calculation gives silica dispersion of -84 at 850 nm and close to zero at 1,310 nm [10], so a laser has a narrow linewidth and also sits at a wavelength where dispersion is practically absent. A microLED has to send a broad spectrum in the blue that GaN emits, which is the wavelength band where silica dispersion is largest, so the handicap is doubled. This one piece of arithmetic explains why this camp keeps lane speed around 2 Gbps and why the line falls somewhere between 20 m and 30 m (author calculation, a first-order estimate of material dispersion only, for silica, so actual fiber materials will differ).

Laser at 1 pm vs microLED at 25 nm, how far the pulse spreads at 20 m and 50 m

The orange bar in the figure is the spread at 50 m, and you can compare it with the bit period box next to it. So the physics the objection points at is correct. Reading the skeptics, I could not find a sentence that was wrong. But the conclusion the skeptics usually reach is “so 30 m is out of reach,” and for that conclusion to hold there would have to be no lever at all for reducing dispersion. If there are levers, the story changes. How the three light sources split by distance is covered in The AI Light Source War Is Not a Speed Race: InP, VCSEL, and μLED Are Buying Different Distances, so here I look only at the levers.

3. How Far MOSAIC Actually Sent Data

The evidence that levers exist sits inside the very paper the skeptics cite. MOSAIC, which Microsoft Research presented at SIGCOMM in September 2025 [9]. With a 100-channel prototype it sent 2 Gbps per channel over 20 m, and at 30 m it had to drop to 1.6 Gbps. To be precise, the bit error rate at 20 m was under 10 to the minus 6, more than 100 times below the error correction threshold used by Ethernet and InfiniBand. At 30 m, 2 Gbps edged just over that threshold, so they dropped to 1.6 Gbps [9]. A simulation assuming production-grade parts gives 2 Gbps at 50 m, and more than 8 Gbps per channel within 10 m [9].

MOSAIC paper Fig. 12, measured bit error rate by distance

There is one thing to be careful about when reading those numbers. The paper notes that hand-wiring 100 drivers was complicated, so each experiment ran 25 channels at a time [9]. It was not a measurement of 100 channels driven simultaneously. Still, they said any 25 channels could be chosen, so each channel on its own was validated.

How did they get past 20 m? One lever is the direction of the light. Without a lens a microLED emits into the whole upper hemisphere, ±90 degrees, but after printing a micro lens built on total internal reflection (TIR), the beam collimated into a ±12 degree cone, fiber coupling efficiency went up, and crosstalk between channels went down, according to the paper [9]. The paper’s claim is that these lenses can be mass-produced at wafer scale by nano-imprinting. The next lever is the fiber. They used imaging fiber, the kind used in endoscopes, with up to ten thousand cores in a single strand, and found it was actually better to spread one microLED across several cores [9]. The last is signal processing. Each channel runs NRZ with only two levels, 0 and 1, and because the speed is low the spread pulse is rebuilt with analog equalizers alone, with no DSP (the digital signal processing chip that eats a large share of today’s optical module power) and no ADC/DAC [9]. Error correction was not removed altogether. Instead of a separate high-speed FEC block inside the module, the design keeps the Ethernet PCS layer FEC as is, and adds a lightweight Hamming code plus spare channel switchover for channel failures [9]. Dispersion was not eliminated in the fiber. It was contained within a range that slow lanes and analog correction can handle.

What they got in return is power. The estimated power for one end of an 800G link, counting the host interface, the digital backend and the light source, is 3.1 to 5.3 W, more than half below the 9.8 to 12 W of today’s laser 800G optical links measured the same way, by the paper’s numbers [9]. The digital backend is only 0.4 W because there is no DSP and no ADC/DAC.

One more thing worth writing down here. 30 m is a number Credo did not produce first. Avicena announced at ECOC in September 2024 that it had extended LightBundle’s reach from 10 m to 30 m, and its CEO at the time said 100 m or more could be possible [11]. So Brennan’s 30 m is less a declaration that broke a physical limit than a listed company putting a distance a startup demonstrated two years ago into a product spec. 30 m has been shown separately in two places, and what remains is doing it in a production cable at a price.

4. The Hyperlume Patent and the Fiber Variable

As it happens, on September 3 the US Patent Office published one of Hyperlume’s applications. The title is “System for Optimizing Propagation and Dispersion of an Optical Signal” [12]. Hyperlume is the Ottawa microLED startup Credo acquired last September [13], and this application was filed in February 2025, seven months before the acquisition. Among the three inventors are Hyperlume’s CEO Mohsen Asad and CTO Hossein Fariborzi [12], so the front page also tells you this was a problem the founders worked on themselves.

The contents aim straight at the problem in the previous section. The background states that a microLED’s wide spectrum causes chromatic dispersion that cuts the effective bandwidth of a signal passing through fiber, and the solution works on the fiber, not the light source. It sets the core’s numerical aperture (NA, the range of angles a fiber accepts light from) between 0.17 and 0.7, the core diameter between 2 µm and 400 µm, suppresses modal dispersion with a GI (graded-index) structure in which the core’s refractive index falls off gradually from center to edge, and chooses the core material from fluorinated polymer, PMMA, or silica-based glass [12]. It comes with drawings. FIG. 7 plots the dispersion coefficient of the three materials on one graph from 400 nm to 1,600 nm, and FIG. 8 tabulates, for seven fiber samples with NA from 0.14 to 0.63, the bandwidth allowed by modal and chromatic dispersion at 1 m, 3 m and 10 m. At 10 m the chromatic dispersion bandwidth is 2.8 GHz for most samples and 5 GHz at best [12]. The line is drawn in the same place as the arithmetic in the previous section.

Hyperlume patent FIG. 7 dispersion curves and FIG. 8 dispersion bandwidth table

One line to draw in advance: 30 m appears nowhere in this patent. The existing microLED link distances in the background are 1 to 10 m, and the worked examples are 1 m, 3 m and 10 m [12]. So writing that this application is the technology that made the ALC’s 30 m would be an exaggeration. What I read into it goes this far: the team Credo bought had been building IP that handles dispersion through fiber design since before the acquisition.

How five listed companies came into this seat is laid out in The microLED Light Source Was Just Avicena. A Quarter Later, Five Listed Tickers Piled In. In that piece I wrote that microLED is an option inside platform names, and over two months the physics behind that option got thicker while the stock price fell.

So if the physics is solved, what fight is left? From here on we go past what public sources show. Why the material list in that patent caught my eye, where the money to cut dispersion in the fiber comes from, where the lane speed ceiling of a DSP-free equalizer sits, whose hands hold the cost of plugging hundreds of strands into a connector, and when those items reach each ticker’s P&L, that is the paid section. Before that, one picture from the memory side.

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• The government says it will catalyze 550 trillion KRW of private investment to build 8.4 GW by 2029, SK signed a 2 GW AI factory LOI with NVIDIA, and NAVER put out a 200 MW expansion plan for Sejong [1][2][3][4]. Every announcement names an accelerator and a memory company, but not one line says who supplies the optical interconnect that links rack to rack.

• OE Solutions, a Korean listed transceiver maker, booked 57.38 billion KRW of revenue for fiscal 2025 with 283 employees. Coherent sold 7.12 billion dollars in the fiscal year ended June 2026 with 51,480 people [8]. That’s a 166x gap in revenue.

• The Ministry of Science and ICT budgeted 3.85 trillion KRW for 140 Vera Rubin NVL72 racks next year. That’s 27.5 billion KRW per rack, against Bernstein’s rack cost estimate of 12.2 billion KRW. The government said it allowed for GPU price rises and facility costs, and NVIDIA said the configuration includes networking, cooling and storage, so a simple comparison doesn’t work [6][7].

• Korean companies do hold 400G and 800G optical module supply contracts. But a supply contract, in-house production, and domestic sourcing of core parts are three different things, and whether Korea’s supply chain can carry the certification, capacity and component sourcing an AI factory of this scale requires isn’t something the public record confirms. There is one layer where a Korean company has done its own production and delivery, and it’s a layer that wasn’t on the SemiAnalysis map at all.

• My base case is that the bill for this layer ends up with vendors outside Korea. But who takes each layer splits differently than you’d expect, and whether Korea ends up at the back of that line is still an open question.

Contents

1. The Layers SemiAnalysis Counted, and the One It Didn’t

2. The Plan in Practice: What the Announcements Say and What They Don’t

3. A Korean Supply Chain Audit: Who Is in the Optics Layer

4. 27.5 Billion KRW per Rack, and What’s Inside It

5. Five Layers, Five Bills

6. Dispersed Sites and Scale-Across

7. The Cross Constraint from the FCC Draft

8. How Far Localization Has Actually Come

9. The Price of the Queue, and What to Watch to Judge It

1. The Layers SemiAnalysis Counted, and the One It Didn’t

The conclusion of the September 1 piece is in its title. Nvidia wins, Hynix loses [9]. Follow the body, though, and what’s actually argued is a bit different. It estimates 2027 HBM4 pricing at 3.0 to 3.3 dollars per Gb for Nvidia versus 3.7 to 4.1 dollars for other tier-one customers like AMD and Broadcom, and reads the discount as the price of priority GPU allocation for SK Group [9]. That’s less an Nvidia win than value moving from SK hynix’s income statement to SK Group’s data center business. It’s a transfer between affiliates, and more a governance story than a semiconductor story.

Up to there it’s a well built analysis. But the piece counts two layers. Accelerators and memory. Inside the rack it’s dense, outside the rack it’s empty.

I’ve run into the same shape before. On the SemiAnalysis piece about Meta’s data center map, I dug one layer down in One Layer Below SemiAnalysis’s Meta Map: Scale-Across Is Coherent, Not CPO, and what was missing then was the connectivity layer too. The same spot is empty this time.

If SemiAnalysis covered accelerators and memory, the question left is outside the rack. Unpack the 8.4 GW plan into procurement line items and the layers Korea can build split from the layers where it has to stand in a foreign queue.

2. The Plan in Practice: What the Announcements Say and What They Don’t

The government announcement came at a national briefing in late June. The structure isn’t direct fiscal spending but pulling in private investment: 550 trillion KRW to build 8.4 GW by 2029, then another 10 GW by 2035 for 18.4 GW and over 1,000 trillion KRW of investment drawn in [1]. The sites line up as SK Telecom targeting 2 GW plus across the Gyeongsang region starting from Ulsan, GS at 2.4 GW in Donghae, Gangwon, and NAVER aiming at 1 GW in Sejong [16][17][18].

One thing to flag. SemiAnalysis wrote the plan up as 919 billion dollars [9], but 1,000 trillion KRW at the September 7 rate of 1,341.88 works out to 745 billion dollars [8]. Back-solving gives 1,088 KRW, and it’s unclear which point in time that rate is from. The KRW figures are the primary ones, so this piece works mainly in KRW and quotes dollars alongside with the rate stated.

On July 24, SK Group and NVIDIA announced a partnership of more than 500 billion dollars. SK Telecom builds a 2 GW NVIDIA Vera Rubin DSX AI factory, the first unit runs in 2027, and it carries SK hynix HBM4 [3]. But the form on the document is an LOI. That means it isn’t a binding contract, so the amount shouldn’t be read as committed capex [3].

The NAVER side is a bit more specific. The plan starts at 55 MW in the first half of 2027 at the GAK Sejong data center, grows to 200 MW in 2028, and ultimately aims at 1 GW. The 200 MW stage was reported at roughly 100,000 GPUs, NVIDIA plans to invest 1 billion dollars in NAVER, with conditions attached including NAVER separately finalizing at least 9 billion dollars of committed financing, and Brookfield has signed a nonbinding term sheet to fund up to 9 billion dollars [4][5].

Korea’s AI data center plan by procurement layer, and which layers are made at home

Now let’s reread these announcements from a procurement angle. The accelerator is named: Vera Rubin. The memory is named: SK hynix HBM4. Power and land have named owners: SK, GS, NAVER. It’s a structure that names a supplier for each layer, and only the optical interconnect goes unnamed. The full text of the SK-NVIDIA release contains none of the words networking, transceiver, optics or CPO [3]. The NAVER release is the same [4].

Concluding from absence in a press release alone is a weak argument. Releases never list everything. What gives this absence meaning is the next section. A Korean supplier that could take that volume on a 2027 schedule doesn’t show up in the public record.

3. A Korean Supply Chain Audit: Who Is in the Optics Layer

The representative listed company in Korea whose core business is optical transceivers is OE Solutions (138080). Founded in Gwangju in 2003, it has developed its own transceivers and laser diodes.

For the fiscal year ended December 2025: revenue 57.38 billion KRW, net loss 27.04 billion KRW, 283 employees. At 21,400 KRW on September 7, the market cap is 251.9 billion KRW [8]. It’s up 125.5% over one year and 63.5% year to date, so the market is clearly treating it as an AI data center name [8].

Here’s the control group. Coherent sold 7.12 billion dollars in the fiscal year ended June 2026, with net income of 805 million dollars and 51,480 employees [8]. At the exchange rate that’s 9.554 trillion KRW, about 166 times OE Solutions’ revenue, and 182 times on headcount [8]. Lumentum is at 3.01 billion dollars and 13,760 people [8]. Turn to China and Innolight is number one with 21.2% of the global optical interconnect market on 2025 revenue as stated in its Hong Kong listing prospectus (market definition per the prospectus) [23]. On scale it overlaps head-on with Coherent.

Revenue and headcount, OE Solutions versus Coherent

Put the numbers side by side and the feeling is a little strange. The optics supply chain standard-bearer of a country that says it will build 8.4 GW is a 283-person company with annual revenue in the 57 billion KRW range and a loss. It’s far below one quarter of one US company’s data center segment.

Of course, the comparison isn’t meant to run the company down. OE Solutions built its position on 10G and 25G telecom transceivers and has been widening the lineup toward datacom recently. It already has an AI product out. In March it announced a 23 dBm cooled ELSFP, an external laser source module for CPO, stated it was aimed at 1.6T scaling, and set sampling for the third quarter of 2026 [12]. So writing that Korea has no technology would be wrong. The issue is weight class, not whether the technology exists. And in an AI data center scale-out fabric, weight class can turn into a constraint on certification, capacity ramps and delivery response. Light sources alone are a market where TrendForce sees combined monthly capacity for EML and CW-DFB lasers at 50.7 million units in 2026 [22], so the units of certification and capacity are of a different order.

There’s one more Korean name. Opticore (380540) lists an 800G OSFP and a 1.6T OSFP for AI and high performance computing on its official product page, and between September 2025 and May 2026 it filed four supply contracts on DART for 400G and 800G AI data center optical transceivers. The amounts are 6.68, 6.01, 4.01 and 2.42 billion KRW, and the supply region is Korea in every case [28]. So current-generation optical module supply contracts held by a Korean company do exist. But read the filing tables and a different picture appears alongside. All four list the production method as in-house production not applicable, outsourced production applicable, and the counterparty was withheld as a trade secret and then disclosed only as a domestic server and peripheral supplier [28]. On top of that, the company has been suspended from trading since March 23, 2026 after its auditor refused an opinion on fiscal 2025, and it sits in delisting review with an improvement period granted [28]. So whether a Korean company is party to the supply contract, whether it makes the product in a Korean factory, and whether core parts like light sources and DSPs come from a Korean supply chain are three different questions, and this case answers yes only to the first.

The production-method row in Opticore’s DART supply-contract filing

Light sources show the same picture. There is no Korean name on the top supplier list for AI data center EML and CW-DFB lasers [22]. OE Solutions’ ELSFP is Korea’s first attempt in this layer, and for DSPs and packet switch silicon I couldn’t find a Korean candidate in the public record.

So this is what Korea’s sovereign AI procurement stack looks like. Memory is domestic, accelerators are imported, and the layer that connects them has products but no scale. That third layer is the subject of this piece.

So who fills this gap? As you’ve probably guessed, American names come to mind first, but split the supply chain by layer and the answer doesn’t come out in one line. There’s a layer American companies take, a layer where China is hard to exclude, and one layer where a Korean company has already done production. And the two commitments NVIDIA locked in with Coherent and Lumentum this March show who grabbed capacity access first [14][15]. Whether that actually reaches Korea’s place in the procurement queue is still a hypothesis.

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TL;DR

• The Defiance Quantum ETF rose 54.9 percent over the past year while the median of the four quantum pure plays was negative. Most of the return came from outside the obvious quantum stocks.

• On September 8, 2026, the US Commerce Department turned the first three May letters of intent into definitive agreements, putting $100 million each into D-Wave, Rigetti, and Quantinuum while taking equity stakes. Six of the nine remain pending.

• I measured “quantum purity” across 23 listed companies two ways: the Jensen shock and a 64-session quantum factor beta. Only nine show statistically significant quantum sensitivity.

• The highest-ranked company on this map is not a quantum pure play. Strip out optical interconnect, the signature axis of my own framework, and the same company still ranks first.

• Government capital lowers financing risk, not technology risk. It can keep funding from drying up. It cannot make the quantum computer work.

Contents

1. Two eras: 1,063 percent and minus 5 percent

2. Why I am the one drawing this map

3. Background one: qubits, errors, and logical qubits

4. Background two: five platform branches

5. The farther you go, the more light wins

6. The government attached conditions

7. Three frameworks

8. 23 companies and who works with whom

9. The five axes

10. Rankings, and quantum purity

11. The lag between tiers, and what I have not confirmed

12. Catalyst calendar: the next 12 months

13. Group mapping and hidden cards

14. Company cards

15. Scenarios

16. Where this framework breaks

17. Watchlist: private and adjacent

18. Closing

19. References and sources

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1. Two eras: 1,063 percent and minus 5 percent

Over 2024, Quantum Computing Inc (QUBT) rose 1,713 percent, Rigetti (RGTI) 1,449 percent, D-Wave (QBTS) 855 percent, and IonQ (IONQ) 237 percent. Simple average across the four: 1,063 percent. More than a tenbagger.

In the same year Coherent rose 118 percent, Tower Semiconductor 69 percent, FormFactor 5 percent, MKS and Keysight 1 percent each, while GlobalFoundries fell 29 percent and Hamamatsu fell 39 percent. Average across those seven: 18 percent.

Look only at 2024 and the answer seems obvious. If you want to invest in quantum, buy quantum companies. Why would you buy component makers.

But I think that rally was mostly hype with nothing inside it. Prices ran ten times over, to levels the revenue and product scale of the time could not explain. What changed that year was attention, not technology. Which is why one sentence from Jensen was enough to break it.

At the CES Q and A on January 7, 2025, Jensen Huang said this. “We are probably five or six orders of magnitude off. If you said 15 years for very useful quantum computers, that would probably be on the early side. If you said 30, it is probably on the late side. If you picked 20, a whole bunch of us would believe it” [2]. The next day Rigetti fell 45.4 percent, Quantum Computing Inc 43.3 percent, IonQ 39.0 percent, and D-Wave 36.1 percent [1][3].

That same day the tech names held up: Coherent fell only 3.9 percent, Keysight only 0.7 percent, and Hamamatsu Photonics actually rose 2.4 percent [3].

Single-session moves on January 8, 2025, four quantum pure plays versus seven component-layer names

One sentence from one person took 45 percent off some assets in a day, and other assets in the same industry went up on that same sentence. What that difference is, is where this piece starts.

That one-day move gets used again later. As a ruler for how much of a quantum stock a given name really is. This was the largest quantum sentiment shock on record, so how far a company moved that day is its quantum purity. The broad market barely moved: SMH, the semiconductor ETF, was down 0.7 percent. Meaning it was not a day when the whole market sold off.

Look at what came after that day and the direction flips. From January 7, 2025, the day before CES, through September 4, 2026, the four pure plays are down 5 percent on average. Over the same window the seven component and metrology names are up 129 percent. Tower Semiconductor 329 percent, Coherent 189 percent, MKS 131 percent [3].

Cut it to the last year alone and the picture holds. IonQ minus 4.1 percent, Rigetti minus 0.2 percent, D-Wave plus 7.2 percent, Quantum Computing Inc minus 45.2 percent. Average across the four is minus 10.6 percent, median minus 2.2 percent. IBM is flat too at minus 4.3 percent. The seven component and metrology names, meanwhile, are up 156.1 percent on average, 161.4 percent at the median [3]. Those seven are the ones just counted: Coherent, Tower, FormFactor, MKS, Keysight, GlobalFoundries and Hamamatsu. AXT is excluded because the InP cycle is what drives it.

One more number belongs here. Over that same year, the Defiance Quantum ETF (QTUM) rose 54.9 percent [3]. Which means that while a quantum ETF was up 55 percent, the median quantum pure play was down. So where did that 55 percent come from. As you would guess, the answer was outside the pure plays.

Something has to be said honestly here. The real driver that pushed the component layer into triple digits is, surprisingly, not quantum but AI. What took Coherent up 189 percent was optical demand from AI datacenters, and what took Tower up 329 percent is the same cycle. Quantum revenue at these companies is small enough that it does not get broken out in filings.

So this is as far as the data proves anything. Assets tied only to quantum expectations collapsed on one sentence, and assets whose revenue turns on a different cycle held up. The next question, which is where the quantum exposure at these companies turns into actual orders, is what this map is trying to answer.

Let me flag one exception up front. Not every pure play broke together. D-Wave is up 74 percent since CES and still sits 48 percent above its March 2025 high [3]. There was an acquisition this year that changed what the company is, and first-half bookings grew sharply. That bookings number has a few things worth picking apart, though. I get into it in the company card behind the paywall.

2. Why I am the one drawing this map

This is the sixth in the investment map series. I have drawn glass substrates, LEO satellites, submarine cable, defense sensors, and humanoids. This one is quantum.

This one is a different animal from the previous five. Those five were cycles where revenue was already turning. Glass substrate pilot lines were going in. Submarine cable had 13 billion dollars of orders on the table. Quantum is not like that. A good share of the companies on this map have no product and effectively no revenue.

Which is why nobody draws this map. It is hard.

I wonder if there is anyone other than PhotonCap who can cover this. Someone fluent not just in optics but in semiconductors, in quantum, and in metrology and packaging, all of it. How many people have designed a semiconductor, laid it out, actually built one, and then measured it. I mean someone who has done all of it. Quantum is the same story. On X, on Substack, across the various online communities, I have not seen anyone other than me covering quantum at anything above trader level.

There is a reason all five of those are needed. Take a quantum computer apart and you find a chip built on a semiconductor process, optics that get light into and out of that chip, equipment that cools it or holds it in vacuum, and metrology that reads out what is happening inside. And in the end it has to go through packaging to become a product. Someone who knows only one of those layers cannot see which of the other four is the bottleneck. And from an investment standpoint, the bottleneck is exactly where the money turns first.

For readers who want to invest in quantum but get stuck at what a qubit even is, I am starting from background. Sections 3 and 4 are for people seeing quantum for the first time, so if you already know this, skip to section 5.

3. Background one: qubits, errors, and logical qubits

The computers we use calculate with 0 or 1. Switch off is 0, switch on is 1. We call it a bit.

A qubit is a switch that can sit somewhere between on and off. It holds a probability of being 0 and a probability of being 1 at the same time, and settles into one of the two at the moment you read it. Physics calls that state superposition.

Every qubit you add doubles the state space you can represent. At 300 qubits that space exceeds the number of atoms in the universe. 2 to the 300th is about 2.04 times 10 to the 90th. There is a common misunderstanding here, though. You cannot read that whole space at once. The moment you measure, it collapses to a single answer. The real advantage comes from specific algorithms that use interference to raise the probability of the answer you want. Molecular bonding calculations and integer factorization are that kind of case.

The problem is that this superposition breaks very easily in practice.

A vibration, a temperature swing, a cosmic ray passing through, and the qubit loses its state. This is called decoherence. How you defend against it differs by platform. For superconducting and some spin qubits, cooling to millikelvin is the core of it. For trapped ions and neutral atoms, ultra-high vacuum and laser control are the core. Photonic runs at room temperature but lives or dies on optical loss and detection. Even with all of that, the best qubits today get it wrong somewhere between one time in a thousand and one time in ten thousand.

One in a thousand sounds fine? A single useful calculation involves billions of operations. The probability of never making a single error is the per-operation success probability of 999/1000 multiplied by itself as many times as there are operations. At a billion operations that is (999/1000) to the billionth power, which is essentially zero. At one error per thousand, the calculation turns to garbage long before an answer comes out.

This is where error correction enters.

The idea itself is simple. Bundle a set of unreliable qubits together and use them as one reliable qubit. The physically existing qubits are physical qubits, and the logical unit you build by bundling many of them is a logical qubit. They keep checking each other so the wrong one can be found and fixed.

The cost is large. It depends on the scheme and on qubit quality, but one logical qubit takes hundreds to thousands of physical qubits. So when you see an announcement that says a company built a 1,000 qubit machine, the first thing to check is whether that is physical or logical. It is about three orders of magnitude of difference.

Here is the part that matters to an investor. To increase logical qubits you have to multiply physical qubits, and when physical qubits go up, the equipment that cools or confines them, the wiring that connects them, the control channels that drive them, and the detectors that read them all go up together. Add one qubit and that much hardware really does get added alongside it. So the moment error correction genuinely starts working, money flows to the objects around the qubit.

There is a further condition: that checking has to happen in real time. You have to find and fix the error before the qubit loses its state, so the verdict has to land faster than the error correction cycle of that platform. That verdict is called decoding, and it is a classical computer’s job. How much time you get differs by platform. Superconducting is already in the regime where microseconds are the constraint, while trapped ion readout itself runs hundreds of microseconds to milliseconds, so the margin is different. Either way it means a fast enough classical computer has to sit next to the quantum computer.

From bits to qubits to logical qubits, and the cooling, wiring, control channels, detectors, and decoding load that multiply alongside one added logical qubit

4. Background two: five platform branches

The camps split on what you make the qubit out of. Based on what is investable in listed markets and what current government programs fund, this piece centers on five branches.

Superconducting. Run current through a circuit chilled to very low temperature to make a qubit. It is also the best known quantum platform. Google, IBM, and Rigetti are here. It reuses semiconductor processes so it is familiar to build, and gate speeds are fast. In exchange it has to be cooled to millikelvin, so a dilution refrigerator is mandatory, and every qubit needs wiring running into the fridge, so wiring saturates before qubit count does. What this camp can and cannot do is something I worked through using Google’s case in Google Quantum AI says it can break Bitcoin in 9 minutes. Should we actually worry?.

Trapped ion. Levitate ions in a vacuum chamber with electromagnetic fields and manipulate them with lasers. IonQ, the bellwether among the quantum pure plays, is here, and so is Quantinuum. Gate fidelity is high and there is no device-to-device variation, because you are using atoms that nature made. In exchange it is slow. And there is a limit on how many ions fit in one trap, so scaling means splitting into modules. You read an ion’s current state by counting the faint fluorescence it emits, and the photomultiplier tubes used for that come back in section 13.

Neutral atom. Pick up chargeless atoms one at a time with optical tweezers made of laser beams and arrange them. QuEra, Atom Computing, and Infleqtion are here, and Auratomic, which took Bezos money, is here too. The strength is that the array can be reconfigured freely. And this approach is structurally a pile of lasers. Holding the qubit, manipulating it, and reading it are all done with light. Infleqtion built revenue in quantum sensing before quantum computing, and I covered that structure in Infleqtion and Quantum Sensing: The Quantum Reality That Arrived Before Computing. It was private then and is now listed as INFQ.

Photonic. Use particles of light themselves as the qubit. Among listed companies there is Xanadu, and among private ones PsiQuantum. The strengths are that it runs at room temperature and can use silicon photonics processes directly. In exchange photons are easy to lose. Loss is the biggest wall for this camp. I went into this in detail on Xanadu in The 1% Loss Wall (Part 1): Where Xanadu ($XNDU) Really Stands, Through the Lens of Three Nature Papers.

Silicon spin. Use the spin direction of a single electron inside silicon as the qubit. Diraq, Quantum Motion, EeroQ, and Silicon Quantum Computing are here. The biggest strength is that it can use existing semiconductor fabs almost as they are. Qubit counts are still low. And in this camp, Diraq and Quantum Motion and EeroQ all use the same process at the same foundry. Which one comes out in section 8.

Five platforms compared, representative companies and the physical condition each camp has to defend against

Five branches, five different physics. So nobody knows who wins right now. If someone says it with confidence, here is something I can say with confidence. That someone does not know.

This is the core difficulty of quantum investing. If you cannot pick the winning modality, how do you pick a stock.

5. The farther you go, the more light wins

Half the answer is already in an earlier piece. My subscribers already know this one, in fact.

Whichever of the five branches you take, meaningfully increasing qubit count means going past the limit of one chip, one fridge, or one trap. Which means splitting into modules, and then reconnecting the modules you split.

What you connect them with is decided by distance. Modules close together inside a fridge can be linked with superconducting wiring and microwave, and there are demonstrations of cryogenic microwave links between separate fridges. But the moment distance grows and the path has to cross a room-temperature section, microwave gets sharply worse. At the scale of rack to rack and room to room, conversion into telecom-band light is the best-validated scaling path so far. More precisely than saying light is the only answer: as distance grows, the scalability of optical conversion wins.

Trapped ion links modules with photons. Neutral atom does the same. For the photonic camp light is the qubit to begin with, so there is nothing to argue. Even in superconducting systems, conversion from microwave to photons for long-distance transport is under active research.

I took this argument apart layer by layer in Superconducting or Trapped Ion, They All Buy the Same Light. Four layers, source and conversion and transport and routing and detection, down to who sits in each.

The conclusion there was to stop waiting for a modality winner and look at the component and foundry layer first. Here is what happened in the three months since.

In April 2026, IonQ announced it had linked two independent commercial trapped ion systems through photonic entanglement. By the company’s own account it is the first case of commercial quantum computers connected by photons [4]. And on July 31, 2026, IonQ closed its 1.8 billion dollar acquisition of SkyWater Technology [5][19]. A trapped ion quantum company bought an entire US semiconductor foundry. In January it also acquired Skyloom, a free-space optical communications company. And Lightsynq, which does quantum memory and photonic interconnect for linking quantum processors, closed earlier than either of those, in June 2025. More than 20 patents and applications covering quantum memory and interconnect came with it [37].

Why would a trapped ion company buy a foundry, an optical comms company, and a quantum memory and interconnect company. Its own qubits are ions floating in vacuum.

Because once you split into modules you have to reconnect them, reconnecting takes light, and someone has to build the chips that handle light. Hand that to someone else and someone else holds the bottleneck.

There is one more layer on top of this. Look at the 11 companies that made Stage 2 of DARPA QBI and you find Photonic Inc, which DARPA itself describes as “optically-linked silicon spin qubits” [6]. Even the silicon spin camp has optical linking baked into its architectural premise.

6. The government attached conditions

On May 21, 2026, the US Commerce Department announced it had signed letters of intent with nine quantum companies totaling 2.013 billion dollars [7]. One billion to IBM, 375 million to GlobalFoundries. Atom Computing, D-Wave, Infleqtion, PsiQuantum, and Quantinuum get 100 million each, Rigetti up to 100 million, and Diraq up to 38 million, the one name at a different order of magnitude.

The conditions matter more than the amounts. The announcement says this. “The Department will take a minority, non-controlling equity stake in each company as a condition of receiving funds, in order to increase returns for the American taxpayer.”

Give funding, take equity. That is an investment structure.

The equity-stake condition sentence in the US Commerce announcement

What Commerce announced is a letter of intent, and the equity is a condition of receiving funds. The announcement contains no confirmation that equity has been taken in all nine. Only one company has disclosed a percentage: GlobalFoundries, which put about 1 percent in its own release [21]. The other eight have to be confirmed at definitive agreements in the fourth quarter. Commerce is aiming to close them then.

Then, right before I filed this, the first three closed. On September 8, 2026, D-Wave and Rigetti and Quantinuum each signed a definitive agreement worth 100 million dollars [38][39][40]. Three deals, 300 million dollars, and Commerce takes a minority non-controlling equity stake in each as a condition of the funding. This is the first case of a letter of intent turning into actual money and an actual stake.

The stated uses differ. D-Wave said it will put the money toward a 100,000-qubit annealing system and a 10,000-qubit gate model system designed to carry 100 logical qubits through more than a million operations [38]. Rigetti committed to three things: compressing readout electronics into a miniaturized package, expanding cryogenic capacity through a new cryostat architecture, and building fabrication capability for high-connectivity chip architectures [39]. Neither is about the qubit itself. Both are about what surrounds the qubit. Section 3 said money flows to the objects around the qubit once error correction starts working. This time that move happened through government funding rather than acquisitions.

Quantinuum’s award names two more companies. GlobalFoundries is named as the fab that will make its next-generation ion traps and control electronics on 300mm wafers, and Monarch Quantum is named for the lasers and optical components [40]. The first name comes back behind the paywall. The second one is on the watchlist.

The other six are still pending. So the verification of this axis is only half done.

Even so, I think a government putting money down with equity as the condition is a hard floor. But the floor sits under financing, not under the share price. That is the answer to the question of why you should not exclude companies with no product and no revenue. The US has no option to give up quantum in its technology competition with China, so capital keeps coming in.

What that floor actually buys you has to be kept straight, though. A government stake raises financing availability and signals government technical validation. It does not guarantee continued listing, or solvency, or the absence of further dilution. Do not blur that distinction.

And this is not just Commerce. In June 2026 the Department of Energy launched Quantum Genesis with a stated goal of building and deploying a scientifically useful fault-tolerant quantum computer by 2028 [8]. DARPA QBI is running 11 companies in Stage 2 with Stage 3 validation to follow. The National Quantum Initiative Reauthorization Act (H.R. 8462) passed the House Science Committee in April 2026 and went to the floor [33]. It is not law yet.

The other side is symmetric. China’s 15th Five-Year Plan put quantum near the top of its future industries list. Origin Quantum raised close to 3 billion yuan in a July 2026 pre-IPO round led by China North Industries Group [18]. A state-owned defense conglomerate put money into a quantum computing company. I covered this shape in The Real Quantum Race: NVIDIA, NQI, and China’s State Capital.

Overlay the nine Commerce names with the 11 DARPA QBI names and something interesting falls out. Only four companies appear on both lists. Which four, and what that means for scoring, is behind the paywall.

7. Three frameworks

That is as far as the picture goes on public information alone.

The market looks at quantum through ordinary financial metrics. Revenue, growth, valuation. In an industry where revenue is effectively zero, those metrics distinguish nothing. You cannot line up five companies with zero revenue and compare P/E ratios.

So this cycle needs its own scorecard. Behind the paywall I apply three frameworks to all 23 companies at once.

The GVM score. Five axes, one to five points each. The axes are government anchor, modality neutrality, physical bottleneck, revenue substance, and convergence proximity. That last axis is this map’s signature, and it measures how tightly a company is attached to the two convergence axes, optical interconnect and real-time decoding. This axis is graded on evidence tier. Having your name in a press release, giving a supporting quote, and actually shipping parts or running a joint demonstration do not get the same score. No primary source, no points.

Phase weighting. Adding the five axes straight up fails to reflect the current phase. In a stretch where revenue does not mean much yet, the revenue substance axis has to weigh less and government anchor, modality neutrality, and convergence proximity have to weigh more. Apply the weights and the ranking changes.

The catalyst calendar. Trigger events scheduled in the next 12 months, placed on a time axis. Each row is marked as a fixed government date, a company-stated target, or my estimate.

And quantum purity. This is the part of this piece I put the most work into. The obvious objection is that Google and IBM and a foundry are not quantum companies, so scoring them on quantum axes alone cannot be right. So I measured how much of a quantum stock each name actually is, two different ways, and published it as its own column. There is plenty of writing that hand-waves at quantum exposure. I have yet to see anyone measure it as a number and attach it name by name. Overlay this column on the ranking table and investment character splits four ways, and it explains why the two hidden cards come out of the quadrant they come out of.

Quantum value chain positioning matrix, vertical axis government capital anchor strength, horizontal axis modality neutrality, company names withheld

Behind the paywall: all 23 companies identified, the foundry and component supply wiring diagram, market cap and returns by tier, the five-axis scorecard, the weighted ranking, group mapping, two hidden cards, the 12-month calendar, scenarios, and monitoring points. Five ownership changes in 2026 alone reshaped this map. One of them is an event where the listed exposure to the hardest physical bottleneck in this industry disappeared entirely, and another happened in late August and actually changed the rankings in this piece.

Read more

Somewhere on a Swiss airfield, two points 1.4 km apart were linked over a 226 GHz radio carrier. Net rate 153 Gb/s. The thing that caught that carrier at the receive end and put it back onto light was a plasmonic modulator. The paper is from ETH Zurich and Polariton, and the publication date is the interesting part: it ran four days before Marvell announced the acquisition. But a more important document came out two months later. The Polariton founders, now carrying Marvell business cards, wrote up the application range of this technology themselves. In that post, plasmonics sits on co-packaged optics inside the package and on coherent links between campuses, at the same time. The layers do not divide. They overlap. Which raises a question about the other optical platform this company bought four months earlier for more than three billion dollars. To say where I land before the paywall: I read this overlap as an internal contest that has not been settled yet rather than a failure of division, and I think it gets settled on materials and reliability rather than on bandwidth. The name of that material never appears in anything Marvell has published. It does appear in the August deck of the company that sells it, where Marvell is listed as a customer.

Contents

1. The paper that ran four days early

2. Two months later, the company drew its own map

3. What 1,400 meters proved and what it did not

4. So where does Celestial AI’s SiGe stand

5. Two blanks left in the material layer

6. One sentence from August 11

7. The ECOC 2026 checklist

8. Closing

1. The paper that ran four days early

A joint team from ETH Zurich and Polariton Technologies linked two points 1,400 m apart over a 226 GHz carrier [1]. Net 153.2 Gb/s, 184 Gb/s at the line rate. The paper claims this as a record on net-rate times distance. The signal did cross 1.4 km of outdoor path rather than a short bench span. Worth keeping in proportion though: the equipment sat in a container and the modulator was contacted with GSG probes, so this is an outdoor link demonstration and not a finished product.

The architecture is unusual. At the transmit end, two optical tones are mixed to generate the 226 GHz carrier and radiated. At the receive end, an antenna picks that carrier up and feeds it straight onto the modulator electrodes. The resulting electrical signal rides back onto light and goes into fiber. What gets skipped is the electronic downmixer in the wireless receive front end, with the sub-THz signal lifted directly into the optical domain instead. Baseband conversion and signal processing still happen downstream in the coherent receiver, and the RF amplifiers, the antennas and the optical amplifiers are all still there. The part doing the receive-side job is a plasmonic Mach-Zehnder modulator filled with an organic material.

Now the dates. The paper was received on December 26, 2024 and published on April 18, 2026 [1]. Four days after that, on April 22, Marvell announced the Polariton acquisition [2]. Two of the thirteen authors, Marcel Destraz and Wolfgang Heni in the fifth and sixth slots, carry Polariton Technologies affiliations.

What the sequence supports stops there. This result was public before the acquisition was announced. What Marvell actually reviewed during diligence is internal, and dates alone are not a basis for guessing. I covered the acquisition itself and the material question inside the slot in The Truth Behind Marvell-Polariton: Is LWLG the First Candidate, or Just a Backup Bet?, so this piece picks up what the company has said in the four months since.

2. Two months later, the company drew its own map

On June 17, a post explaining plasmonic technology went up on the Marvell blog [3]. Two authors: Claudia Hoessbacher and Wolfgang Heni, listed as Senior Director and Director of Optical Engineering at Marvell. The Polariton founders writing a technical document on Marvell letterhead.

The device description is specific. It explains compressing light below the diffraction limit at a metal-dielectric interface, and states that prototypes measure roughly 10 micrometers in length, 300x to 500x shorter than existing silicon photonics devices, and operate at 1 THz [3]. There is a line on manufacturing too: modified silicon processes with the metal dielectrics added toward the end of production.

Then come the applications. This is the part that matters.

“Plasmonic-based SiPho engines for co-packaged optics for scale-inside or scale-up applications could deliver the same or more bandwidth as conventional devices while minimizing space and power...”

“plasmonic-based SiPho engines for scale-across networks could be used to develop compact, ultra-fast and energy efficient ZR/ZR+ class modules...”

The same technology gets placed on co-packaged optics inside the package and on coherent links between campuses. The April acquisition release named only scale-across, DCI and the ZR family [2]. Two months on, the technical document widened the range upward. It also adds a new class of modules built around massively parallel plasmonic arrays as a possibility, and mentions modules at 3.2T and beyond [3].

The tenses tell you something else. Every sentence describing an application uses could. Able to, not doing. One sentence is in the past tense.

“High-speed SiPho devices capable of operating at 400G/lane containing plasmonic transponders were delivered to customers in 2026.“

400G per lane plasmonic transponders shipped to customers in 2026 [3]. No customer names, no volumes, no distinction between samples and production units. But it is the one completed event sitting among the conditionals.

The same post also sums up what is left.

“The technology is still in the early days of development for commercialization. In the next phase, the focus is on improving the reliability and performance of the devices as well as manufacturing methodologies to make the devices at scale.”

The company calls its own technology early stage for commercialization, and puts reliability first among the next-phase problems. That the company picked that word itself comes back later

3. What 1,400 meters proved and what it did not

With the map in hand, back to the paper. What the April result actually proved is narrower than it looks.

The application is different. The paper states its target as fronthaul and backhaul for 6G mobile networks [1]. Linking base stations over radio instead of fiber. Not datacenter interconnect, and there is no passage in the paper that frames DCI as the target.

The role the device plays is different too. Here the modulator is not loading data onto light at the transmit end. It is an up-mixer at the receive end, lifting an incoming radio carrier into the optical domain. Which changes the drive conditions completely. The paper puts the voltage amplitude at the modulator input at 0.3 V, with the sub-THz power reaching the modulator at minus 5.6 dBm [1]. With a Vpi of 12.3 V, that is small-signal operation at less than a fortieth of Vpi.

This distinction matters because taking Vpi 12.3 V and turning it into “the drive voltage is high, so the power budget is bad” gets it wrong. In this experiment the device was never swung anywhere near Vpi. Receive sensitivity was the thing that mattered. Try to use the same device as a transmit-side data modulator and Vpi comes back as a real burden. Change the role and the number means something else.

Insertion loss is 17.5 dB fiber to fiber [1]. Optical power drops to roughly a sixtieth. The paper reports this as a total and does not break it into components. Metal absorption in the plasmonic structure and the coupling loss of pushing light from a fiber into a slot tens of nanometers wide are both in there somewhere, but how much each contributes is not something this paper answers. In the lab you cover that with optical amplification. In a product, that amplifier shows up on the bill as cost, power and noise.

One comparison deserves care. This paper says thin-film lithium niobate gives low optical insertion loss but that its electro-optic bandwidth drops beyond 100 GHz [1]. That is the plasmonics camp talking, and there is work pointing the other way. A November 2025 paper in the same journal, on thin-film lithium niobate over a quartz substrate, reported 145 GHz at 3 dB and 310 GHz at 6 dB [4]. So 100 GHz is not a wall that cannot be crossed.

Which puts plasmonics somewhere other than winning a bandwidth race. Its claim is the same bandwidth in a far shorter device. The company blog saying 300x to 500x shorter is pointing at exactly that [3].

That is as far as public material takes us. But once the June blog widens the applications in both directions, the targets start to overlap with the other optical platform this company bought four months earlier for considerably more money.

4. So where does Celestial AI’s SiGe stand

Put Marvell’s optical acquisitions in order and there are two inside ten months.

Celestial AI was announced on December 2, 2025, structured as roughly $3.25B upfront with up to $2.25B in earnout [5], and closed on February 2, 2026 [6]. The object of the release headline is scale-up connectivity. Then Polariton on April 22, 2026 [2].

The modulation methods are genuinely different.

Celestial AI’s Photonic Fabric does not use micro-rings. The company-side paper writes down why: narrow optical bandwidth and too much temperature sensitivity to sit next to a hot chip. It uses germanium-silicon electro-absorption modulators instead [7]. Apply a voltage and the material changes how much light it swallows. Simple structure, small footprint, easy to pack densely inside a package. I followed how far that company has actually gotten through two of its papers in Marvell Bought Celestial AI. How Far Along Is Photonic Fabric?.

Polariton’s POH does not swallow light. It rotates phase. Light is confined in a narrow gap between metal walls and that gap is filled with an organic electro-optic material working through the Pockels effect.

So the two platforms run on different physics. Celestial AI has nothing to do with plasmonics. No organic slot, no Pockels effect.

What overlaps is the target application rather than the technology. Marvell bought Celestial AI for scale-up connectivity, per the release headline itself [5], and the June blog places plasmonics on scale-inside and scale-up CPO as well [3]. Two technologies built on entirely different physics have both become placement candidates for the same scale-up slot.

One caution here. Do not shrink the acquisition down to a modulator. Celestial AI came with an optical fabric architecture, packaging, system IP and a team. Reading this overlap as “one of them gets dropped” is premature, because the system layer and the device layer are separate problems.

Three things are still worth recording.

One. The two technologies get explained separately. The June plasmonics post never mentions Celestial AI or Photonic Fabric [3], and the Photonic Fabric material shown at FMS in August talks about package, server and rack scale [9]. Reach figures differ between company documents, so I will leave those numbers out here. Product blogs sticking to their own subject is ordinary, so the silence itself should not carry much weight. What remains is that the two ranges the company drew for itself meet at scale-up.

Two. The August 27 earnings release contains none of the words optics, photonics, plasmonic, Celestial AI, scale-up, scale-across or coherent [8]. The quarterly report filed the next day reads differently. Listing what drove data center revenue growth, it puts electro-optics first, and it describes the Celestial AI acquisition as a Photonic Fabric technology platform purpose-built for next-generation scale-up interconnect [10]. So the optical business is already inside the consolidated statements. The same document also says this.

“Revenue and earnings of Celestial since the acquisition date were not material”

Revenue and earnings since the acquisition were not at a level worth calling out. The precise reading is that it came into the consolidation but was not large enough to break out. Writing that it does not touch the income statement gets it wrong, and reading a revenue figure out of it gets it wrong too. Polariton and plasmonics, meanwhile, appear nowhere in that same quarterly report [10].

Three. The timing guidance has a different character on each side. For Celestial AI the company guided meaningful revenue contribution to the second half of FY2028. On the plasmonics side there is no such guidance, and instead there is a completed sentence about customer deliveries in 2026 [3]. Since that delivery is not described as samples or production units, and not dated relative to the acquisition, the two cannot be lined up to say which came first. What can be said is that one side has a shipment on record and the other has a revenue date.

Put those three together and a picture of layers divided by design does not emerge. It looks more like something not yet settled, and where it gets settled is not bandwidth.

Read more

NVIDIA’s revenue growth itself does not prove silicon photonics adoption.

The stronger argument is that continued AI growth increases cluster size, bandwidth requirements and rack power density, pushing electrical interconnects closer to their physical limits.

That creates increasing pressure to move toward optical I/O, CPO and eventually scale-across architectures.

AI is no longer just a semiconductor buildout.

It is becoming a memory, networking, optics, power and physical-infrastructure buildout.

Nineteen layers, up to three articles each. Picked for coverage, not chronology: one entry point, one structural piece, one current read wherever the archive allows.

All links resolve to published PhotonCap articles at

photoncap.net / https://photoncap-map.pages.dev/

1. Compute silicon

$NVDA, $AMD, $AVGO, $MRVL

• The GPU era ran on TSMC. The inference era runs on multiple foundries: NVIDIA Rubin NVL8 and 14 stocks (where the foundry split goes in the inference era)

• Same Split, Opposite Directions: Where NVIDIA and AMD Cut the Rack Decides Where Optics Gets Paid (rack partitioning decides the optics bill)

• Copper Wall, Age of Light — Dissecting Marvell’s FY2026 & the 1.6T Optics Chain (custom silicon meets the copper reach limit)

2. HBM / DRAM

$SKHY, $MU, Samsung Electronics

• Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains (the three architectural exits from the capacity wall)

• The Cut Was Not HBM: The SOCAMM Selloff and the Optical Memory Fabric (what the market misread in the memory selloff)

• Samsung and SK hynix Went Optical. What About Micron? (three memory makers, traced through patent priority dates)

3. Advanced packaging

$TSM, Amkor, ASE

• 7 Bonding Equipment Companies Behind HBM4 and CPO: AI’s Real Bottleneck Lives in Assembly (the assembly-side bottleneck, company by company)

• [OFC 2026] Part 3 of 5: Packaging: Glass Substrates to 3D Hybrid Bonding (the packaging roadmap as presented at OFC)

• TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM (two foundry strategies for the same problem)

4. Semiconductor equipment

ASML, Applied Materials, Lam Research, KLA, Tokyo Electron

• Compute Is the New Oil. So Who Builds the Drilling Rigs? (the equipment layer as the pick-and-shovel trade)

• The 6 Companies Behind Coherent and Lumentum: The Real Leading Edge of the AI Optical Cycle (who sells to the optics names before they ship)

• Veeco Q1 2026: Behind the MOCVD Thesis, Spector IBD Was the Real SiPh Lever (a single-name check on the equipment thesis)

5. Test / probe

$FORM

• The Three Pillars of SiPh Wafer Test: What AEHR, FORM, and KEYS Actually Do (who owns which part of photonic test)

• The 100-Second Bottleneck Behind NVIDIA CPO: 7 Companies That Own the 4-Stage Test Stack (test time as the CPO volume constraint)

• FormFactor’s July 29th (the most recent read on the probe card cycle)

6. AI networking

NVIDIA, Broadcom, Marvell, Arista Networks

• There Is No Such Thing as a ‘CPO Stock’: How the Market Misread SemiAnalysis (why the CPO trade does not map to one ticker)

• The Optical Axis Alone Won’t Show It: Redrawing CPO Across Three Budgets, Energy, Heat, and Reach (the networking problem redrawn as three budgets)

• Mapping the AI Landscape with Light: How OCS Transforms the Data Center Physical Layer (optical circuit switching at the physical layer)

7. Optical transceivers / optical engines

$COHR, $LITE, $AAOI, Innolight

• DSP, LPO, NPO, CPO: The Four Optical Architectures and the Light Source Beneath Them All (start here: the four architectures, plainly)

• Lumentum’s First $1B Quarter: FQ4 2026 Earnings Analysis (what a $1B optics quarter is actually made of)

• Five Days After Innolight’s $6.8B: The FCC Ban Draft and the AI Optical Module Supply Chain (the China module supply chain under export pressure)

8. InP / lasers

Lumentum, Coherent, $AXTI, Sumitomo Electric

• AXT and Lumentum’s Prepayment Deal: The InP Substrate LTA Chain (substrate scarcity written into a contract)

• Coherent FQ4 2026: InP Capacity, CPO/NPO Content, and CapEx Return (capacity additions read off the capex line)

• The AI Light Source War Is Not a Speed Race: InP, VCSEL, and μLED Are Buying Different Distances (three light sources, three reach budgets)

9. Silicon photonics / CPO

Marvell, Broadcom, Intel, TSMC, $TSEM, $GFS

• [PC101] Lecture 1: Why ‘Silicon Photonics’ Now? (The Next Fabless Revolution) (the entry point, no prior optics needed)

• [OFC 2026] Part 1 of 5: 300mm SiPh Foundry: Who Is Actually Ready? (foundry readiness, measured rather than claimed)

• The More Silicon Wins, the More InP Sells: Why UMC and Tower Both Expanded 300mm on the Same Day (the silicon and InP volumes move together)

10. Optical fiber / connectivity

$GLW, Fujikura, Furukawa Electric, Sumitomo Electric

• InP Makes the Light. Fiber Carries It: Same Cycle, Different Bottleneck (two bottlenecks in one cycle, priced differently)

• Coherent, Lumentum, Marvell, and Now Corning: NVIDIA’s 4 Photonics Bets and the Path of Light (where Corning entered the NVIDIA stack)

• [OFC 2026] Part 5 of 5: Hollow-Core Fiber and Next-Gen Transmission: Beyond the Loss Record (what comes after the loss record)

11. Networking systems / DCI

Arista Networks, Cisco, Nokia, $CIEN

• Down 40%, 40%, and 14% in Six Weeks: What the Ciena, Nokia, and Cisco Correction Priced In (what the correction actually priced)

• One Layer Below SemiAnalysis’s Meta Map: Scale-Across Is Coherent, Not CPO (scale-across belongs to coherent optics)

• [OFC 2026] Part 4 of 5: 400G/Lane and 1.6T Coherent: Two Fronts, One Power Wall (two roadmaps hitting the same power ceiling)

12. High-density power conversion

$VICR, Monolithic Power Systems

• P = I²R: The One-Line Equation Shaping AI Infrastructure and Vicor’s ($VICR) VPD (one equation behind the whole power layer)

• The Last 1.5mm of AI Power: Three Numbers from Vicor’s Q1 2026 Earnings Call (vertical power delivery, checked against results)

Two articles here, not three. The archive is thin on this layer.

13. Datacenter power infrastructure

Vertiv, Eaton

No dedicated article yet. Nearest coverage:

• The Optical Axis Alone Won’t Show It: Redrawing CPO Across Three Budgets, Energy, Heat, and Reach (800V HVDC and rack-level power distribution)

• The GPU Repricing Cycle and Q2 Hyperscaler Earnings: Which Hardware Layer the Capex Flows To (where the capex lands once it leaves the GPU line)

14. Cooling

Vertiv, Modine, Schneider Electric

No dedicated article yet. Nearest coverage:

• The Optical Axis Alone Won’t Show It: Redrawing CPO Across Three Budgets, Energy, Heat, and Reach (the thermal budget, treated as a first-class constraint)

15. Grid infrastructure

GE Vernova, Eaton, Quanta Services

No dedicated article yet. Nearest coverage:

• The Nuclear Cycle AI Data Centers Revived: 13 Listed Companies Beyond Constellation and Cameco (grid capacity as the binding constraint on siting)

16. Power generation

GE Vernova, Siemens Energy, Constellation Energy, Vistra, Cameco

• The Nuclear Cycle AI Data Centers Revived: 13 Listed Companies Beyond Constellation and Cameco (the full nuclear chain, not just the two obvious names)

• AIDC on Ground, Starlink in Space: Perovskite’s Dual Frontier (the same cell technology on two very different frontiers)

17. Datacenter construction

Quanta Services, EMCOR, Comfort Systems

Coverage gap. No PhotonCap article sits on this layer.

18. Datacenter / powered land

Equinix, Digital Realty, hyperscalers

• The Real Beneficiaries of Azure +40%, AWS +28%, GCP +63%: The Hardware Supply Chain Map Behind $580B in Cloud Capex (cloud capex traced down to hardware line items)

• The GPU Repricing Cycle and Q2 Hyperscaler Earnings: Which Hardware Layer the Capex Flows To (the most recent read on hyperscaler spending)

• SpaceX’s First Earnings Report: Revisiting the S-1, and the Hardware Value Chain Behind 10GW (10GW of orbital compute as an alternative to powered land)

19. Storage / memory disaggregation

Marvell, Micron, $SNDK, CXL ecosystem

• HBF (High Bandwidth Flash) and Optics: The Missing Link in AI Infrastructure (where flash and optics meet)

• Beside, Above, or Beyond: The AI Memory Capacity Race and Where Optics Fits (three placements for capacity, one of them optical)

• The More Anthropic Buys Micron HBM, the Faster Optical Memory Pooling Arrives (pooling as the consequence of buying more HBM)

Across the whole chain

• The Real Beneficiaries of Azure +40%, AWS +28%, GCP +63%: The Hardware Supply Chain Map Behind $580B in Cloud Capex

• Compute Is the New Oil. So Who Builds the Drilling Rigs?

• 1Y +124%, Four Months Behind by 10.4pp: Portfolio Quarterly Review

Cycles outside this map

• LEO and satellite optical links: [Investment Map] 26 Companies in the LEO Satellite Cycle: From Deployment to Service

• Quantum: Superconducting or Trapped Ion, They All Buy the Same Light: The Hidden Layer That Wires Quantum Computers Rack to Rack

• Defense and humanoid: [Investment Map] 20 Companies in the Humanoid Cycle: From Rare Earth Magnets to Vision Language Action

• Acquired in February, two papers in May. Authors who used celestial.ai addresses last year filed on the same subject this year from marvell.com. One word in the title changed, from Assembly Process to Demonstration.

• The two papers filled different halves. Last year measured the path the light would travel and left assembly for later. This year completed the assembly and pushed the optical measurement back. Only the diagonal is filled in.

• So one cell is left empty. An optical link measured on an assembled OMIB package. It appears in neither paper.

• Photonic Fabric is really three pieces. Assembly has been demonstrated, the link has been measured but on a different test vehicle, and system performance is all simulation.

• Meanwhile the product came out on August 4. No customer name and no sampling schedule are attached, and the 32 terabytes in the marketing copy is the number the paper lists as a simulation configuration.

I am very bullish on $MRVL and ‘Photonic Fabric’ idea and I still like this acquisition. What I think is that the place where the call gets settled is not the August 27 print but next year’s conferences.

Contents

1. The papers that changed affiliation

2. The layer this piece looks at

3. What beachfront means

4. What OMIB is

5. The mold and the dam

6. Hitting the same wall electrically

7. The halves they traded

8. Three pieces, three stages

9. The question with no answer yet

10. Absence is a signal too

11. But the product lineup is already out

12. What I asked in April

13. Closing

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1. The Papers That Changed Affiliation

Marvell closed the Celestial AI acquisition on February 2 of this year [1]. As announced at the time of the deal, the structure was $3.25B, with up to $2.25B more in performance based stock on top [2].

Four months later, at the end of May, two papers went up at ECTC 2026. One is about an optical bridge called OMIB [3], and the other is about the whole Photonic Fabric architecture [4].

The interesting part is the author list. There is a paper from ECTC 2025 with almost the same title [5], and the key people overlap. Of the six authors on last year’s paper, five appear across this year’s two papers: Aggarwal, Pothukuchi, Sahni, Winterbottom, and Lazovsky, who founded Celestial AI. Last year the email domain was celestial.ai. This year it is marvell.com.

One word in the title changed as well. Assembly Process became Demonstration. Last year’s paper did demonstrate part of the process and the optical path. It left the full assembly for later, and this year is the report that finished it.

Author blocks compared, 2025 paper versus 2026 papers

If you want to know what the acquisition price bought, this is more honest than the press release. These are sentences an engineer wrote for a conference, not sentences a company picked for promotion.

2. The Layer This Piece Looks At

I want to place this piece first.

There is already a very careful piece tracking Marvell at the earnings and valuation layer. ’s Marvell Part 3 is that piece, and it covers everything from the segment revenue bridge to the structure of the Google warrant. I read it closely.

On Photonic Fabric, that piece concludes as follows. It barely shows up in the income statement yet, only part of it is reflected in the valuation, and the confirmation point is when the first customer and the memory partner are disclosed.

That is an accurate read. On company guidance, the FY28 scale up optics outlook went from $150M to about double that, which is a rounding error next to the $16.5B revenue guide [6].

So this is a question about an option rather than about revenue. And the value of an option is set by how long it takes to be realized.

Damnang proposes learning that timing from disclosures. That works too, but there is also a way to read it one layer down first. The papers. This piece is about that lower layer.

So let me say up front that the clock for this piece is not the August 27 earnings release. This is not the kind of piece that turns out right or wrong on a number a few days from now. It measures where the gates are.

3. What Beachfront Means

Let me unpack one word before going into the technology.

The doors where data enters and leaves a chip are cut into the chip edge. But the length of a chip edge is fixed. Make the chip bigger and the area grows as the square, while the perimeter grows much more slowly than that.

Attaching optical modules beside the chip also ends up sharing that same edge. So if you want to keep raising bandwidth you need more doors, and there is nowhere to put them. This constraint is called beachfront. It means shoreline, and you can think of it as a question of how many ports you can build.

This is the wall the whole CPO camp is up against. I covered this subject in an earlier piece, The Optical Axis Alone Won’t Show It: Redrawing CPO Across Three Budgets, Energy, Heat, and Reach, splitting it into three budgets: energy, heat, and reach.

The answer OMIB proposes is this. Stop cutting the optical doors only into the edge, and put them directly under the place where the computing happens. The paper calls this a point of compute arrangement.

4. What OMIB Is

Start with the structure [3].

The photonic chip (PIC) is buried inside an organic interposer. The electronic chip (EIC) sits directly on top of it. The EIC and the XPU are joined by a silicon bridge.

The light does not exit sideways. It comes up out of a grating on the PIC surface, passes through a silicon or glass block that penetrates the mold, and meets a fiber bundle at the very top of the package.

OMIB cross section and the optical path (schematic, redrawn from the paper’s description)

The phrase organic interposer may bother you here. It means this is not a silicon interposer. You coat a carrier with dielectric, plate copper, and repeat to build up wiring layers, and that is called RDL. The wiring is coarser than silicon and it warps more easily, but it is cheap and you can make it large.

And what the paper emphasizes is that this assembly is compatible with a standard 2.5D flow. The original wording is “amenable to scaling at OSATs,” which means it can run on an OSAT line. From here on this is my inference, but if so, it means optical packaging volume does not have to be tied to a particular foundry’s advanced packaging queue. The paper does not claim that far. It also did not show yield or capacity.

5. The Mold and the Dam

Where was the hardest spot in the assembly? This part was the most fun for me.

Semiconductor packages are black because after the dies are attached you pour black epoxy resin over everything and cure it. This is called molding, and the material is called EMC. You mix in a lot of silica powder to control thermal expansion, and you grind the top flat to build structure. It is the skeleton of a 2.5D assembly, so you cannot skip it.

But EMC is black, the silica scatters light, and the refractive index does not match the design either. If EMC covers a grating, that optical port is dead. The paper did not measure how much coverage causes how much degradation. It only reports that mold was kept out of the grating area.

So the requirements collide head on. The whole thing has to be molded, and the small windows over the gratings must never be touched by EMC.

The method Marvell used is a dam. They build walls of polyimide around the grating window. It is the same as setting formwork around one hole before pouring concrete. The inside of the window is filled with index matched optical adhesive.

The dam holding back EMC, both walls of one window (schematic, redrawn from the paper’s description)

That cross section appears in a figure in the paper. The dark, grainy EMC stops dead at the white dam wall, and inside there is nothing but clean adhesive. They shot the left wall and the right wall of a single window separately to show that both held.

To add one thing about why this is hard, the first opponent the dam has to hold back is underfill, not EMC. Underfill is material you flow under the PIC on purpose to fill around the bumps, and it is not pushed by pressure. It works its way in by capillary action. The narrower the gap, the more strongly it is drawn in. Two liquids have to hold their own territory in the same gap.

And the dam sits under a die, so it is invisible during the process. If one spot leaks there is no obvious way to save that optical port, and the paper does not give repair options or a reject criterion.

6. Hitting the Same Wall Electrically

Optics is not the only way over the wall. The third paper Marvell put into the same conference is on the electrical side [7].

It is about custom HBM. They strip out the standard JEDEC PHY and put a dedicated interface on the logic base die of the HBM stack, and the numbers are fairly strong. Interposer channel length goes from 6.5 millimeters to 1.5 millimeters, and the area the HBM PHY was eating on the host chip shrinks by close to 60%.

Same 2µm design rules, same nine routing layers, and per lane speed becomes two and a half times. These figures are channel simulation results rather than measurements.

The EMIB-T paper Intel put into the same conference gives the opposite answer [8]. They keep the 6 millimeter channel and hold on with equalization. At 12 Gb/s the eye width lands right on the budget line without correction, and margin only appears once DFE is on. These are full channel simulation results as well.

It is interesting that two companies gave different answers to the same wall, but for the argument of this piece the point is this. Marvell is hitting this wall from the optical side and the electrical side at once. It is also a physical reason why content per socket keeps rising for custom silicon. If you can give a customer back area to spend on compute, they hand you more.

7. The Halves They Traded

Let me bring the story back to OMIB. That is what this year’s paper showed, so what has it not shown yet? Yes, as you have guessed, performance.

Put last year’s paper and this year’s paper side by side and they split like this.

Last year (2025) measured the optics. They polished the glass block with CMP down to roughly one nanometer surface roughness, and measured the peak wavelength and peak loss of gratings through that block on two wafers, comparing against a baseline [5]. But that was a test setup where a glass spacer sat on the gratings of a PIC test chip and a lensed fiber bundle received the light, and the paper itself wrote that the full assembly flow was left for future work.

This year (2026) completed that full assembly. They buried 24 dies in the interposer, molded, ground, flipped, placed the optical blocks, put the XPU on, and attached it to the substrate. The joint cross sections are the evidence [3]. But an important qualifier is attached here. This test vehicle was designed as a passive daisy chain structure. The XPU, the EIC, and the PIC are all test chips, and the optical side is a passive loopback. It was built to see whether the wiring connects and whether the assembly works, not as a working product. And the optical measurement section defers to a citation of last year’s paper and ends like this. Measurement on assembled units will come after reliability testing.

To put it together. Last year’s paper measured the path the light would travel and did not carry assembly to the end. This year’s paper carried assembly to the end and did not measure the light. What one paper filled, the other left empty, and what the other filled, the first left empty.

Only the diagonal is filled in. A paper with both cells filled, meaning an optical link measured on an assembled OMIB package, appears in neither of these two.

What each paper filled and what it left empty

8. Three Pieces, Three Stages

Calling Photonic Fabric one thing makes this distinction disappear. It is really three pieces, and each is at a different stage. This is a different split from the three product families the paper defines. I split it this way to organize the evidence.

Assembly. Proven end to end. There are cross section images, and the claim of compatibility with a standard back end flow is backed by the process sequence. But the subject was a passive test vehicle, and reliability results are not in the paper [3].

Link. Measured. Four TX and RX pairs on a 5 nm EIC, 56 Gb/s per channel, 2.8 pJ/bit energy efficiency on the electronic side, eye opening over 0.2 UI at the target error rate [4]. Good numbers. But these came off a different object. The paper says power was fed to the PIC by wire bond. This is a separate link demonstrator rather than the OMIB organic interposer structure.

System performance. All simulation. A 32 terabyte shared memory appliance cutting communication power by 60 to 90%, and throughput going up 5.6 times on a one trillion parameter model, belong here [4]. The simulator itself is reported as validated at about 8% mean error against real GPU hardware, but the appliance itself was not built and measured.

So the pieces each work, and they have not yet come together as one body. This is what it means for an option to have internal structure.

Assembly, link, and system performance, and the evidence grade of each

9. The Question With No Answer Yet

One of the things the paper does not cover keeps nagging at me.

The caption on the optical adhesive carries the word permanent. It means this is not a temporary protective material but a medium that stays in the final product for good, with the beam passing through it for its whole life. That makes yellowing, refractive index shift with temperature, moisture uptake, and delamination all lifetime items.

And EMC sits right next to that adhesive. The two materials have different coefficients of thermal expansion and shrink by different amounts as they cure. That boundary happens to be the edge of the optical aperture. When temperature cycles, stress concentrates exactly there.

The paper has no data on this item. Let me note that what follows is a failure hypothesis I constructed rather than something the paper proved. Even so, I think this is the real gate for this approach. Whether the assembly works has been answered, and the next question is how many years it holds.

10. Absence Is a Signal Too

An objection can be raised here. Not in the paper does not mean not at the company. That is fair. A paper is the floor of public evidence, not the ceiling of development progress.

But I read this case a little differently.

ECTC is the best conference in packaging. Marvell submitted papers there, and not one but several. So if there had been a result to show, they would have shown it there. Data showing an optical link running on an assembled package is a far stronger result than showing the assembly process works. From the position of choosing which papers to submit, there is no obvious reason to hold that result back and publish only the process story.

The timing has to be taken into account, of course. ECTC 2026 was held at the end of May, but paper submission comes several months before that. So what these papers reflect is the state as of early this year. Now, in August, they may have gone further.

But there is no public material telling us what moved how much in between. And what the paper wrote down is a sequence rather than a date. Reliability testing first, then measuring the assembled unit. Months can pass and that sequence still stands.

11. But the Product Lineup Is Already Out

Reading this far, something may feel off. The paper says the measurement has not happened, so what is the company doing?

On August 4 at FMS 2026, Marvell announced the Photonic Fabric product lineup [9]. Memory modules, a NIC, and a chiplet. The content is that it builds a shared memory tier across multiple racks, offloads up to 32 terabytes of warm KV cache, and raises token throughput by two to three times within existing data center footprint and power limits.

Two and a half months after the paper wrote “measurement after reliability testing.”

What is missing from the announcement matters too. There is no customer name. No sampling schedule and no production schedule either.

And how to read the number 32 terabytes is a question. The same number appears in the ECTC paper, where it is the capacity of the proposed appliance architecture and at the same time a configuration value fed into the system simulation. The table lists 32 terabytes of memory and 26.8 TB/s of network [4]. A result actually measured on 32 terabytes of hardware is not in the paper.

To be fair I should write one item the other way. The phrase two to three times on tokens is actually lower than the paper’s simulation. The paper put out up to 2.3 times at 405 billion parameters and up to 5.6 times at one trillion parameters. The same figure also carries 1.3 times and 1.4 times conditions. Marketing called it more conservatively than the paper did.

To put it together. The announcement and the paper move on different clocks. There is nothing strange about a company signaling its roadmap first, and papers are slow by nature. But you will get the timing wrong if you look at only one of them. The product announcement tells you where the company intends to go, and the paper tells you how far it has come.

12. What I Asked in April

In April of this year I wrote a piece called NVIDIA’s $2B Marvell Bet and Celestial AI’s “25x Bandwidth” Claim: What’s the Denominator?. I asked what the denominator was behind the 25x figure Celestial AI was putting forward, and at the time I could not find the answer.

The two OMIB papers carry that 25x and 10x wording in the introduction as is [3][5]. They still do not state the denominator.

What did arrive in the body are measured values. 56 Gb/s, 2.8 pJ/bit, 0.09 square millimeters of silicon per TX and RX pair. Converted to an HBM sized chiplet that comes to about 7.2 Tb/s, and the paper compares this against HBM3 at 6.5 Tb/s [4].

So April’s question got a partial answer. The denominator behind the marketing phrase is still unknown, but what the company has in mind as the comparison target came out in the papers. I think that was a reasonably well aimed question.

One more thing. The modulator choice I covered in the April piece and in The Truth Behind Marvell-Polariton: Is LWLG the First Candidate, or Just a Backup Bet? also got an answer this time. Photonic Fabric does not use micro rings. The paper even writes the reason, which is that their optical bandwidth is narrow and they are too temperature sensitive to sit next to a high power chip. It uses germanium silicon electro absorption modulators instead [4].

This is a choice that splits camps, so it is a subject that needs its own piece.

13. Closing

To compress the current state into one sentence, the pieces have each been proven and the data on the combined object has not come out yet. And the product has already been announced.

So I am holding my judgment. I lean positive, but the grounds to settle it have not been made public.

What is comfortable is that what to watch from here is clear. Two disclosures of different character are racing, and which one arrives first gives the answer.

One is on the paper side. The 2026 paper wrote the sequence down itself. Reliability testing first, then measuring the optics on assembled units. So the venues are set. OFC in the first half of 2027, and ECTC 2027 at the end of May or early June. Watch whether assembled unit optical data and reliability results show up there.

The other is on the business side. When the customer name and the sampling schedule that were missing from the August 4 announcement get filled in. The October 6 investor day is the nearest venue.

Before that there is the August 27 earnings release. What gets decided there is not the quarterly number but what comes up in the Q&A. Whether the customer name or the sampling schedule missing from the August 4 announcement gets mentioned, and whether the FY28 scale up optics outlook gets called up again. Calling it up would be a signal that the option value is being pulled forward, and leaving it alone means things are running in the sequence the papers drew. The revenue line itself will not decide it. Next to the $16.5B guide it is a rounding error [6].

The order of the two disclosures carries information. If reliability and optical data come first and customers attach after, it is rolling in the order I read. If instead customers and a production schedule are disclosed first, my understanding of the order is wrong, and it means the company is moving faster than what it publishes in papers. That is not bad news. It does mean the material I based this on is not keeping up with actual progress, and at that point I would have to move the basis of the judgment outside the papers.

And if next year’s conferences bring measurements on yet another test structure instead of assembled unit data, or if the reliability items start mentioning the adhesive and EMC boundary, the realization timing has to be pushed back. That stress concentrates at that boundary is my estimate rather than a value the paper measured, so until data comes out it is right to leave it as an open question.

To add one thing, what this piece covered is technical readiness, not this quarter’s numbers. However the earnings land a few days from now, the positions of the gates above do not change. Think of them as two clocks running on different layers.

Why buying and selling CPO at the ticker level does not work well is something I covered in an earlier piece, There Is No Such Thing as a ‘CPO Stock’: How the Market Misread SemiAnalysis, and this case is similar. It is closer to watching whether one gate opens than to buying one company.

Acknowledgment

One of the starting points for this piece is Damnang’s Marvell Part 3: What Has Been Proven, and What Is Still Open. That piece placed Photonic Fabric accurately at the earnings and valuation layer as “an option that is barely in the P&L yet,” and set the confirmation point at customer disclosure. This piece looks at the same question from the layer below, using different material. The two are not competing. They sit at different layers.

References

[1] Marvell Technology, “Marvell Completes Acquisition of Celestial AI,” 2026-02-02. https://www.marvell.com/company/newsroom/marvell-completes-acquisition-of-celestial-ai.html

[2] Marvell Technology, “Marvell to Acquire Celestial AI, Accelerating Scale-up Connectivity for Next-Generation Data Centers,” 2025-12-02. (Consideration structure as announced at the time of the deal) https://investor.marvell.com/news-events/press-releases/detail/1000/marvell-to-acquire-celestial-ai-accelerating-scale-up-connectivity-for-next-generation-data-centers

[3] D. Raorane, A. Aggarwal, S. Pothukuchi, S. Chadda, “Optical Multi-Chip Interconnect Bridge (OMIB) Interposer Demonstration to Enable High-density Photonic Interconnects for High-Performance Computing Applications,” 2026 IEEE 76th Electronic Components and Technology Conference (ECTC), pp. 1898-1902. DOI: 10.1109/ECTC51846.2026.00311

[4] D. Oh, A. Aggarwal, S. Pothukuchi, J. Pesic, S. Sahni, P. Mishra, G. Balamurugan, T. Diep, P. Winterbottom, D. Lazovsky, “Photonic Fabric Interconnect for a Scale-up Network Solution in Accelerated Computing,” 2026 IEEE 76th ECTC, pp. 862-867. DOI: 10.1109/ECTC51846.2026.00146

[5] A. Aggarwal, S. Pothukuchi, A. Rathi, S. Sahni, P. Winterbottom, D. Lazovsky, “Optical Multi-Chip Interconnect Bridge (OMIB) Interposer Assembly Process to Enable High-Density Photonic Interconnects for High-Performance Computing Applications,” 2025 IEEE 75th ECTC, pp. 331-336. DOI: 10.1109/ECTC51687.2025.00062

[6] Damnang, “Marvell Part 3: What Has Been Proven, and What Is Still Open,” 2026-08-21. (Secondary source. Company guidance figures are cited as compiled in that piece)

Damnang’s Substack

Marvell Part 3: What Has Been Proven, and What Is Still Open

I have been analyzing Marvell closely since the beginning of this year and have shared a positive view across several articles…

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2 months ago · 25 likes · Damnang

[7] J. F. Dillon, T. Zheng, A. Vohra, K. Blacklow, E. Tremble, W. Sauter, S. Allman, “Marvell custom HBM routing and signal integrity analysis,” 2026 IEEE 76th ECTC, pp. 298-303. DOI: 10.1109/ECTC51846.2026.00055

[8] Y. Mekonnen, J. Xie, Z. Qian, X. Konstantinou, Y. Si, Y. Cui, K. Aygün, K. Radhakrishnan, “Enabling 12+Gb/s HBM4E with EMIB-T Advanced Packaging Technology,” 2026 IEEE 76th ECTC, pp. 455-460. DOI: 10.1109/ECTC51846.2026.00078

[9] Marvell Technology, “Marvell Advances AI Memory Infrastructure Portfolio to Accelerate Agentic AI Inference,” 2026-08-04. https://investor.marvell.com/news-events/press-releases/detail/1030/marvell-advances-ai-memory-infrastructure-portfolio-to-accelerate-agentic-ai-inference

This article is an independent technical analysis published by PhotonCap, based on an engineering perspective. All content is derived from publicly available information and is intended solely for educational and informational purposes. In other words, nothing in this material should be construed as a recommendation to buy, sell, or hold any specific securities. Please note this carefully.

The author may hold positions in the securities mentioned herein and reserves the right to trade such securities at any time without prior notice. Readers should conduct their own thorough review and research before making any investment decisions.

SK hynix announced on August 20 that its co-packaged optics roadmap paper had run in Nature Electronics[1]. CPO puts the optical chip that moves signals as light inside the same package as the compute chip.

I opened the paper right away and followed the twelve authors’ backgrounds and where the company had put money before that, which I wrote up in One Interconnect Company, All Three Memory Makers on the Cap Table: Fifteen Months of SK hynix’s CPO Track. Something stayed with me after I filed that one.

The paper is a review. It reads less like a company product roadmap and more like a summary of where the field has gotten to, with tables of energy and bandwidth per integration method and a list of problems still open.

The newsroom post had a different flavor. There the company put its own name behind a bigger claim, that memory would be bound into a single pool to get past the memory wall[1]. The paper surveys, the announcement points.

So I got curious. Is this only SK hynix’s direction?

Samsung is already out in public. Its foundry declared entry into silicon photonics in March and published a schedule. That leaves Micron, which has no roadmap, no paper, and no press release on optics from the last ten years.

So I went to the patents. And one filing came back with a February 2023 priority date that is still under examination. The title is optical signaling for stacked memory device architectures. Memory dies stacked up, with light running between them.

Something the company has never said out loud is sitting at the patent office right now.

Three memory makers on two axes, public disclosure above and patent priority below

TL;DR

• SK hynix’s Nature paper reads mostly as a review, but the newsroom post put the company’s name behind memory pooling as the way past the bandwidth bottleneck

• Samsung already stands in the same place as a foundry product. It laid down a PDK at OFC and published a turnkey schedule

• Micron has no public optical roadmap from the last ten years, so I went through patents and job postings instead

• Binding memory with light is an idea more than twenty years old. Micron filed in 2002 and Samsung in 2008

• Narrowed to the silicon photonics package family, Micron has a 2023 priority filing that is still under examination

• Lined up by priority date, filings recur across several generations from 2002 to 2023. What clearly stopped was the public announcements

Contents

1. Why This Comes Up Now

2. Samsung Is Already Standing There

3. No Announcements, So Open the Patent File

4. The Role Micron Is Hiring For

5. Ten Billion Dollars and August 27

6. Four Layers That Are Easy to Miss

7. Where This Goes

8. References

1. Why This Comes Up Now

Memory bandwidth has come up several times in this series. The routes to more bandwidth and the paths for moving capacity outside the package are laid out in Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains.

The short version. Putting memory right beside the GPU made it fast and also made capacity hard to grow. Stacking more layers is getting expensive in heat and yield. So the remaining path is to move memory outside the package and connect it through a channel.

Right now that channel is copper. CXL is the one. It works, though round trip latency runs somewhere around double what local memory costs. The number moves with the device, the number of switch hops, and the memory media, so pinning it to one figure is hard. Either way it is slower, which means software has to keep deciding what sits near and what sits far.

The targets in the SK hynix paper are worth noticing here. More than 100Tb/s per node, under 1 picojoule per bit, and chip to chip latency below 10 nanoseconds[1][2]. That last number is aggressive. It is a target for the chip to chip optical link though, not for end to end memory access, since controller, protocol, queuing, and coherence costs stack on top of it. Even so, a link at that level would make tier management much lighter than it is today.

The paper says as much itself. It leaves an optical memory interface that keeps coherence while lowering latency on the open problems list[1]. The picture got drawn and the method got assigned as homework.

Here is where it splits, why a memory company would look at this directly. Turning the channel optical used to belong to the networking companies and the foundries, since CPO started by putting an optical engine beside a switch. But when the thing at the far end of the channel becomes memory, the situation changes. The optical chip has to come inside the memory package, and the company that designs, assembles, and tests that package is the memory company. It stops being somebody else’s problem.

2. Samsung Is Already Standing There

I mapped Samsung once in July. In TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM I laid out who holds which of the chips that go on the interposer, and Samsung was the only one holding memory, logic, and the optical chip together.

It has moved further since. At OFC 2026 on March 17 the foundry division formally declared entry into silicon photonics and said its PDK was complete[3]. A PDK is the toolkit customers design with. Its arrival means customers have a base to start design and tapeout from. It does not mean production yield and process qualification are finished. The kit reportedly carries more than forty device models with a verification flow, on a 300mm process[3].

Why the PDK matters is that optical devices diverge from simulation more than electrical ones do. A modulator that behaves in the schematic often comes back strange on the actual wafer. The PDK is the foundry’s attempt to shrink that gap before handing it over, and without one you cannot build a repeatable standard design flow. That is also why Samsung bothered to mention that free carrier absorption and self heating went into the models[3].

The schedule went public too. Thermocompression bonded optical engines in 2027, turnkey CPO service in 2029[4].

That is the visible picture. Samsung tells you because Samsung has to sell. A foundry only has a business when customers knock, and that means saying where you are, repeatedly.

So what about Micron?

I searched by silicon photonics, optical I/O, CPO, and conference presentations, and nothing recent comes back. Recent OFC and ECTC programs carry no Micron optical talk, and no optical interconnect startup investment shows up either. As far as I can find, the company has issued no press release on the subject at all.

When there are no announcements you look somewhere else. I opened the patent file and the job postings.

What follows is that record. Line the three companies up by priority date and the order comes out different from the market’s impression, and on Micron’s side one filing is still waiting on examination. The qualifications on a currently open job posting carry a word the company has never put in a press release. The dates on the Boise lab announcement and the SK hynix Indiana groundbreaking sitting a week apart, and Micron’s continued absence from the US government optical programs, both come up later.

The last part is the value chain. Everybody already says packaging benefits when memory gets pooled, so instead I pulled four layers that rarely get named. They are process steps you pass through whichever way the architecture goes.

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Abstract

On August 20 SK hynix used its own newsroom to announce that a co-packaged optics roadmap paper had been published in Nature Electronics. CPO means putting the optical transceiver inside the same package as the processor. The company’s post leans on two things: Seunghoon Hong, its AI Infra team lead, served as a corresponding author, and the work goes beyond HBM innovation to a system-level blueprint. I read the post, opened the 15-page paper next to it, and then walked through the public record of all twelve authors one by one. That is when I found out this track did not start with the paper. The company post has not one line about the step before it. I treat this announcement as a positioning signal rather than a CPO product schedule. What holds up is that the technology choice was already marked in money, with all three memory makers leaving that mark side by side.

Contents

1. The company published this itself

2. The wall the paper draws

3. The table the post left out

4. Twelve authors and where they come from (Paywall)

5. Where the track actually starts

6. The same cap table

7. The distance still left

8. How far I take this

1. The company published this itself

Here is the headline that went up on the SK hynix newsroom dated August 20.

“SK hynix’s technology roadmap for co-packaged optics features in ‘Nature Electronics,’ as AI competition shifts from chips to systems” [1]

SK hynix newsroom post

The paper is “Co-packaged optics for high-performance computing and artificial intelligence,” the journal is Nature Electronics, and the format is a Review article. The front page is stamped submitted November 18, 2025 and accepted July 8, 2026 [2].

The company names two corresponding authors. Seunghoon Hong, team lead at AI Infra, SK hynix, and Professor Kyusang Lee of the Department of Electrical and Computer Engineering at the University of Virginia [1]. The collaborating institutions are listed as UIUC, NTU, MIT and Yonsei.

Look at the paper itself and there are twelve authors. Nature titles attach a contact e-mail only to corresponding authors, and the bottom of the first page carries six e-mail lines, one of them on the sk.com domain [2]. So the company took those six and introduced two of them as the lead corresponding authors.

AI Infra is an organization SK hynix set up in January 2024. By the company’s own newsroom description it groups global sales and marketing, the HBM business, and Memory System Research, which does pathfinding beyond HBM [3].

The newsroom even added a footnote defining what a corresponding author is. Principal authors who oversee and take responsibility for the whole process, from planning through submission, peer review response, and post-publication questions [1]. The fact that the company bothered to footnote that phrase tells you where the weight of this announcement sits.

The company did not leave this in an internal research news column either. The official X account pushed the same content on the afternoon of August 19 local time, with the hashtags #SKhynix #CPO #AIInfrastructure [4]. The Korean newsroom date reads August 20 because that is Korea time, so the global channel started the day before.

The X wording carries one more edit, though.

“Published in Nature Electronics, a new paper from @SKhynix and University of Virginia researchers explores how CPO can overcome the ‘bandwidth wall’ through optical connectivity.” [4]

SK hynix and University of Virginia researchers is all that survives in that sentence. The Korean newsroom lists UIUC, NTU, MIT and Yonsei too [1], and they are gone from the global channel. By author count the MIT and UIUC share is not small.

A memory company taking part in an optical interconnect review is not new by itself. A company turning that into an external message is a different thing. And the one partner name left standing in that message is the University of Virginia, which comes back later.

2. The wall the paper draws

The term the paper’s own text uses for this bottleneck is bandwidth wall. Memory wall shows up once, in a reference title. Here are the scaling numbers behind it. Every two years compute throughput went up 3x, DRAM bandwidth 1.6x, and interconnect bandwidth 1.4x, while on the same axis AI model training compute jumped 8.8x [2].

Newsroom scaling graphic, 3x compute against 1.4x interconnect

The company post quotes only two of those, the 3x and the 1.4x [1]. The paper has DRAM bandwidth at 1.6x sitting in the same figure. A memory company issuing a release with the DRAM curve dropped out is a curious edit.

So compute moves 3x while the pipe that carries the data moves 1.4x. The gap bites hardest at the boundary between memory and logic. Here is the paper’s own sentence.

“the gains are confined to intra-package communication; once data goes beyond the memory-logic boundary, electrical interconnects ... incur resistive and capacitive losses that greatly increase with frequency and distance” [2]

What HBM gained holds only inside the package, and the moment data crosses the memory-logic boundary the losses in copper take over again. You can stack DRAM dies with TSVs, which are vias drilled vertically through the chip to make the connections, and pull multiple terabits per second out of them, and that gain still will not follow the data out of the package.

This series has been over that diagnosis several times. Once in Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains, which laid out three ways of raising memory bandwidth, and once on the optical memory fabric side in The More Anthropic Buys Micron HBM, the Faster Optical Memory Pooling Arrives. The diagnosis has been around for a while. A memory company putting its name on that chart and then issuing a release about it is the part that changed.

3. The table the post left out

The company post summarizes the paper’s technical targets in three lines. More than 100 Tb/s of bandwidth per node, energy below 1 pJ per bit, chip-to-chip latency under 10 ns [1]. The same numbers are in the paper [2].

There is one more table in the paper that the post did not carry over. Table 2, titled representative industrial CPO and optical I/O platforms in the original. It mixes shipped products, demonstrated prototypes and some projected figures, so not everything in it is in production. Broadcom Bailly and Davisson, NVIDIA Quantum-X Photonics, Intel OCI, Ayar Labs TeraPHY, Lightmatter Passage M1000, Celestial AI Photonic Fabric, Ranovus, Avicena, Microsoft MOSAIC. Ten rows, nine companies [2].

paper Table 2, industrial CPO and optical I/O platform list

Switch companies, accelerator companies and optical I/O startups are all in there, and the memory makers are the ones missing from the list.

This gap is something I already mapped once in July. In TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM I mapped who holds each of the three chips that go on the interposer, meaning HBM, logic and the PIC. Samsung was the only one holding all three, and SK hynix held memory while sending the logic base die outside. That piece sorted SK hynix’s routes into CPO into three. Packaging verticalization in Indiana and Cheongju, the memory-system CPO review at the 2025 Future Forum, and the CPO ecosystem on the public-project side.

I went back to the original on that Future Forum item. It was held September 11, 2025 at the Icheon campus, and the third agenda was a joint presentation by KAIST Professor Kyoungsik Yu and SK hynix Vice President Hoyoung Son [5]. The title reads like this.

“A future connected by light: CPO (Co-Packaged Optics) technology evolution and its ripple effects on the memory industry” (author translation from the Korean original) [5]

SK hynix Future Forum 2025 newsroom

Son’s title is worth a second look. He is head of Advanced PKG Development [5], which is a package development organization rather than strategy or planning. And the content, per the newsroom, was sharing a review of silicon photonics technology types, working through how to apply it inside and around the memory system, and setting out what preparation is needed across Architecture, Design, Device and Package [5].

That July piece also left a monitoring item at the end. Watch whether the memory-system CPO reviewed at the Future Forum turns into an actual R&D program or a partner disclosure. This announcement is the first answer to that item. An academic partner is disclosed, and a company employee put his name on it as a corresponding author. It is still not confirmation that an R&D program is running, so I am leaving that item half filled rather than closing it.

A later figure in the same paper puts a memory pool and an XPU pool facing each other across a single photonic interposer [2]. The company post ran that same concept diagram [1]. The side with no name in the table takes up half of the future architecture.

The word CXL never appears in this paper. I checked by searching the full text. UCIe shows up five times in the same document, NVLink and PCIe twice each. The die-to-die standards and the network standards are covered, and the current standard for memory pooling is the one that is missing.

The paper talks about pooling memory without touching the electrical pooling standard the industry actually uses today. The right reading is that the review’s scope sits on the optical architecture side. A missing word and a deliberate exclusion are different claims, and I will not push it that far. Readers should account for the gap either way.

That is as far as you get from putting the paper and the release side by side. Checking the public record of all twelve authors one at a time makes it fairly clear where this collaboration came from. And there was a step before it that appears nowhere in the company post. A trace of money that moved before the paper did.

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Contents

1. An Update After Four Months

2. The One Year Return, and the Path Underneath It

3. How to Read These Numbers

4. July: Zero Sells

5. The Homework April Left Behind

6. The 15 That Disappeared: Judgment and Raising Cash

7. The 8 That Came In

8. What the Two Snapshots Do Not Show

9. What Remains: Why I Still Hold Them Four Months Later

10. The SMH Comparison: Same Money, Same Dates

11. The Cost of Concentration

12. Conclusion

1. An Update After Four Months

On April 11 I wrote 1Y +122%: What Happens When a SiPh Engineer Only Buys What He’s Touched and disclosed all 40 or so tickers across three accounts. At the end of that piece I wrote “next update: Q3.” This is the piece that keeps that promise.

On a trailing one year basis ending August 17, the combined return across the three accounts is +124.25%. That moved about 2pp from the +122.29% I wrote in April.

Looking at this number alone, it seems like nothing happened for four months. But open the account records and it is the opposite. So instead of walking through allocations ticker by ticker like April, this piece tries to focus on what actually happened during those four months.

So the material for this piece is the records underneath rather than the account screens. I downloaded a full year of deposits and withdrawals plus 1,600 executions, and matched them one by one against the sentences I wrote in April. Whether a ticker I said I would “keep watching” four months ago is still in the account, what orders I actually placed when the drawdown came, and whether anything came in and went out unnoticed between the two disclosures.

For reference, on August 11 and 12 I moved a bit over 20% of the accounts out to a CMA account. That was money for another purpose and it had nothing to do with a market judgment. So part of the balance curve coming down from the June high is the portion I took out. The return numbers in this piece are calculated with all of those flows stripped out.

2. The One Year Return, and the Path Underneath It

Cut month by month, it looks like this. I calculated it with the Modified Dietz method, reflecting each month’s starting balance and the money that came in and out on a daily basis, and I put SMH next to it for the same period. The window is August 1, 2025 to August 17, 2026, which is twelve and a half months.

In April, 58% got added in a single month. And in July, 30% went away. In August it is in the middle of taking back 20%. Out of thirteen months, five trailed SMH.

Monthly return bars and relative performance versus SMH. Cumulative curve normalized to a starting value of 100, no dollar axis

The reason the trailing one year number looked like it stood still is that these months offset each other. But this only means two trailing one year readings with different as of dates printed 2pp apart, and the actual performance over the four months has to be looked at separately. That number comes below.

April is unusually large in this table, and the April piece was published on April 11. So about halfway through that month, holding an account that had already risen a lot, I wrote “1Y +122%.” The timing of the disclosure was good, and luck played a big part in it. If you look at what happened to the same account four months later in this piece, that difference should become a little clearer.

The return summary section of the April 11 article

Over the same period, the semiconductor ETF SMH returned +109.87%. From an adjusted close of 283 dollars on August 1, 2025 to 594 dollars on August 17. It was a window where holding SMH alone and sitting still would have doubled your money. My chained return of +132.84% is a number sitting on top of that.

Two numbers show up here and it may be confusing, but the basis is different. +124.25% is the trailing one year money weighted return the broker calculates, and +132.84% is a twelve and a half month time weighted approximation from chaining the table above. The calculation method is different and the measurement window is different, so the gap between the two cannot be explained by cash flow effects alone. When comparing against SMH in this piece, I use the latter basis throughout.

If I match the basis to the monthly table and cut only from the end of April to August 17, the picture gets clearer. Part one was published on April 11, but this starts from month end, so it is a window that begins about three weeks later. Over this window SMH is +17.24% while my portfolio is +6.80%. I fell behind by 10.4pp.

The biggest cause, as you already know, is July. If you look at the difference column in the table, 12.93pp opened up in that single month, which is larger than the other three months combined. SMH also fell more than 17% in July, but my account fell more than 30%. It is a concentrated, high beta small cap optics portfolio, so it took a much bigger hit than the index, and even after taking back 20% in August it still has not closed that gap.

The conclusion of the April piece was that “concentrating in what you know beats diversifying into what you do not know,” and three months after writing that sentence, the other side of concentration arrived. If you gather names that move in the same direction, they rise together and they fall together. The fact that it fell nearly twice as much as the index probably includes some individual bad news, but the composition itself, a group of names tied to the same direction, worked in the direction of amplifying the drawdown.

The April piece ended with the sentence that it was 42pp ahead of SMH. What happened to that edge four months later is in section 10.

3. How to Read These Numbers

Before laying out more numbers, it seems right to state the calculation method first. The same account can produce different returns.

The +124.25% that shows on the broker screen is a money weighted return. When and how much you put in gets reflected in the result. Money put in during September compounded for a year while money put in during July only compounded for a month, and this method puts that difference into the calculation.

The value from chaining the table above is +132.84%. Because it links monthly Modified Dietz returns, it is an approximation of a strict time weighted return, and months where a large amount came in mid month, like July, carry some error. This one reduces the influence of deposit and withdrawal timing, but what is left is not only stock selection. Position sizing, trade timing, and how much cash was held are all mixed in.

There is a reason the two diverged by more than 8pp. I kept adding money from March through July, and it was with an account grown that large that I took a -30% month. The weight of a bad month taken with large capital late outweighed the good months made with small capital early. That is why the dollar based result comes out lower than the stock picking result.

And, in order to compare my results, I tried comparing against the semiconductor ETF SMH. This was something a subscriber requested, and I thought it was a good reference so I prepared it again this time. If the same money went into SMH on the actual deposit dates and amounts, how much would it be now. That calculation is section 10.

There is one more thing I want to write down here. There are plenty of pieces that disclose returns, but most of them cut out the good stretch and show that. I did the same in April. I announced a one year return about halfway through a month where 58% had been added in a single month. Pieces like that leave the reader with very little after reading. Either envy or suspicion, one of the two.

What I want to do this time is the opposite of that. Account records do not allow you to keep only the bragging. What orders I placed in July, what I sold two weeks after writing that I was convinced in April, how many tickers I bought impulsively while writing a piece and how those ended, all of it is there with the dates. If you lay that out as it is, good judgment and things gained by luck and plain mistakes become distinguishable from one another.

I think what is useful from the reader’s side is that distinction. This is not to say you should buy my tickers. It is about seeing, through one person’s record, how long something written down as conviction actually holds. And then when you look at your own account, you will probably see something similar.

So from here on are the things that only come out when you open more than 1,000 executions. What I did in July, why the 15 tickers that were there in April disappeared, what trades do not show up in either of the two snapshots, and why I still hold the 35 that remain.

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On August 14, the June 30 positions of two funds were disclosed on the same day. Leopold Aschenbrenner’s Situational Awareness had pulled off almost all of the roughly $8.4B in puts it carried through the end of March in a single quarter, and Gavin Baker’s Atreides went the other way and doubled its QQQ put contracts [1][2][3][4]. A month later, on July 29, semiconductor and optics names all bottomed together, and while the index fell a bit over 10% that day, SanDisk was down 55% and Astera Labs 48%. This piece is part two of the August 1 article, and it goes back to the SEC originals to see where each of them cut the AI infrastructure value chain and how each reads it. On Baker’s side I looked at one more thing. The speaker list for the TomorrowX Summit he co-hosts in Austin in November overlaps substantially with the top names in this 13F [5]. To put my lead up front, I think the part of Baker’s 13F actually worth reading is less the list of top holdings and more the stretch he did not touch.

Contents

1. Two 13F Filings Opened on August 14

2. Aschenbrenner’s June 30

3. Baker’s June 30

4. What the +1.73% Is

5. Splitting Interconnect Into Layers

6. Why Only Lumentum Was Dropped

7. What the Two Filings Share, and Cerebras at 10.7%

8. Baker’s TomorrowX Event

1. Two 13F Filings Opened on August 14

August 14 was the 13F deadline. The rule is that you file your holdings as of June 30 within 45 days, so every quarter the 13Fs of US institutions all open at once on this day. Berkshire came out that day, so did Druckenmiller, but the ones I looked at with interest were two.

The reasons being

1. AI and AI infrastructure and related tech stocks make up most of my brokerage

2. Memory, optics, semis, related names, a wide range of stocks that both 13Fs hold

I see these two as the two masters of the tech long. Leopold Aschenbrenner in particular is someone I think looks carefully at bottlenecks and invests by seeing straight through to those points, and he did it successfully. (Leaving the leverage aside, of course.) Everyone knows this, but he left OpenAI and set up Situational Awareness in 2024, and reportedly grew assets under management from around $200M at launch to tens of billions in two years.

Gavin Baker ran the Fidelity OTC fund for a long time before starting Atreides, and he keeps up an active presence in online communities, so these days he has exchanges with real depth with all sorts of tech industry experts, tech stock supporters and analysts. There’s an event that’s been getting a lot of promotion lately, where he co-hosts something called the TomorrowX Summit under his own name. It’s held in Austin in November, and looking at the speaker list, I get the sense there aren’t many tech longs who can pull semiconductor company CEOs together like that [5].

Part one on these two was written on August 1. In Compute Short, Memory Long: Aschenbrenner’s Unwind, Gavin Baker’s Hold I opened the March 31 filings and covered why compute sells expensive and memory sells cheap. When I wrote that piece, I was looking at why Leopold built his positions the way he did, and by coincidence Baker’s portfolio was also sitting on tech stocks in a fairly similar way, so I found it interesting to analyze.

This piece is the picture from the next quarter.

But the situation of these two has now split completely. Leopold is reported to have had his public equity book forcibly liquidated in July, and Baker is still riding high (there is no public data on the fund returns themselves, so this is just my impression). That said, people say Leopold blew up, but his year to date return is still above the average person’s. I thought his attempt was a bold and admirable challenge, but looking at it now with hindsight it was a reckless challenge, and it feels like he got brutally trampled.

SEC EDGAR filing index for both funds, 2026-08-14

All the numbers were pulled directly from the info table originals posted at the SEC. The aggregator sites were still showing end of March data as the latest as of yesterday, so to check I downloaded and parsed the original XML, and that work took half a day. Thankfully the verification came out clean. The implied unit price you get by dividing reported value by share count matched the June 30 close for every name [6]. Micron $1,154.29, Ciena $490.56, QQQ $736.40. Which means the parsing was not wrong.

Let me draw one distinction up front. What a 13F shows is a slice cut out of the book. Only US listed equity longs and options appear, and shorts, non US assets, cash and private stakes all drop out. So when I talk about weights below they are all on a reported value basis, and the weight in the actual book could be smaller than this. That gap becomes the raw material of this piece in sections 4 and 7.

2. Aschenbrenner’s June 30

The thing that stood out most in the March 31 filing was the puts. Around $2.0B on the SMH semiconductor ETF, around $1.5B on NVIDIA, roughly $1B each on Oracle, Broadcom and AMD. Add Micron, TSMC, ASML, Intel and Corning on top of that and it comes to around $8.4B on an underlying market value basis [4]. It was a double structure, long memory and power with puts draped across semiconductors broadly.

Open the June 30 filing and this is gone.

The only put left is Infosys, and that one is around $5M [3]. Everything else disappeared, and Micron and TSMC flipped completely from puts to common. Nothing is public about what judgment happened in between. Someone who held 1.72M Micron puts in March holds 4.83M Micron common shares in June.

So what came in to fill that space. The answer is two memory names. SanDisk at around $5.7B and Micron at around $5.6B, together 55.6% of reported value. After that comes Bloom Energy at around $1.9B, TSMC at around $1.3B, Nebius at around $1.2B, then CoreWeave, Core Scientific, STMicro, Applied Digital, RIOT, IREN [3]. It’s a lineup that runs through power and neoclouds and bitcoin miners, and the big picture is the inputs to compute. It’s a layout that says buy electricity and memory and compute comes out.

Situational Awareness Q1 2026 13F info table, put rows highlighted

The biggest empty seat in this filing is optics. There isn’t a single name. No coherent equipment, no transceivers, no optical DSP, not even connectors. It carries the same AI infrastructure fund label but the connection layer is completely empty. This comes back later as the biggest difference when we compare with Baker.

This picture is right before the liquidation. On June 30 he had all the hedges pulled off and 55% loaded into two names, and you all know what happened in July. It’s said to have been a forced liquidation.

3. Baker’s June 30

Atreides’ total reported value jumped from $5.0B at the end of March to $14.3B at the end of June [1][2]. The number of holdings actually went down, from 54 to 49. So what came in to make it grow like that. Yes, as you’ve probably guessed, SpaceX.

27.33M shares, around $4.6B, 32.6% of reported value. It’s the single largest position, and it is more than five times the gap to Micron, the second largest on a common stock basis [1].

I’ve held SpaceX myself since the IPO, and I’ve kept writing in support of the earnings analysis and the compute rental business. What I laid out in SpaceX’s First Earnings Report: Revisiting the S-1, and the Hardware Value Chain Behind 10GW is that story, and my view is that this company is closer to an AI company than a space company. I see it as an AI company wearing a space costume. I don’t think the reason Baker loaded 32% into it is the orbital launch business either.

The second largest is the QQQ put. Around $2.3B on 3.2M shares, 16.4% of reported value. He more than doubled it on a contract basis from 1.4M shares at the end of March [1][2].

This part is interesting, because in the second quarter QQQ went from $577 to $736, up a full 27.6% [6]. While the index was melting up like that, he doubled his index puts. One of them pulled every hedge off and the other doubled his hedge, and both of them are AI infrastructure bulls.

The rest of the top names are Micron at around $800M, Cerebras common at around $600M plus around $100M in calls, Meta calls at around $600M plus around $200M in common, Astera Labs at around $500M, Ciena at around $300M, Credo at around $300M, Coherent at around $200M [1].

Layer by layer comparison of the July 29 trough drawdown. QQQ and NVDA against the AI hardware names

The lows clustered on July 29. Almost every name bottomed together that day, but the size of the drawdown was completely different by layer. Measured against the June 30 close, while QQQ fell 10.1% and NVIDIA 5.0%, SanDisk fell 55.3%, Astera Labs 48.3%, Bloom Energy 45.9%, and Coherent 43.7% [6].

At the time I was studying the representative coherent optics players in order to look into Scale-Across names, and the piece I wrote is exactly Down 40%, 40%, and 14% in Six Weeks from last July, and the moment of publication was the middle of this correction, with the actual bottom coming ten days after that piece.

Up to here is the range anyone can see by skimming public material. The top holdings list and the drawdown table go up on the aggregator sites within a day or two.

There is a separate reason I downloaded the original XML and calculated every share count delta. The share count increases for Ciena and Coherent and Nokia and Semtech were the same down to the second decimal place. What that means, and once you know it, is what separates judgment from plain drift in this 13F.

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On August 13, one slide was shared at the Sandisk Investor Day. The content was that Meta joined the HBF consortium following Google, and ten days earlier, the first HBF standard specification of up to 512GB and up to 3.0TB/s was published through OCP. Ironically, in the same week, Samsung brought out the zHBM concept that stacks memory vertically on top of the accelerator. Then the question, naturally, has a place it heads to. What about Micron? Micron is officially not putting its name in this game. However, the phrase “stacking NAND” points to a completely different structure at each company, and if you do not distinguish them, you end up drawing the beneficiary map wrong. So this article is going to try dividing the question into two. How to stack, and where to place the capacity made that way, relative to the processor. My interpretation is on the side of “whichever direction the stacking competition gets settled, wouldn’t a considerable part of the growth go not to the memory companies but to the optical interconnect layer?” The evidence has been prepared with job posting originals and physics arithmetic.

Contents

1. August 13, One Slide at Investor Day

2. Three Meanings of the Word “Stacking”

3. Micron’s Public Stance and the Careers Site

4. The Structure Micron’s Job Postings Draw

5. Beside, Above, Beyond: Three Paths and Three Walls

6. Microseconds and Meters: The Physical Reason NAND Is Allowed to Move Away

7. The Optics Map: Which Layer It Falls On

8. Stacking Equipment and Optical Links: The Related Names

9. Conclusion

1. August 13, One Slide at Investor Day

Let me start with the $SNDK story. Sandisk stock rose 6% on August 12 alone and reached the mid $1,300 range (as of the 2026-08-12 close) [3], and on the 13th, the day of the Investor Day, it rose another 14% and closed at $1,528 (as of the 2026-08-13 close) [1][4]. In terms of the gain since the start of the year, it is over five times, remarkably [3][4]. It is true that the NAND shortage cycle made these numbers, but the place where my eyes stayed long that day was one slide on the technology roadmap side, rather than the financial targets page.

The “HBF Consortium Milestones” slide from the Sandisk 2026 Investor Day. The August 2026 milestone shows “Consortium Expands: Meta”

The timeline of the slide reads like this. In August 2025, Sandisk and SK hynix agreed on HBF (High Bandwidth Flash) standardization, and in February 2026, a consortium was formed under OCP (Open Compute Project, the body where hyperscalers turn hardware specifications into open standards). The ones that joined at that time were Google and Tenstorrent [5][7]. Until then there did not seem to be much reaction, but just recently, in August 2026, when the first standard spec was published and the Meta logo went up in the consortium expansion box [1], the mood really became one of wondering whether HBF is going to become the standard. In other words, to organize it again, two hyperscalers that design their own AI chips, namely Google and Meta, are now in a state of having put their names on a NAND-based memory standard.

What HBF is, I covered in January in HBF (High Bandwidth Flash) and Optics: The Missing Link in AI Infrastructure, and at that time, it was the article with the best response among the ones I had posted on my Substack.

To say it again in one line, it is a plan to transplant HBM’s stacking formula onto NAND and create a middle tier that is “much wider than SSD and much bigger than HBM.” At that time it was at the level of conference presentations and concepts. Now, a concrete spec document with 512GB capacity, three bandwidth grades from 0.4 to 3.0TB/s, and a UCIe interface is up on OCP [5][6], and it has come to the stage where the company states a schedule: samples in the second half of this year, inference devices in early 2027 [5]. At the Investor Day they went one step further, and it is said that the tape-out of the first HBF die (the state of having finished the design and handed it to the foundry) is complete and customer samples are next year [4].

So the material the market encountered this week is two things. On the surface there are the NAND price cycle, the contract backlog that has grown to the $90 billion range [4], and the Investor Day’s long-term financial targets [2], and below that there is the structural change that “NAND comes out of the storage box and climbs onto the memory bus.” This article intends to deal with the latter. And the question is one.

Everyone says they are stacking NAND, but are they stacking the same thing?

2. Three Meanings of the Word “Stacking”

Before the main body, it would be good to divide the axes first. The news of “stacking NAND” actually has two different questions mixed in it. One is the process question of how to stack and build, and the other is the placement question of where to put the capacity block made that way, relative to the processor. This section is the former question, and the beside, above, and beyond in the title are the latter question.

Starting from the process side, the word “stacking” in the industry right now points to three different processes. The three differ in purpose, and the direction the money flows is also different.

Concept diagram of the three kinds of stacking. Layer stacking, wafer bonding, and package-level TSV stacking compared in one view

The first is layer stacking. It stacks NAND cells vertically inside the die, and the “hundreds-of-layers NAND” we see in the news is all this story. It is said that Samsung V10 has passed 400 layers, Kioxia and Sandisk’s BiCS10 is 332 layers, and Micron G9 is 276 layers [8][9][10]. The purpose is simple. Extracting more bits from the same wafer and lowering the cost. It is the economics of storage devices, and it is a game that every NAND company is playing without exception.

The second is wafer bonding. It is a method of making the NAND cell array wafer and the peripheral circuit (CMOS) wafer separately, then attaching them whole to complete one die. Kioxia and Sandisk went first under the name CBA [9], and Samsung also announced that it is joining this column from V10 under the name BV-NAND [8]. Up to here, it is still a story about “how to make one die well.” Density increases and I/O gets faster, but the completed die still sits behind the SSD controller, behind the serial passage called PCIe.

The third is HBF. It is a structure that threads multiple completed NAND dies with TSV (Through-Silicon Via, vertical wiring that penetrates the die) like HBM, puts them on a logic base die, and connects them directly with a wide parallel bus from the seat beside the processor [5][6]. The first spec is 8-high or 16-high stacking, up to 512GB per stack, and bandwidth from 0.4 to 3.0TB/s depending on grade [6]. If the previous two stackings are the game of “cheaper,” this one is the game of “wider.” Since it is a matter of changing the interface itself from the storage kind (serial PCIe) to the memory kind (parallel wide bus), I see only this third one as a stacking of a different nature.

But here, one placement question cuts in ahead of time. It is the option of moving the stacking position onto the processor entirely. The zHBM that Samsung unveiled at FMS 2026 is a concept that stacks not NAND flash memory but HBM vertically right on top of the accelerator, and by the company’s claims, it speaks of 8 times the performance of HBM5 and more than 10 times the density [8]. Let me clearly attach the maturity label that it is still at the concept model stage. It is not a product, not a confirmed roadmap, and the figures are vendor claims. Still, the direction itself needs a serious look, because as covered in July in TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM, Samsung keeps digging into the real estate problem inside the package from different angles. And that makes sense, because Samsung is a vertically integrated semiconductor company that can optimize the processor, memory, HBM, photonics, and process together, so it may well be making various attempts. I also think this point is their strength.

Concept diagram of the zHBM structure from the Samsung newsroom. A cross-section with the HBM stack placed on top of the processor

That was long, so to organize it a little: the layer-count competition and the bonding transition are the stacking of cost, HBF is the stacking of bandwidth, and zHBM is the stacking of position. The reason investors must not lump the three into one word is, as we will see later, that the physical limits each one hits are different.

3. Micron’s Public Stance and the Careers Site

Now it is Micron’s turn. In fact, Micron is not a member of the HBF consortium [7]. The award it received at FMS 2026 is also said to have been on the 245TB-class data center SSD side [11]. In early August at the Technology Leadership Forum, the remarks of CBO Sumit Sadana also stop at the level of “when DRAM is insufficient, KV cache spills over to the NAND side” [12].

To summarize, the Micron on public stages concentrates its firepower on HBM4 and sells NAND as fast SSDs. It stacks, but in the first and second meanings of stacking, that is, the stacking of cost.

Then is Micron really keeping its hands off the third game?

Actually, in January this year I made an inquiry to an acquaintance, and since it seemed difficult to talk in a public place about the answer I heard privately, only now have I found public materials and come to make it public.

If you open the careers site, the answer comes out somewhat different.

This part took some time to confirm. Nothing came up in news searches, so I went through Micron’s recruiting system directly, keyword by keyword, and the word “HBF” is 0 cases in all postings. Instead, two postings from the NAND design organization (NVEG) in Tokyo were caught. One was posted in April, one in July, a hiring that has continued for four months [13][14], and since postings can come down, I saved the originals as captures.

Please look at the highlighted phrase in the capture below. What structure of NAND this posting is hiring for, and why I crossed over to the optics-side conclusion after seeing it, is the content of the paid section.

Original Micron Tokyo NVEG job posting.

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TL;DR

• Coherent’s FQ4 2026 revenue, released after the close on August 12, came in at $2.05B. That lands almost exactly at the top of the guidance range given three months ago, and non-GAAP EPS of $1.74 went past the top end ($1.72) [1].

• Guidance for the next quarter is $2.2B to $2.4B in revenue, roughly +12% QoQ at the midpoint. And yet the stock, up nearly 9% in the session right before the release on the 12th, gave the entire rally back with an 8% drop on the 13th, the first trading day after [1][3].

• My read is this. The real news from this call is between the lines of the transcript. Where the bottleneck has moved, what six-inch does to margins, and what the company is worried about instead of demand. The direction is in the body.

Contents

1. August 12: A Top-of-the-Guide Quarter and a Post-Earnings Reversal

2. The constraint has already moved upstream from the module

3. Six-inch InP is a capacity story and a margin story at the same time

4. (Paywall) What kind of debate is CPO versus NPO for Coherent?

5. How far up the network does OCS go?

6. What does Coherent sell into scale-across?

7. What the FY27 order book says

8. Where to check the return on CapEx

9. Checking the Last Call: The Six Items I Flagged in May

10. Conclusion: These Dates Will Do the Judging

1. August 12: A Top-of-the-Guide Quarter and a Post-Earnings Reversal

Results touched the top of the guide, EPS went through it, and the stock still fell 8% the next day. That is this Coherent quarter in one line.

Coherent reported FQ4 2026 results (quarter ended June 30) after the close on August 12. Revenue came in at $2.05B, up 34% year over year on a reported basis [1]. The guidance range the company had given three months earlier was $1.91B to $2.05B, so this lands almost exactly at the top end. I go through the item-by-item guidance comparison in section 9.

Profitability came along with it. Non-GAAP gross margin of 40.2%, EPS of $1.74 up 74% year over year, and for the full year, FY2026 revenue of $7.12B at +22.5% [1]. The segment mix tells you where this growth comes from: Datacenter & Communications did $1.6B-plus in Q4, up close to 60% year over year and now around 80% of the total, while Industrial slipped backward to the $430M level [1]. The AI data center side is carrying the whole company.

Quarterly revenue and non-GAAP gross margin from FQ4 2025 through FQ1 2027 guidance

Guidance is strong too. FQ1 2027 revenue of $2.2B to $2.4B, non-GAAP gross margin of 39.5-41.5%, EPS of $1.85-2.05 [1]. At the midpoint, that is another quarter of 12%-plus sequential growth.

And yet the stock moved in an interesting way. Shares rose nearly 9% to around $356 in the regular session on August 12, right before the release, then closed the first post-earnings session on the 13th down 8% at $327.23, giving the entire rally back (as of the 2026-08-13 close) [3]. After touching the top of the guide and calling for another quarter of double-digit growth, why did it fall? There are about three candidates. Expectations already loaded into a stock trading at close to four times its 52-week low [3], the cash burden of an aggressive buildout, or simply a bar that had formed above the guidance. The second candidate is one you can check directly against the CapEx and cash-flow numbers later in this piece.

The public takeaway was just one thing, the InP bottleneck. But reading the transcript from start to finish, this call carries a few bigger changes underneath. And the gap between the headline numbers and the post-earnings reaction is filled by exactly these lines between the lines. So here they are.

2. The constraint has already moved upstream from the module

On this call, Coherent stated flatly that transceiver assembly and test capacity are not constraints today. The biggest constraint is InP production [2].

Honestly, this is where I paused. It was hard to agree with, and it made me think twice. I have long viewed test as the single biggest bottleneck in optical devices. I have published quite a few articles on test (The 100-Second Bottleneck Behind NVIDIA CPO: 7 Companies That Own the 4-Stage Test Stack, The Three Pillars of SiPh Wafer Test: What AEHR, FORM, and KEYS Actually Do), and I hold quite a few of the related stocks too. Why PIC test is harder than EIC test, and how large its share is at the package level, is something I also touched on in [PC101] Lecture 4: The Last Millimeter: Who Builds It. CPO Packaging Value Chain and Next-Gen Applications (Part 2). So why did Coherent point at InP, and specifically production, instead of test?

I still think InP is critical and close to irreplaceable. But here is how I read that line: the InP bottleneck right now is simply that severe.

The numbers back it up. June-quarter InP laser output grew about 80% year over year, and the company’s own 800G and 1.6T transceiver demand is effectively absorbing all of it [2]. Everything made goes straight into its own modules, which is why the optical supply chain’s scarcity is getting harder to understand by counting transceiver units. You have to look past module assembly to EMLs, CW lasers, and below them, InP wafer and substrate capacity.

And this is not just Coherent’s story. On the Lumentum call the day before Coherent’s report, the same direction showed up: EMLs are still shipping behind demand, and on high-power lasers supply has fallen even further behind as demand accelerated [7]. Two reports one day apart are pointing at the same upstream layer. I put the Lumentum side together separately in Lumentum’s First $1B Quarter: FQ4 2026 Earnings Analysis.

I went deeper into that upstream bottleneck recently in AXT and Lumentum’s Prepayment Deal: The InP Substrate LTA Chain. Expanding fab capacity and securing InP substrate you can actually use are two different problems.

3. Six-inch InP is a capacity story and a margin story at the same time

Coherent’s move to six-inch is not only about a bigger wafer adding production capacity. The CFO’s phrasing was clear.

“Four times, but it’s at half the cost.” [2]

Spelled out, a six-inch wafer yields about four times as many devices as three-inch, at around half the cost per device [2]. The more interesting part is that yields for EMLs, CW lasers, and photodiodes are all already higher on six-inch than on three-inch [2]. Normally, when you move to a larger wafer diameter you lose yield first before you gain anything, and this line says they are already past that stage. So as InP capacity grows, transceiver shipments can rise while the cost of the most critical component inside them comes down at the same time.

I had already flagged this as a core monitoring point in the previous-quarter piece, $20B+ New SAM on Top of +27% Pro Forma Revenue: The Quarter Coherent Crossed from Transceiver Player to Platform, and this call made the six-inch margin thesis considerably sharper than back then. In other words, in this cycle, volume growth and margin expansion do not necessarily have to move in opposite directions.

That is the supply side of the transcript. What stayed with me longer, though, were the demand-side lines: the company’s answer to the market’s CPO-delay worry, and the CEO’s description of the FY27 order book. If the next day’s 8% drop missed something, it is probably here.

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TL;DR

• Lumentum’s FQ4 2026 revenue, announced after the market close on August 11, came in at $1,006.3M. Quarterly revenue crossed $1B for the first time, up 24.5% from the prior quarter and a striking 109.3% from a year ago [1].

• The same quarter shows a GAAP net loss of $7.2B, but the source of this loss sits outside operations. The cause is a one-time, non-cash accounting loss of $7.8B from converting convertible notes into stock, and I walk through it in the body [1][2].

• Non-GAAP operating margin of 36.6%. While revenue doubled, operating margin rose 2,160bps year over year. Next quarter’s guidance calls for $1.25B revenue at the midpoint and a 39.5-40.5% operating margin, arriving at the target model the company laid out at OFC more than a quarter early [1][2].

• Here is my lead. I think the real news this quarter is less the revenue figure and more the five signals mentioned alongside transceivers. What those signals are, and why they change the very size of the market Lumentum can address, is laid out in the body.

Contents

1. August 11, the First $1B Quarter

2. What the $7.2B Loss Really Is

3. Where These Orders Come From

4. Segment Breakdown: Both Sides Ran Together

5. Five Signals: Optics Moving Into the Rack

6. Guidance Check: What a 40% Operating Margin Implies

7. Prior-Call Review: The AXT LTA and the Supply Gap

8. Conclusion: These Dates Will Decide

1. August 11, the First $1B Quarter

Lumentum reported FQ4 2026 results (quarter ended June 27) after the market close on August 11. Revenue was $1,006.3M, up 24.5% QoQ and up 109.3% YoY [1]. A year ago this company’s quarterly revenue was $480.7M, so revenue has more than doubled in four seasons.

You may wonder whether this growth is a one-off jump. Borrowing the language from the call, this is the eighth consecutive quarter of revenue growth, and counting only quarters with more than 20% sequential growth, it is the third in a row [2]. The comparison base keeps getting bigger, and the growth rate is holding anyway. Back in May I covered the $808M quarter in The 8 Companies Behind Lumentum’s $808M Quarter: Why Beta Splits by Orders of Magnitude Across the InP Cycle, and just one quarter later another $200M has been stacked on top. As a growth rate, that is an enormous number.

The profitability numbers actually catch my eye more. Non-GAAP gross margin came in at 50.4%, crossing 50% for the first time. The company reportedly planned to cross this threshold at around $2B in quarterly revenue, and it got there first at half that revenue [2]. Operating margin was 36.6%, an expansion of 440bps QoQ and 2,160bps YoY [1]. While revenue doubled, operating expenses stayed pinned at 13.7% of revenue [2], so this is a zone where added revenue drops almost straight through to profit. When operating leverage works the way the textbook says, this is the picture you get.

The stock reaction was, unexpectedly, on the calm side. The August 11 regular session closed at $820.59 (+0.87%), and after the release the stock was up around 2% after hours (as of 2026-08-11, including after hours) [3]. Market cap is $63.8B, and the 52-week range runs from $111.20 to $1,085.68, so even after printing these results the stock still sits more than 20% below its 52-week high [3]. As it happens, the optics-only ETF LYTE listed five days before these results [4], and LAZR had already arrived in late June [5]. I suppose that means the market’s eyes have reached this layer, enough for optics to become a standalone theme product.

But one of the headline numbers probably snagged your eye. A GAAP net loss of $7.2B. What does it mean that a $1B-revenue company lost more than $7B in a quarter?

2. What the $7.2B Loss Really Is

To put the conclusion first, this loss involved no cash leaving the company, and it does not mean the business rolled over. It is an accounting loss created by the stock rising sharply over the past year.

Here is what happened, in order. Lumentum had issued convertible notes some time ago. A convertible note is borrowed money, but in the form of a bond the holder can swap into stock at a preset price if they choose. Over the past year, with the stock up severalfold, the value of that conversion option grew. This quarter the company proactively converted a portion of these notes into stock (equitization), and as a result $1.1B of debt was erased from the books. That is about 35% of the convertible notes that were outstanding [2].

Here is why an accounting loss shows up.

On the books this debt is recorded at the amount borrowed, but the market value of the shares handed over in repayment is far larger, by as much as the stock has risen. Accounting books that difference as a loss on debt extinguishment. This quarter that amount was $7.8B, which is how the $7.2B GAAP net loss came about [1][2].

As a rough analogy, it is like borrowing the price of rice while promising “you can take our field as repayment,” and in the meantime the field’s value has gone up severalfold. The moment you repay with the field, a big loss prints on the books, but the cause of that loss is the field’s value, that is, the company’s value, having risen in the first place. So I read this $7.2B as closer to a footnote than a worry. Actual quarterly profitability is told by the non-GAAP side: net income of $326.3M, or $3.23 per share [1].

There is one thing to add. Since debt was swapped into stock, dilution for existing shareholders is real, and unlike the one-time accounting number, it stays. That said, interest-bearing debt did shrink, so I lean toward seeing this as a sensible trade: cleaning up debt while the stock is high.

3. Where These Orders Come From

So where does the demand that doubled revenue come from?

The starting point is hyperscaler spending. I covered the capex upgrade trend confirmed in the big four’s late-July results in The GPU Repricing Cycle and Q2 Hyperscaler Earnings: Which Hardware Layer the Capex Flows To, and when that money goes into a data center, a network linking the GPUs to each other always goes in right beside them, and the physical layer of that network is optics. The transceivers that turn the signals running between GPUs and switches into light and carry them, the InP laser chips inside them that make that light, and the pump lasers in the long-haul links connecting data centers to each other: as it happens, all of it is on this company’s product list.

One anecdote from this call captures the scale of this demand well.

For one major hyperscaler, the network capacity connecting two AI data center sites is reportedly double the entire global backbone that company laid over the past decade [2]. A line connecting ‘just two sites.’ The picture is training and inference splitting across multiple sites and inter-site traffic growing, and thanks to that, pump lasers for long-haul links are effectively sold out even after shipments grew more than 80% year over year, and the company plans to quadruple shipments over the next several quarters [2].

I actually found this part interesting and mentioned it in the subscriber-only chat as one of the seven things I was watching.

This flow itself is not a new story. In fact, together with Aurelion Research, I had already handed you a big hint. In July’s A Conversation with Lumentum, which recorded a conversation with Lumentum IR, we had already heard that EML capacity was up eightfold in two and a half years and still could not keep up with demand, and these results are close to the first quarterly closing where those words print as numbers.

Reading the CEO comment, though, I get the impression that what the company really wants to emphasize is not the products selling today. The CEO paragraph of the press release strings together words that are probably a bit unfamiliar: OCS, 1.6T, ultra-high-power CPO lasers, a first ELS module order, and NPO. Five of them packed into one paragraph, and the concluding sentence is that “optics are starting to penetrate in-rack connectivity” [1].

Why is a company that sells transceivers talking about the inside of the rack? And why is the simultaneous appearance of these five words the real news of the quarter?

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Abstract

The Trump administration suddenly came out saying it would block Chinese transceivers. In the early hours of August 4, Reuters reported the FCC’s import ban draft, and communities everywhere got excited. And as you’d expect, US optical stocks rose double digits intraday. In the market, an interpretation was going around that AXTI gets hurt if China retaliates, and I think that’s a one-dimensional reading. Then a few days later, commentators like Jukan, separately from this news, started talking about a short-term short memory, long optical trade based on NVIDIA’s roadmap, so regulation and architecture are pointing at optics for different reasons. This article checks the disclosure documents of Innolight, which raised $6.8B five days earlier, to see how much of its volume is actually US-bound, and works down through capacity and the InP substrate chain to ask whether US-made supply can absorb that demand. To note my direction up front, I think the essence of this regulation is that it exposes the fact that without transceivers, even the US cannot build AI data centers.

Contents

1. A Draft Out of Nowhere

2. The $6.8B Five Days Earlier

3. The US-Bound Volume in the Disclosures

4. A One-Line Fight over the Text: Nationality or Origin (Paywall)

5. Can US-Made Supply Absorb the Demand

6. Going Down to InP: AXTI

7. Can You Build an AIDC Without Transceivers

1. A Draft Out of Nowhere

The Trump administration suddenly came out saying it would block Chinese transceivers. It was a Reuters exclusive on the morning of August 4 (US time): the FCC is drafting an import ban on Chinese data center equipment including new Chinese optical transceivers, aiming for publication within the year and immediate effect [1]. The stated grounds are concerns over data theft, malware, and remote service disruption. I remember people getting very excited. Especially on X, saying that because of the FCC event, US optics-related stocks, for example AAOI, COHR, LITE, would be the beneficiaries.

Reuters exclusive headline, FCC drafting ban on Chinese data center devices, 2026-08-04

Let me start with the market reaction. AAOI rose around 20% intraday, Coherent and Lumentum double digits, and Corning around 8% (intraday figures that vary by when you sampled them) [2]. The Chinese side reacted a day late since the report came out after their market close: on August 5, Innolight’s A-shares fell as much as 16% intraday before closing down 7%, the H-shares fell 5.2%, and the next day they bounced right back to near record highs. The swings continued after that, and on August 10, the same day as a broad optics pullback ahead of earnings season, it closed down 6.9% at HK$1,033. Still 5% above the offer price [3].

And there was one more interpretation people attached to this news. That if China retaliates by squeezing InP exports, AXTI, which makes substrates in China, gets hurt. I think this is a one-dimensional reading, and why becomes visible only once you go down the InP chain, so I’ll write about it later.

What to look at first is the company that is number one in the transceiver industry and sits right in the middle of the ban’s target. This company, of all times, had just raised money in Hong Kong five days earlier.

2. The $6.8B Five Days Earlier

A few days before the FCC event, on July 30, Zhongji Innolight listed its H-shares in Hong Kong. At an offer price of HK$980, it raised HK$53.4 billion (about $6.8B), the largest in Hong Kong since Alibaba in 2019 [4][5]. The Hong Kong retail tranche was 16.8x subscribed and the international tranche 9.7x, and 33 cornerstone investors including Temasek, ADIA, BlackRock, Alibaba, and Tencent took half of the offering (about HK$26.7 billion worth) under a six-month lock-up [4][5].

The ten days around the listing were noisy in the headlines. When the offer price printed around 11% below the A-shares (per press reports), the A-shares plunged 15.7% on the pricing disclosure day [6][7], and on debut day, sitting on top of a chip selloff week, the stock fell as much as 9.8% intraday before closing 2% below the offer price [8][3]. But look at the closing-price chart and there is no stretch you could call a crash. It recovered the offer price the next day, and through the swings since, it sits at HK$1,033, 5% above the offer price even as of the August 10 close [3]. One fact remains. The world’s largest optical module company is holding net proceeds of HK$52.9 billion [5].

How they should use this money, honestly, is the part I’m most curious about. The uses listed in the prospectus are R&D, overseas production capacity expansion, supply chain strengthening, M&A, and general working capital [9]. Five items, and where the weight lands is open, and the FCC draft that came five days later added a variable to that answer. The meaning of the overseas capacity item now changes completely depending on the regulatory text.

Figure: Four forces on the debut day

3. The US-Bound Volume in the Disclosures

Look at the disclosures and quite a lot is US-bound. US customer revenue was 75.9% in 2023, 57.3% in 2025, and 61.7% in Q1 2026 [9]. Overseas revenue overall is above 90% as of Q1. So this is a Chinese company where 60% of revenue comes from the US. This is exactly where the FCC draft is aiming.

But the same disclosures carry numbers pointing the other way. Goods made in mainland China and sold to the US were under 1% of total revenue throughout the track record period. By year: 0.3%, 0.9%, 0.2%, and 0.0% in Q1 2026 [9]. Which means the US-bound volume has effectively already been moved entirely to offshore production. The Singapore entity TeraHop Pte is the hub of overseas production, and the main base for North America-bound goods is Thailand [9][10]. The way Chinese vendors have been adding capacity in Thailand and Indonesia is exactly the layout we covered in April in Chinese Optical Modules Own 7 of the Top 10 Seats.

US revenue is 60%, but mainland-origin US-bound is around 0%. The gap between these two numbers decides the entire effectiveness of this regulation. As the optical communications research firm Cignal AI pointed out, the draft does not yet have a definition of “Chinese” [10]. Do you look at the company’s nationality, or the place of production. The question Cignal posed compresses this ambiguity. Is a module that combines Marvell’s DSP and Lumentum’s optics, assembled in Malaysia, Chinese [10]?

Why does the definition matter this much: because the same module from the same company is a legal import under one criterion and a banned item under the other. Unlike routers or drones, transceivers sit on a layout that a definition clause is perfectly positioned to split: the top suppliers are Chinese by nationality and Southeast Asian by production. One sentence in the Federal Register will decide whether billions of dollars of volume crosses the border.

Prospectus, origin of US-bound shipments and regional revenue pages, 2026-07-22

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