SK hynix announced on August 20 that its co-packaged optics roadmap paper had run in Nature Electronics[1]. CPO puts the optical chip that moves signals as light inside the same package as the compute chip.

I opened the paper right away and followed the twelve authors’ backgrounds and where the company had put money before that, which I wrote up in One Interconnect Company, All Three Memory Makers on the Cap Table: Fifteen Months of SK hynix’s CPO Track. Something stayed with me after I filed that one.

The paper is a review. It reads less like a company product roadmap and more like a summary of where the field has gotten to, with tables of energy and bandwidth per integration method and a list of problems still open.

The newsroom post had a different flavor. There the company put its own name behind a bigger claim, that memory would be bound into a single pool to get past the memory wall[1]. The paper surveys, the announcement points.

So I got curious. Is this only SK hynix’s direction?

Samsung is already out in public. Its foundry declared entry into silicon photonics in March and published a schedule. That leaves Micron, which has no roadmap, no paper, and no press release on optics from the last ten years.

So I went to the patents. And one filing came back with a February 2023 priority date that is still under examination. The title is optical signaling for stacked memory device architectures. Memory dies stacked up, with light running between them.

Something the company has never said out loud is sitting at the patent office right now.

Three memory makers on two axes, public disclosure above and patent priority below

TL;DR

• SK hynix’s Nature paper reads mostly as a review, but the newsroom post put the company’s name behind memory pooling as the way past the bandwidth bottleneck

• Samsung already stands in the same place as a foundry product. It laid down a PDK at OFC and published a turnkey schedule

• Micron has no public optical roadmap from the last ten years, so I went through patents and job postings instead

• Binding memory with light is an idea more than twenty years old. Micron filed in 2002 and Samsung in 2008

• Narrowed to the silicon photonics package family, Micron has a 2023 priority filing that is still under examination

• Lined up by priority date, filings recur across several generations from 2002 to 2023. What clearly stopped was the public announcements

Contents

1. Why This Comes Up Now

2. Samsung Is Already Standing There

3. No Announcements, So Open the Patent File

4. The Role Micron Is Hiring For

5. Ten Billion Dollars and August 27

6. Four Layers That Are Easy to Miss

7. Where This Goes

8. References

1. Why This Comes Up Now

Memory bandwidth has come up several times in this series. The routes to more bandwidth and the paths for moving capacity outside the package are laid out in Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains.

The short version. Putting memory right beside the GPU made it fast and also made capacity hard to grow. Stacking more layers is getting expensive in heat and yield. So the remaining path is to move memory outside the package and connect it through a channel.

Right now that channel is copper. CXL is the one. It works, though round trip latency runs somewhere around double what local memory costs. The number moves with the device, the number of switch hops, and the memory media, so pinning it to one figure is hard. Either way it is slower, which means software has to keep deciding what sits near and what sits far.

The targets in the SK hynix paper are worth noticing here. More than 100Tb/s per node, under 1 picojoule per bit, and chip to chip latency below 10 nanoseconds[1][2]. That last number is aggressive. It is a target for the chip to chip optical link though, not for end to end memory access, since controller, protocol, queuing, and coherence costs stack on top of it. Even so, a link at that level would make tier management much lighter than it is today.

The paper says as much itself. It leaves an optical memory interface that keeps coherence while lowering latency on the open problems list[1]. The picture got drawn and the method got assigned as homework.

Here is where it splits, why a memory company would look at this directly. Turning the channel optical used to belong to the networking companies and the foundries, since CPO started by putting an optical engine beside a switch. But when the thing at the far end of the channel becomes memory, the situation changes. The optical chip has to come inside the memory package, and the company that designs, assembles, and tests that package is the memory company. It stops being somebody else’s problem.

2. Samsung Is Already Standing There

I mapped Samsung once in July. In TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM I laid out who holds which of the chips that go on the interposer, and Samsung was the only one holding memory, logic, and the optical chip together.

It has moved further since. At OFC 2026 on March 17 the foundry division formally declared entry into silicon photonics and said its PDK was complete[3]. A PDK is the toolkit customers design with. Its arrival means customers have a base to start design and tapeout from. It does not mean production yield and process qualification are finished. The kit reportedly carries more than forty device models with a verification flow, on a 300mm process[3].

Why the PDK matters is that optical devices diverge from simulation more than electrical ones do. A modulator that behaves in the schematic often comes back strange on the actual wafer. The PDK is the foundry’s attempt to shrink that gap before handing it over, and without one you cannot build a repeatable standard design flow. That is also why Samsung bothered to mention that free carrier absorption and self heating went into the models[3].

The schedule went public too. Thermocompression bonded optical engines in 2027, turnkey CPO service in 2029[4].

That is the visible picture. Samsung tells you because Samsung has to sell. A foundry only has a business when customers knock, and that means saying where you are, repeatedly.

So what about Micron?

I searched by silicon photonics, optical I/O, CPO, and conference presentations, and nothing recent comes back. Recent OFC and ECTC programs carry no Micron optical talk, and no optical interconnect startup investment shows up either. As far as I can find, the company has issued no press release on the subject at all.

When there are no announcements you look somewhere else. I opened the patent file and the job postings.

What follows is that record. Line the three companies up by priority date and the order comes out different from the market’s impression, and on Micron’s side one filing is still waiting on examination. The qualifications on a currently open job posting carry a word the company has never put in a press release. The dates on the Boise lab announcement and the SK hynix Indiana groundbreaking sitting a week apart, and Micron’s continued absence from the US government optical programs, both come up later.

The last part is the value chain. Everybody already says packaging benefits when memory gets pooled, so instead I pulled four layers that rarely get named. They are process steps you pass through whichever way the architecture goes.

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Abstract

On August 20 SK hynix used its own newsroom to announce that a co-packaged optics roadmap paper had been published in Nature Electronics. CPO means putting the optical transceiver inside the same package as the processor. The company’s post leans on two things: Seunghoon Hong, its AI Infra team lead, served as a corresponding author, and the work goes beyond HBM innovation to a system-level blueprint. I read the post, opened the 15-page paper next to it, and then walked through the public record of all twelve authors one by one. That is when I found out this track did not start with the paper. The company post has not one line about the step before it. I treat this announcement as a positioning signal rather than a CPO product schedule. What holds up is that the technology choice was already marked in money, with all three memory makers leaving that mark side by side.

Contents

1. The company published this itself

2. The wall the paper draws

3. The table the post left out

4. Twelve authors and where they come from (Paywall)

5. Where the track actually starts

6. The same cap table

7. The distance still left

8. How far I take this

1. The company published this itself

Here is the headline that went up on the SK hynix newsroom dated August 20.

“SK hynix’s technology roadmap for co-packaged optics features in ‘Nature Electronics,’ as AI competition shifts from chips to systems” [1]

SK hynix newsroom post

The paper is “Co-packaged optics for high-performance computing and artificial intelligence,” the journal is Nature Electronics, and the format is a Review article. The front page is stamped submitted November 18, 2025 and accepted July 8, 2026 [2].

The company names two corresponding authors. Seunghoon Hong, team lead at AI Infra, SK hynix, and Professor Kyusang Lee of the Department of Electrical and Computer Engineering at the University of Virginia [1]. The collaborating institutions are listed as UIUC, NTU, MIT and Yonsei.

Look at the paper itself and there are twelve authors. Nature titles attach a contact e-mail only to corresponding authors, and the bottom of the first page carries six e-mail lines, one of them on the sk.com domain [2]. So the company took those six and introduced two of them as the lead corresponding authors.

AI Infra is an organization SK hynix set up in January 2024. By the company’s own newsroom description it groups global sales and marketing, the HBM business, and Memory System Research, which does pathfinding beyond HBM [3].

The newsroom even added a footnote defining what a corresponding author is. Principal authors who oversee and take responsibility for the whole process, from planning through submission, peer review response, and post-publication questions [1]. The fact that the company bothered to footnote that phrase tells you where the weight of this announcement sits.

The company did not leave this in an internal research news column either. The official X account pushed the same content on the afternoon of August 19 local time, with the hashtags #SKhynix #CPO #AIInfrastructure [4]. The Korean newsroom date reads August 20 because that is Korea time, so the global channel started the day before.

The X wording carries one more edit, though.

“Published in Nature Electronics, a new paper from @SKhynix and University of Virginia researchers explores how CPO can overcome the ‘bandwidth wall’ through optical connectivity.” [4]

SK hynix and University of Virginia researchers is all that survives in that sentence. The Korean newsroom lists UIUC, NTU, MIT and Yonsei too [1], and they are gone from the global channel. By author count the MIT and UIUC share is not small.

A memory company taking part in an optical interconnect review is not new by itself. A company turning that into an external message is a different thing. And the one partner name left standing in that message is the University of Virginia, which comes back later.

2. The wall the paper draws

The term the paper’s own text uses for this bottleneck is bandwidth wall. Memory wall shows up once, in a reference title. Here are the scaling numbers behind it. Every two years compute throughput went up 3x, DRAM bandwidth 1.6x, and interconnect bandwidth 1.4x, while on the same axis AI model training compute jumped 8.8x [2].

Newsroom scaling graphic, 3x compute against 1.4x interconnect

The company post quotes only two of those, the 3x and the 1.4x [1]. The paper has DRAM bandwidth at 1.6x sitting in the same figure. A memory company issuing a release with the DRAM curve dropped out is a curious edit.

So compute moves 3x while the pipe that carries the data moves 1.4x. The gap bites hardest at the boundary between memory and logic. Here is the paper’s own sentence.

“the gains are confined to intra-package communication; once data goes beyond the memory-logic boundary, electrical interconnects ... incur resistive and capacitive losses that greatly increase with frequency and distance” [2]

What HBM gained holds only inside the package, and the moment data crosses the memory-logic boundary the losses in copper take over again. You can stack DRAM dies with TSVs, which are vias drilled vertically through the chip to make the connections, and pull multiple terabits per second out of them, and that gain still will not follow the data out of the package.

This series has been over that diagnosis several times. Once in Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains, which laid out three ways of raising memory bandwidth, and once on the optical memory fabric side in The More Anthropic Buys Micron HBM, the Faster Optical Memory Pooling Arrives. The diagnosis has been around for a while. A memory company putting its name on that chart and then issuing a release about it is the part that changed.

3. The table the post left out

The company post summarizes the paper’s technical targets in three lines. More than 100 Tb/s of bandwidth per node, energy below 1 pJ per bit, chip-to-chip latency under 10 ns [1]. The same numbers are in the paper [2].

There is one more table in the paper that the post did not carry over. Table 2, titled representative industrial CPO and optical I/O platforms in the original. It mixes shipped products, demonstrated prototypes and some projected figures, so not everything in it is in production. Broadcom Bailly and Davisson, NVIDIA Quantum-X Photonics, Intel OCI, Ayar Labs TeraPHY, Lightmatter Passage M1000, Celestial AI Photonic Fabric, Ranovus, Avicena, Microsoft MOSAIC. Ten rows, nine companies [2].

paper Table 2, industrial CPO and optical I/O platform list

Switch companies, accelerator companies and optical I/O startups are all in there, and the memory makers are the ones missing from the list.

This gap is something I already mapped once in July. In TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM I mapped who holds each of the three chips that go on the interposer, meaning HBM, logic and the PIC. Samsung was the only one holding all three, and SK hynix held memory while sending the logic base die outside. That piece sorted SK hynix’s routes into CPO into three. Packaging verticalization in Indiana and Cheongju, the memory-system CPO review at the 2025 Future Forum, and the CPO ecosystem on the public-project side.

I went back to the original on that Future Forum item. It was held September 11, 2025 at the Icheon campus, and the third agenda was a joint presentation by KAIST Professor Kyoungsik Yu and SK hynix Vice President Hoyoung Son [5]. The title reads like this.

“A future connected by light: CPO (Co-Packaged Optics) technology evolution and its ripple effects on the memory industry” (author translation from the Korean original) [5]

SK hynix Future Forum 2025 newsroom

Son’s title is worth a second look. He is head of Advanced PKG Development [5], which is a package development organization rather than strategy or planning. And the content, per the newsroom, was sharing a review of silicon photonics technology types, working through how to apply it inside and around the memory system, and setting out what preparation is needed across Architecture, Design, Device and Package [5].

That July piece also left a monitoring item at the end. Watch whether the memory-system CPO reviewed at the Future Forum turns into an actual R&D program or a partner disclosure. This announcement is the first answer to that item. An academic partner is disclosed, and a company employee put his name on it as a corresponding author. It is still not confirmation that an R&D program is running, so I am leaving that item half filled rather than closing it.

A later figure in the same paper puts a memory pool and an XPU pool facing each other across a single photonic interposer [2]. The company post ran that same concept diagram [1]. The side with no name in the table takes up half of the future architecture.

The word CXL never appears in this paper. I checked by searching the full text. UCIe shows up five times in the same document, NVLink and PCIe twice each. The die-to-die standards and the network standards are covered, and the current standard for memory pooling is the one that is missing.

The paper talks about pooling memory without touching the electrical pooling standard the industry actually uses today. The right reading is that the review’s scope sits on the optical architecture side. A missing word and a deliberate exclusion are different claims, and I will not push it that far. Readers should account for the gap either way.

That is as far as you get from putting the paper and the release side by side. Checking the public record of all twelve authors one at a time makes it fairly clear where this collaboration came from. And there was a step before it that appears nowhere in the company post. A trace of money that moved before the paper did.

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Contents

1. An Update After Four Months

2. The One Year Return, and the Path Underneath It

3. How to Read These Numbers

4. July: Zero Sells

5. The Homework April Left Behind

6. The 15 That Disappeared: Judgment and Raising Cash

7. The 8 That Came In

8. What the Two Snapshots Do Not Show

9. What Remains: Why I Still Hold Them Four Months Later

10. The SMH Comparison: Same Money, Same Dates

11. The Cost of Concentration

12. Conclusion

1. An Update After Four Months

On April 11 I wrote 1Y +122%: What Happens When a SiPh Engineer Only Buys What He’s Touched and disclosed all 40 or so tickers across three accounts. At the end of that piece I wrote “next update: Q3.” This is the piece that keeps that promise.

On a trailing one year basis ending August 17, the combined return across the three accounts is +124.25%. That moved about 2pp from the +122.29% I wrote in April.

Looking at this number alone, it seems like nothing happened for four months. But open the account records and it is the opposite. So instead of walking through allocations ticker by ticker like April, this piece tries to focus on what actually happened during those four months.

So the material for this piece is the records underneath rather than the account screens. I downloaded a full year of deposits and withdrawals plus 1,600 executions, and matched them one by one against the sentences I wrote in April. Whether a ticker I said I would “keep watching” four months ago is still in the account, what orders I actually placed when the drawdown came, and whether anything came in and went out unnoticed between the two disclosures.

For reference, on August 11 and 12 I moved a bit over 20% of the accounts out to a CMA account. That was money for another purpose and it had nothing to do with a market judgment. So part of the balance curve coming down from the June high is the portion I took out. The return numbers in this piece are calculated with all of those flows stripped out.

2. The One Year Return, and the Path Underneath It

Cut month by month, it looks like this. I calculated it with the Modified Dietz method, reflecting each month’s starting balance and the money that came in and out on a daily basis, and I put SMH next to it for the same period. The window is August 1, 2025 to August 17, 2026, which is twelve and a half months.

In April, 58% got added in a single month. And in July, 30% went away. In August it is in the middle of taking back 20%. Out of thirteen months, five trailed SMH.

Monthly return bars and relative performance versus SMH. Cumulative curve normalized to a starting value of 100, no dollar axis

The reason the trailing one year number looked like it stood still is that these months offset each other. But this only means two trailing one year readings with different as of dates printed 2pp apart, and the actual performance over the four months has to be looked at separately. That number comes below.

April is unusually large in this table, and the April piece was published on April 11. So about halfway through that month, holding an account that had already risen a lot, I wrote “1Y +122%.” The timing of the disclosure was good, and luck played a big part in it. If you look at what happened to the same account four months later in this piece, that difference should become a little clearer.

The return summary section of the April 11 article

Over the same period, the semiconductor ETF SMH returned +109.87%. From an adjusted close of 283 dollars on August 1, 2025 to 594 dollars on August 17. It was a window where holding SMH alone and sitting still would have doubled your money. My chained return of +132.84% is a number sitting on top of that.

Two numbers show up here and it may be confusing, but the basis is different. +124.25% is the trailing one year money weighted return the broker calculates, and +132.84% is a twelve and a half month time weighted approximation from chaining the table above. The calculation method is different and the measurement window is different, so the gap between the two cannot be explained by cash flow effects alone. When comparing against SMH in this piece, I use the latter basis throughout.

If I match the basis to the monthly table and cut only from the end of April to August 17, the picture gets clearer. Part one was published on April 11, but this starts from month end, so it is a window that begins about three weeks later. Over this window SMH is +17.24% while my portfolio is +6.80%. I fell behind by 10.4pp.

The biggest cause, as you already know, is July. If you look at the difference column in the table, 12.93pp opened up in that single month, which is larger than the other three months combined. SMH also fell more than 17% in July, but my account fell more than 30%. It is a concentrated, high beta small cap optics portfolio, so it took a much bigger hit than the index, and even after taking back 20% in August it still has not closed that gap.

The conclusion of the April piece was that “concentrating in what you know beats diversifying into what you do not know,” and three months after writing that sentence, the other side of concentration arrived. If you gather names that move in the same direction, they rise together and they fall together. The fact that it fell nearly twice as much as the index probably includes some individual bad news, but the composition itself, a group of names tied to the same direction, worked in the direction of amplifying the drawdown.

The April piece ended with the sentence that it was 42pp ahead of SMH. What happened to that edge four months later is in section 10.

3. How to Read These Numbers

Before laying out more numbers, it seems right to state the calculation method first. The same account can produce different returns.

The +124.25% that shows on the broker screen is a money weighted return. When and how much you put in gets reflected in the result. Money put in during September compounded for a year while money put in during July only compounded for a month, and this method puts that difference into the calculation.

The value from chaining the table above is +132.84%. Because it links monthly Modified Dietz returns, it is an approximation of a strict time weighted return, and months where a large amount came in mid month, like July, carry some error. This one reduces the influence of deposit and withdrawal timing, but what is left is not only stock selection. Position sizing, trade timing, and how much cash was held are all mixed in.

There is a reason the two diverged by more than 8pp. I kept adding money from March through July, and it was with an account grown that large that I took a -30% month. The weight of a bad month taken with large capital late outweighed the good months made with small capital early. That is why the dollar based result comes out lower than the stock picking result.

And, in order to compare my results, I tried comparing against the semiconductor ETF SMH. This was something a subscriber requested, and I thought it was a good reference so I prepared it again this time. If the same money went into SMH on the actual deposit dates and amounts, how much would it be now. That calculation is section 10.

There is one more thing I want to write down here. There are plenty of pieces that disclose returns, but most of them cut out the good stretch and show that. I did the same in April. I announced a one year return about halfway through a month where 58% had been added in a single month. Pieces like that leave the reader with very little after reading. Either envy or suspicion, one of the two.

What I want to do this time is the opposite of that. Account records do not allow you to keep only the bragging. What orders I placed in July, what I sold two weeks after writing that I was convinced in April, how many tickers I bought impulsively while writing a piece and how those ended, all of it is there with the dates. If you lay that out as it is, good judgment and things gained by luck and plain mistakes become distinguishable from one another.

I think what is useful from the reader’s side is that distinction. This is not to say you should buy my tickers. It is about seeing, through one person’s record, how long something written down as conviction actually holds. And then when you look at your own account, you will probably see something similar.

So from here on are the things that only come out when you open more than 1,000 executions. What I did in July, why the 15 tickers that were there in April disappeared, what trades do not show up in either of the two snapshots, and why I still hold the 35 that remain.

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On August 14, the June 30 positions of two funds were disclosed on the same day. Leopold Aschenbrenner’s Situational Awareness had pulled off almost all of the roughly $8.4B in puts it carried through the end of March in a single quarter, and Gavin Baker’s Atreides went the other way and doubled its QQQ put contracts [1][2][3][4]. A month later, on July 29, semiconductor and optics names all bottomed together, and while the index fell a bit over 10% that day, SanDisk was down 55% and Astera Labs 48%. This piece is part two of the August 1 article, and it goes back to the SEC originals to see where each of them cut the AI infrastructure value chain and how each reads it. On Baker’s side I looked at one more thing. The speaker list for the TomorrowX Summit he co-hosts in Austin in November overlaps substantially with the top names in this 13F [5]. To put my lead up front, I think the part of Baker’s 13F actually worth reading is less the list of top holdings and more the stretch he did not touch.

Contents

1. Two 13F Filings Opened on August 14

2. Aschenbrenner’s June 30

3. Baker’s June 30

4. What the +1.73% Is

5. Splitting Interconnect Into Layers

6. Why Only Lumentum Was Dropped

7. What the Two Filings Share, and Cerebras at 10.7%

8. Baker’s TomorrowX Event

1. Two 13F Filings Opened on August 14

August 14 was the 13F deadline. The rule is that you file your holdings as of June 30 within 45 days, so every quarter the 13Fs of US institutions all open at once on this day. Berkshire came out that day, so did Druckenmiller, but the ones I looked at with interest were two.

The reasons being

1. AI and AI infrastructure and related tech stocks make up most of my brokerage

2. Memory, optics, semis, related names, a wide range of stocks that both 13Fs hold

I see these two as the two masters of the tech long. Leopold Aschenbrenner in particular is someone I think looks carefully at bottlenecks and invests by seeing straight through to those points, and he did it successfully. (Leaving the leverage aside, of course.) Everyone knows this, but he left OpenAI and set up Situational Awareness in 2024, and reportedly grew assets under management from around $200M at launch to tens of billions in two years.

Gavin Baker ran the Fidelity OTC fund for a long time before starting Atreides, and he keeps up an active presence in online communities, so these days he has exchanges with real depth with all sorts of tech industry experts, tech stock supporters and analysts. There’s an event that’s been getting a lot of promotion lately, where he co-hosts something called the TomorrowX Summit under his own name. It’s held in Austin in November, and looking at the speaker list, I get the sense there aren’t many tech longs who can pull semiconductor company CEOs together like that [5].

Part one on these two was written on August 1. In Compute Short, Memory Long: Aschenbrenner’s Unwind, Gavin Baker’s Hold I opened the March 31 filings and covered why compute sells expensive and memory sells cheap. When I wrote that piece, I was looking at why Leopold built his positions the way he did, and by coincidence Baker’s portfolio was also sitting on tech stocks in a fairly similar way, so I found it interesting to analyze.

This piece is the picture from the next quarter.

But the situation of these two has now split completely. Leopold is reported to have had his public equity book forcibly liquidated in July, and Baker is still riding high (there is no public data on the fund returns themselves, so this is just my impression). That said, people say Leopold blew up, but his year to date return is still above the average person’s. I thought his attempt was a bold and admirable challenge, but looking at it now with hindsight it was a reckless challenge, and it feels like he got brutally trampled.

SEC EDGAR filing index for both funds, 2026-08-14

All the numbers were pulled directly from the info table originals posted at the SEC. The aggregator sites were still showing end of March data as the latest as of yesterday, so to check I downloaded and parsed the original XML, and that work took half a day. Thankfully the verification came out clean. The implied unit price you get by dividing reported value by share count matched the June 30 close for every name [6]. Micron $1,154.29, Ciena $490.56, QQQ $736.40. Which means the parsing was not wrong.

Let me draw one distinction up front. What a 13F shows is a slice cut out of the book. Only US listed equity longs and options appear, and shorts, non US assets, cash and private stakes all drop out. So when I talk about weights below they are all on a reported value basis, and the weight in the actual book could be smaller than this. That gap becomes the raw material of this piece in sections 4 and 7.

2. Aschenbrenner’s June 30

The thing that stood out most in the March 31 filing was the puts. Around $2.0B on the SMH semiconductor ETF, around $1.5B on NVIDIA, roughly $1B each on Oracle, Broadcom and AMD. Add Micron, TSMC, ASML, Intel and Corning on top of that and it comes to around $8.4B on an underlying market value basis [4]. It was a double structure, long memory and power with puts draped across semiconductors broadly.

Open the June 30 filing and this is gone.

The only put left is Infosys, and that one is around $5M [3]. Everything else disappeared, and Micron and TSMC flipped completely from puts to common. Nothing is public about what judgment happened in between. Someone who held 1.72M Micron puts in March holds 4.83M Micron common shares in June.

So what came in to fill that space. The answer is two memory names. SanDisk at around $5.7B and Micron at around $5.6B, together 55.6% of reported value. After that comes Bloom Energy at around $1.9B, TSMC at around $1.3B, Nebius at around $1.2B, then CoreWeave, Core Scientific, STMicro, Applied Digital, RIOT, IREN [3]. It’s a lineup that runs through power and neoclouds and bitcoin miners, and the big picture is the inputs to compute. It’s a layout that says buy electricity and memory and compute comes out.

Situational Awareness Q1 2026 13F info table, put rows highlighted

The biggest empty seat in this filing is optics. There isn’t a single name. No coherent equipment, no transceivers, no optical DSP, not even connectors. It carries the same AI infrastructure fund label but the connection layer is completely empty. This comes back later as the biggest difference when we compare with Baker.

This picture is right before the liquidation. On June 30 he had all the hedges pulled off and 55% loaded into two names, and you all know what happened in July. It’s said to have been a forced liquidation.

3. Baker’s June 30

Atreides’ total reported value jumped from $5.0B at the end of March to $14.3B at the end of June [1][2]. The number of holdings actually went down, from 54 to 49. So what came in to make it grow like that. Yes, as you’ve probably guessed, SpaceX.

27.33M shares, around $4.6B, 32.6% of reported value. It’s the single largest position, and it is more than five times the gap to Micron, the second largest on a common stock basis [1].

I’ve held SpaceX myself since the IPO, and I’ve kept writing in support of the earnings analysis and the compute rental business. What I laid out in SpaceX’s First Earnings Report: Revisiting the S-1, and the Hardware Value Chain Behind 10GW is that story, and my view is that this company is closer to an AI company than a space company. I see it as an AI company wearing a space costume. I don’t think the reason Baker loaded 32% into it is the orbital launch business either.

The second largest is the QQQ put. Around $2.3B on 3.2M shares, 16.4% of reported value. He more than doubled it on a contract basis from 1.4M shares at the end of March [1][2].

This part is interesting, because in the second quarter QQQ went from $577 to $736, up a full 27.6% [6]. While the index was melting up like that, he doubled his index puts. One of them pulled every hedge off and the other doubled his hedge, and both of them are AI infrastructure bulls.

The rest of the top names are Micron at around $800M, Cerebras common at around $600M plus around $100M in calls, Meta calls at around $600M plus around $200M in common, Astera Labs at around $500M, Ciena at around $300M, Credo at around $300M, Coherent at around $200M [1].

Layer by layer comparison of the July 29 trough drawdown. QQQ and NVDA against the AI hardware names

The lows clustered on July 29. Almost every name bottomed together that day, but the size of the drawdown was completely different by layer. Measured against the June 30 close, while QQQ fell 10.1% and NVIDIA 5.0%, SanDisk fell 55.3%, Astera Labs 48.3%, Bloom Energy 45.9%, and Coherent 43.7% [6].

At the time I was studying the representative coherent optics players in order to look into Scale-Across names, and the piece I wrote is exactly Down 40%, 40%, and 14% in Six Weeks from last July, and the moment of publication was the middle of this correction, with the actual bottom coming ten days after that piece.

Up to here is the range anyone can see by skimming public material. The top holdings list and the drawdown table go up on the aggregator sites within a day or two.

There is a separate reason I downloaded the original XML and calculated every share count delta. The share count increases for Ciena and Coherent and Nokia and Semtech were the same down to the second decimal place. What that means, and once you know it, is what separates judgment from plain drift in this 13F.

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On August 13, one slide was shared at the Sandisk Investor Day. The content was that Meta joined the HBF consortium following Google, and ten days earlier, the first HBF standard specification of up to 512GB and up to 3.0TB/s was published through OCP. Ironically, in the same week, Samsung brought out the zHBM concept that stacks memory vertically on top of the accelerator. Then the question, naturally, has a place it heads to. What about Micron? Micron is officially not putting its name in this game. However, the phrase “stacking NAND” points to a completely different structure at each company, and if you do not distinguish them, you end up drawing the beneficiary map wrong. So this article is going to try dividing the question into two. How to stack, and where to place the capacity made that way, relative to the processor. My interpretation is on the side of “whichever direction the stacking competition gets settled, wouldn’t a considerable part of the growth go not to the memory companies but to the optical interconnect layer?” The evidence has been prepared with job posting originals and physics arithmetic.

Contents

1. August 13, One Slide at Investor Day

2. Three Meanings of the Word “Stacking”

3. Micron’s Public Stance and the Careers Site

4. The Structure Micron’s Job Postings Draw

5. Beside, Above, Beyond: Three Paths and Three Walls

6. Microseconds and Meters: The Physical Reason NAND Is Allowed to Move Away

7. The Optics Map: Which Layer It Falls On

8. Stacking Equipment and Optical Links: The Related Names

9. Conclusion

1. August 13, One Slide at Investor Day

Let me start with the $SNDK story. Sandisk stock rose 6% on August 12 alone and reached the mid $1,300 range (as of the 2026-08-12 close) [3], and on the 13th, the day of the Investor Day, it rose another 14% and closed at $1,528 (as of the 2026-08-13 close) [1][4]. In terms of the gain since the start of the year, it is over five times, remarkably [3][4]. It is true that the NAND shortage cycle made these numbers, but the place where my eyes stayed long that day was one slide on the technology roadmap side, rather than the financial targets page.

The “HBF Consortium Milestones” slide from the Sandisk 2026 Investor Day. The August 2026 milestone shows “Consortium Expands: Meta”

The timeline of the slide reads like this. In August 2025, Sandisk and SK hynix agreed on HBF (High Bandwidth Flash) standardization, and in February 2026, a consortium was formed under OCP (Open Compute Project, the body where hyperscalers turn hardware specifications into open standards). The ones that joined at that time were Google and Tenstorrent [5][7]. Until then there did not seem to be much reaction, but just recently, in August 2026, when the first standard spec was published and the Meta logo went up in the consortium expansion box [1], the mood really became one of wondering whether HBF is going to become the standard. In other words, to organize it again, two hyperscalers that design their own AI chips, namely Google and Meta, are now in a state of having put their names on a NAND-based memory standard.

What HBF is, I covered in January in HBF (High Bandwidth Flash) and Optics: The Missing Link in AI Infrastructure, and at that time, it was the article with the best response among the ones I had posted on my Substack.

To say it again in one line, it is a plan to transplant HBM’s stacking formula onto NAND and create a middle tier that is “much wider than SSD and much bigger than HBM.” At that time it was at the level of conference presentations and concepts. Now, a concrete spec document with 512GB capacity, three bandwidth grades from 0.4 to 3.0TB/s, and a UCIe interface is up on OCP [5][6], and it has come to the stage where the company states a schedule: samples in the second half of this year, inference devices in early 2027 [5]. At the Investor Day they went one step further, and it is said that the tape-out of the first HBF die (the state of having finished the design and handed it to the foundry) is complete and customer samples are next year [4].

So the material the market encountered this week is two things. On the surface there are the NAND price cycle, the contract backlog that has grown to the $90 billion range [4], and the Investor Day’s long-term financial targets [2], and below that there is the structural change that “NAND comes out of the storage box and climbs onto the memory bus.” This article intends to deal with the latter. And the question is one.

Everyone says they are stacking NAND, but are they stacking the same thing?

2. Three Meanings of the Word “Stacking”

Before the main body, it would be good to divide the axes first. The news of “stacking NAND” actually has two different questions mixed in it. One is the process question of how to stack and build, and the other is the placement question of where to put the capacity block made that way, relative to the processor. This section is the former question, and the beside, above, and beyond in the title are the latter question.

Starting from the process side, the word “stacking” in the industry right now points to three different processes. The three differ in purpose, and the direction the money flows is also different.

Concept diagram of the three kinds of stacking. Layer stacking, wafer bonding, and package-level TSV stacking compared in one view

The first is layer stacking. It stacks NAND cells vertically inside the die, and the “hundreds-of-layers NAND” we see in the news is all this story. It is said that Samsung V10 has passed 400 layers, Kioxia and Sandisk’s BiCS10 is 332 layers, and Micron G9 is 276 layers [8][9][10]. The purpose is simple. Extracting more bits from the same wafer and lowering the cost. It is the economics of storage devices, and it is a game that every NAND company is playing without exception.

The second is wafer bonding. It is a method of making the NAND cell array wafer and the peripheral circuit (CMOS) wafer separately, then attaching them whole to complete one die. Kioxia and Sandisk went first under the name CBA [9], and Samsung also announced that it is joining this column from V10 under the name BV-NAND [8]. Up to here, it is still a story about “how to make one die well.” Density increases and I/O gets faster, but the completed die still sits behind the SSD controller, behind the serial passage called PCIe.

The third is HBF. It is a structure that threads multiple completed NAND dies with TSV (Through-Silicon Via, vertical wiring that penetrates the die) like HBM, puts them on a logic base die, and connects them directly with a wide parallel bus from the seat beside the processor [5][6]. The first spec is 8-high or 16-high stacking, up to 512GB per stack, and bandwidth from 0.4 to 3.0TB/s depending on grade [6]. If the previous two stackings are the game of “cheaper,” this one is the game of “wider.” Since it is a matter of changing the interface itself from the storage kind (serial PCIe) to the memory kind (parallel wide bus), I see only this third one as a stacking of a different nature.

But here, one placement question cuts in ahead of time. It is the option of moving the stacking position onto the processor entirely. The zHBM that Samsung unveiled at FMS 2026 is a concept that stacks not NAND flash memory but HBM vertically right on top of the accelerator, and by the company’s claims, it speaks of 8 times the performance of HBM5 and more than 10 times the density [8]. Let me clearly attach the maturity label that it is still at the concept model stage. It is not a product, not a confirmed roadmap, and the figures are vendor claims. Still, the direction itself needs a serious look, because as covered in July in TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM, Samsung keeps digging into the real estate problem inside the package from different angles. And that makes sense, because Samsung is a vertically integrated semiconductor company that can optimize the processor, memory, HBM, photonics, and process together, so it may well be making various attempts. I also think this point is their strength.

Concept diagram of the zHBM structure from the Samsung newsroom. A cross-section with the HBM stack placed on top of the processor

That was long, so to organize it a little: the layer-count competition and the bonding transition are the stacking of cost, HBF is the stacking of bandwidth, and zHBM is the stacking of position. The reason investors must not lump the three into one word is, as we will see later, that the physical limits each one hits are different.

3. Micron’s Public Stance and the Careers Site

Now it is Micron’s turn. In fact, Micron is not a member of the HBF consortium [7]. The award it received at FMS 2026 is also said to have been on the 245TB-class data center SSD side [11]. In early August at the Technology Leadership Forum, the remarks of CBO Sumit Sadana also stop at the level of “when DRAM is insufficient, KV cache spills over to the NAND side” [12].

To summarize, the Micron on public stages concentrates its firepower on HBM4 and sells NAND as fast SSDs. It stacks, but in the first and second meanings of stacking, that is, the stacking of cost.

Then is Micron really keeping its hands off the third game?

Actually, in January this year I made an inquiry to an acquaintance, and since it seemed difficult to talk in a public place about the answer I heard privately, only now have I found public materials and come to make it public.

If you open the careers site, the answer comes out somewhat different.

This part took some time to confirm. Nothing came up in news searches, so I went through Micron’s recruiting system directly, keyword by keyword, and the word “HBF” is 0 cases in all postings. Instead, two postings from the NAND design organization (NVEG) in Tokyo were caught. One was posted in April, one in July, a hiring that has continued for four months [13][14], and since postings can come down, I saved the originals as captures.

Please look at the highlighted phrase in the capture below. What structure of NAND this posting is hiring for, and why I crossed over to the optics-side conclusion after seeing it, is the content of the paid section.

Original Micron Tokyo NVEG job posting.

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TL;DR

• Coherent’s FQ4 2026 revenue, released after the close on August 12, came in at $2.05B. That lands almost exactly at the top of the guidance range given three months ago, and non-GAAP EPS of $1.74 went past the top end ($1.72) [1].

• Guidance for the next quarter is $2.2B to $2.4B in revenue, roughly +12% QoQ at the midpoint. And yet the stock, up nearly 9% in the session right before the release on the 12th, gave the entire rally back with an 8% drop on the 13th, the first trading day after [1][3].

• My read is this. The real news from this call is between the lines of the transcript. Where the bottleneck has moved, what six-inch does to margins, and what the company is worried about instead of demand. The direction is in the body.

Contents

1. August 12: A Top-of-the-Guide Quarter and a Post-Earnings Reversal

2. The constraint has already moved upstream from the module

3. Six-inch InP is a capacity story and a margin story at the same time

4. (Paywall) What kind of debate is CPO versus NPO for Coherent?

5. How far up the network does OCS go?

6. What does Coherent sell into scale-across?

7. What the FY27 order book says

8. Where to check the return on CapEx

9. Checking the Last Call: The Six Items I Flagged in May

10. Conclusion: These Dates Will Do the Judging

1. August 12: A Top-of-the-Guide Quarter and a Post-Earnings Reversal

Results touched the top of the guide, EPS went through it, and the stock still fell 8% the next day. That is this Coherent quarter in one line.

Coherent reported FQ4 2026 results (quarter ended June 30) after the close on August 12. Revenue came in at $2.05B, up 34% year over year on a reported basis [1]. The guidance range the company had given three months earlier was $1.91B to $2.05B, so this lands almost exactly at the top end. I go through the item-by-item guidance comparison in section 9.

Profitability came along with it. Non-GAAP gross margin of 40.2%, EPS of $1.74 up 74% year over year, and for the full year, FY2026 revenue of $7.12B at +22.5% [1]. The segment mix tells you where this growth comes from: Datacenter & Communications did $1.6B-plus in Q4, up close to 60% year over year and now around 80% of the total, while Industrial slipped backward to the $430M level [1]. The AI data center side is carrying the whole company.

Quarterly revenue and non-GAAP gross margin from FQ4 2025 through FQ1 2027 guidance

Guidance is strong too. FQ1 2027 revenue of $2.2B to $2.4B, non-GAAP gross margin of 39.5-41.5%, EPS of $1.85-2.05 [1]. At the midpoint, that is another quarter of 12%-plus sequential growth.

And yet the stock moved in an interesting way. Shares rose nearly 9% to around $356 in the regular session on August 12, right before the release, then closed the first post-earnings session on the 13th down 8% at $327.23, giving the entire rally back (as of the 2026-08-13 close) [3]. After touching the top of the guide and calling for another quarter of double-digit growth, why did it fall? There are about three candidates. Expectations already loaded into a stock trading at close to four times its 52-week low [3], the cash burden of an aggressive buildout, or simply a bar that had formed above the guidance. The second candidate is one you can check directly against the CapEx and cash-flow numbers later in this piece.

The public takeaway was just one thing, the InP bottleneck. But reading the transcript from start to finish, this call carries a few bigger changes underneath. And the gap between the headline numbers and the post-earnings reaction is filled by exactly these lines between the lines. So here they are.

2. The constraint has already moved upstream from the module

On this call, Coherent stated flatly that transceiver assembly and test capacity are not constraints today. The biggest constraint is InP production [2].

Honestly, this is where I paused. It was hard to agree with, and it made me think twice. I have long viewed test as the single biggest bottleneck in optical devices. I have published quite a few articles on test (The 100-Second Bottleneck Behind NVIDIA CPO: 7 Companies That Own the 4-Stage Test Stack, The Three Pillars of SiPh Wafer Test: What AEHR, FORM, and KEYS Actually Do), and I hold quite a few of the related stocks too. Why PIC test is harder than EIC test, and how large its share is at the package level, is something I also touched on in [PC101] Lecture 4: The Last Millimeter: Who Builds It. CPO Packaging Value Chain and Next-Gen Applications (Part 2). So why did Coherent point at InP, and specifically production, instead of test?

I still think InP is critical and close to irreplaceable. But here is how I read that line: the InP bottleneck right now is simply that severe.

The numbers back it up. June-quarter InP laser output grew about 80% year over year, and the company’s own 800G and 1.6T transceiver demand is effectively absorbing all of it [2]. Everything made goes straight into its own modules, which is why the optical supply chain’s scarcity is getting harder to understand by counting transceiver units. You have to look past module assembly to EMLs, CW lasers, and below them, InP wafer and substrate capacity.

And this is not just Coherent’s story. On the Lumentum call the day before Coherent’s report, the same direction showed up: EMLs are still shipping behind demand, and on high-power lasers supply has fallen even further behind as demand accelerated [7]. Two reports one day apart are pointing at the same upstream layer. I put the Lumentum side together separately in Lumentum’s First $1B Quarter: FQ4 2026 Earnings Analysis.

I went deeper into that upstream bottleneck recently in AXT and Lumentum’s Prepayment Deal: The InP Substrate LTA Chain. Expanding fab capacity and securing InP substrate you can actually use are two different problems.

3. Six-inch InP is a capacity story and a margin story at the same time

Coherent’s move to six-inch is not only about a bigger wafer adding production capacity. The CFO’s phrasing was clear.

“Four times, but it’s at half the cost.” [2]

Spelled out, a six-inch wafer yields about four times as many devices as three-inch, at around half the cost per device [2]. The more interesting part is that yields for EMLs, CW lasers, and photodiodes are all already higher on six-inch than on three-inch [2]. Normally, when you move to a larger wafer diameter you lose yield first before you gain anything, and this line says they are already past that stage. So as InP capacity grows, transceiver shipments can rise while the cost of the most critical component inside them comes down at the same time.

I had already flagged this as a core monitoring point in the previous-quarter piece, $20B+ New SAM on Top of +27% Pro Forma Revenue: The Quarter Coherent Crossed from Transceiver Player to Platform, and this call made the six-inch margin thesis considerably sharper than back then. In other words, in this cycle, volume growth and margin expansion do not necessarily have to move in opposite directions.

That is the supply side of the transcript. What stayed with me longer, though, were the demand-side lines: the company’s answer to the market’s CPO-delay worry, and the CEO’s description of the FY27 order book. If the next day’s 8% drop missed something, it is probably here.

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TL;DR

• Lumentum’s FQ4 2026 revenue, announced after the market close on August 11, came in at $1,006.3M. Quarterly revenue crossed $1B for the first time, up 24.5% from the prior quarter and a striking 109.3% from a year ago [1].

• The same quarter shows a GAAP net loss of $7.2B, but the source of this loss sits outside operations. The cause is a one-time, non-cash accounting loss of $7.8B from converting convertible notes into stock, and I walk through it in the body [1][2].

• Non-GAAP operating margin of 36.6%. While revenue doubled, operating margin rose 2,160bps year over year. Next quarter’s guidance calls for $1.25B revenue at the midpoint and a 39.5-40.5% operating margin, arriving at the target model the company laid out at OFC more than a quarter early [1][2].

• Here is my lead. I think the real news this quarter is less the revenue figure and more the five signals mentioned alongside transceivers. What those signals are, and why they change the very size of the market Lumentum can address, is laid out in the body.

Contents

1. August 11, the First $1B Quarter

2. What the $7.2B Loss Really Is

3. Where These Orders Come From

4. Segment Breakdown: Both Sides Ran Together

5. Five Signals: Optics Moving Into the Rack

6. Guidance Check: What a 40% Operating Margin Implies

7. Prior-Call Review: The AXT LTA and the Supply Gap

8. Conclusion: These Dates Will Decide

1. August 11, the First $1B Quarter

Lumentum reported FQ4 2026 results (quarter ended June 27) after the market close on August 11. Revenue was $1,006.3M, up 24.5% QoQ and up 109.3% YoY [1]. A year ago this company’s quarterly revenue was $480.7M, so revenue has more than doubled in four seasons.

You may wonder whether this growth is a one-off jump. Borrowing the language from the call, this is the eighth consecutive quarter of revenue growth, and counting only quarters with more than 20% sequential growth, it is the third in a row [2]. The comparison base keeps getting bigger, and the growth rate is holding anyway. Back in May I covered the $808M quarter in The 8 Companies Behind Lumentum’s $808M Quarter: Why Beta Splits by Orders of Magnitude Across the InP Cycle, and just one quarter later another $200M has been stacked on top. As a growth rate, that is an enormous number.

The profitability numbers actually catch my eye more. Non-GAAP gross margin came in at 50.4%, crossing 50% for the first time. The company reportedly planned to cross this threshold at around $2B in quarterly revenue, and it got there first at half that revenue [2]. Operating margin was 36.6%, an expansion of 440bps QoQ and 2,160bps YoY [1]. While revenue doubled, operating expenses stayed pinned at 13.7% of revenue [2], so this is a zone where added revenue drops almost straight through to profit. When operating leverage works the way the textbook says, this is the picture you get.

The stock reaction was, unexpectedly, on the calm side. The August 11 regular session closed at $820.59 (+0.87%), and after the release the stock was up around 2% after hours (as of 2026-08-11, including after hours) [3]. Market cap is $63.8B, and the 52-week range runs from $111.20 to $1,085.68, so even after printing these results the stock still sits more than 20% below its 52-week high [3]. As it happens, the optics-only ETF LYTE listed five days before these results [4], and LAZR had already arrived in late June [5]. I suppose that means the market’s eyes have reached this layer, enough for optics to become a standalone theme product.

But one of the headline numbers probably snagged your eye. A GAAP net loss of $7.2B. What does it mean that a $1B-revenue company lost more than $7B in a quarter?

2. What the $7.2B Loss Really Is

To put the conclusion first, this loss involved no cash leaving the company, and it does not mean the business rolled over. It is an accounting loss created by the stock rising sharply over the past year.

Here is what happened, in order. Lumentum had issued convertible notes some time ago. A convertible note is borrowed money, but in the form of a bond the holder can swap into stock at a preset price if they choose. Over the past year, with the stock up severalfold, the value of that conversion option grew. This quarter the company proactively converted a portion of these notes into stock (equitization), and as a result $1.1B of debt was erased from the books. That is about 35% of the convertible notes that were outstanding [2].

Here is why an accounting loss shows up.

On the books this debt is recorded at the amount borrowed, but the market value of the shares handed over in repayment is far larger, by as much as the stock has risen. Accounting books that difference as a loss on debt extinguishment. This quarter that amount was $7.8B, which is how the $7.2B GAAP net loss came about [1][2].

As a rough analogy, it is like borrowing the price of rice while promising “you can take our field as repayment,” and in the meantime the field’s value has gone up severalfold. The moment you repay with the field, a big loss prints on the books, but the cause of that loss is the field’s value, that is, the company’s value, having risen in the first place. So I read this $7.2B as closer to a footnote than a worry. Actual quarterly profitability is told by the non-GAAP side: net income of $326.3M, or $3.23 per share [1].

There is one thing to add. Since debt was swapped into stock, dilution for existing shareholders is real, and unlike the one-time accounting number, it stays. That said, interest-bearing debt did shrink, so I lean toward seeing this as a sensible trade: cleaning up debt while the stock is high.

3. Where These Orders Come From

So where does the demand that doubled revenue come from?

The starting point is hyperscaler spending. I covered the capex upgrade trend confirmed in the big four’s late-July results in The GPU Repricing Cycle and Q2 Hyperscaler Earnings: Which Hardware Layer the Capex Flows To, and when that money goes into a data center, a network linking the GPUs to each other always goes in right beside them, and the physical layer of that network is optics. The transceivers that turn the signals running between GPUs and switches into light and carry them, the InP laser chips inside them that make that light, and the pump lasers in the long-haul links connecting data centers to each other: as it happens, all of it is on this company’s product list.

One anecdote from this call captures the scale of this demand well.

For one major hyperscaler, the network capacity connecting two AI data center sites is reportedly double the entire global backbone that company laid over the past decade [2]. A line connecting ‘just two sites.’ The picture is training and inference splitting across multiple sites and inter-site traffic growing, and thanks to that, pump lasers for long-haul links are effectively sold out even after shipments grew more than 80% year over year, and the company plans to quadruple shipments over the next several quarters [2].

I actually found this part interesting and mentioned it in the subscriber-only chat as one of the seven things I was watching.

This flow itself is not a new story. In fact, together with Aurelion Research, I had already handed you a big hint. In July’s A Conversation with Lumentum, which recorded a conversation with Lumentum IR, we had already heard that EML capacity was up eightfold in two and a half years and still could not keep up with demand, and these results are close to the first quarterly closing where those words print as numbers.

Reading the CEO comment, though, I get the impression that what the company really wants to emphasize is not the products selling today. The CEO paragraph of the press release strings together words that are probably a bit unfamiliar: OCS, 1.6T, ultra-high-power CPO lasers, a first ELS module order, and NPO. Five of them packed into one paragraph, and the concluding sentence is that “optics are starting to penetrate in-rack connectivity” [1].

Why is a company that sells transceivers talking about the inside of the rack? And why is the simultaneous appearance of these five words the real news of the quarter?

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Abstract

The Trump administration suddenly came out saying it would block Chinese transceivers. In the early hours of August 4, Reuters reported the FCC’s import ban draft, and communities everywhere got excited. And as you’d expect, US optical stocks rose double digits intraday. In the market, an interpretation was going around that AXTI gets hurt if China retaliates, and I think that’s a one-dimensional reading. Then a few days later, commentators like Jukan, separately from this news, started talking about a short-term short memory, long optical trade based on NVIDIA’s roadmap, so regulation and architecture are pointing at optics for different reasons. This article checks the disclosure documents of Innolight, which raised $6.8B five days earlier, to see how much of its volume is actually US-bound, and works down through capacity and the InP substrate chain to ask whether US-made supply can absorb that demand. To note my direction up front, I think the essence of this regulation is that it exposes the fact that without transceivers, even the US cannot build AI data centers.

Contents

1. A Draft Out of Nowhere

2. The $6.8B Five Days Earlier

3. The US-Bound Volume in the Disclosures

4. A One-Line Fight over the Text: Nationality or Origin (Paywall)

5. Can US-Made Supply Absorb the Demand

6. Going Down to InP: AXTI

7. Can You Build an AIDC Without Transceivers

1. A Draft Out of Nowhere

The Trump administration suddenly came out saying it would block Chinese transceivers. It was a Reuters exclusive on the morning of August 4 (US time): the FCC is drafting an import ban on Chinese data center equipment including new Chinese optical transceivers, aiming for publication within the year and immediate effect [1]. The stated grounds are concerns over data theft, malware, and remote service disruption. I remember people getting very excited. Especially on X, saying that because of the FCC event, US optics-related stocks, for example AAOI, COHR, LITE, would be the beneficiaries.

Reuters exclusive headline, FCC drafting ban on Chinese data center devices, 2026-08-04

Let me start with the market reaction. AAOI rose around 20% intraday, Coherent and Lumentum double digits, and Corning around 8% (intraday figures that vary by when you sampled them) [2]. The Chinese side reacted a day late since the report came out after their market close: on August 5, Innolight’s A-shares fell as much as 16% intraday before closing down 7%, the H-shares fell 5.2%, and the next day they bounced right back to near record highs. The swings continued after that, and on August 10, the same day as a broad optics pullback ahead of earnings season, it closed down 6.9% at HK$1,033. Still 5% above the offer price [3].

And there was one more interpretation people attached to this news. That if China retaliates by squeezing InP exports, AXTI, which makes substrates in China, gets hurt. I think this is a one-dimensional reading, and why becomes visible only once you go down the InP chain, so I’ll write about it later.

What to look at first is the company that is number one in the transceiver industry and sits right in the middle of the ban’s target. This company, of all times, had just raised money in Hong Kong five days earlier.

2. The $6.8B Five Days Earlier

A few days before the FCC event, on July 30, Zhongji Innolight listed its H-shares in Hong Kong. At an offer price of HK$980, it raised HK$53.4 billion (about $6.8B), the largest in Hong Kong since Alibaba in 2019 [4][5]. The Hong Kong retail tranche was 16.8x subscribed and the international tranche 9.7x, and 33 cornerstone investors including Temasek, ADIA, BlackRock, Alibaba, and Tencent took half of the offering (about HK$26.7 billion worth) under a six-month lock-up [4][5].

The ten days around the listing were noisy in the headlines. When the offer price printed around 11% below the A-shares (per press reports), the A-shares plunged 15.7% on the pricing disclosure day [6][7], and on debut day, sitting on top of a chip selloff week, the stock fell as much as 9.8% intraday before closing 2% below the offer price [8][3]. But look at the closing-price chart and there is no stretch you could call a crash. It recovered the offer price the next day, and through the swings since, it sits at HK$1,033, 5% above the offer price even as of the August 10 close [3]. One fact remains. The world’s largest optical module company is holding net proceeds of HK$52.9 billion [5].

How they should use this money, honestly, is the part I’m most curious about. The uses listed in the prospectus are R&D, overseas production capacity expansion, supply chain strengthening, M&A, and general working capital [9]. Five items, and where the weight lands is open, and the FCC draft that came five days later added a variable to that answer. The meaning of the overseas capacity item now changes completely depending on the regulatory text.

Figure: Four forces on the debut day

3. The US-Bound Volume in the Disclosures

Look at the disclosures and quite a lot is US-bound. US customer revenue was 75.9% in 2023, 57.3% in 2025, and 61.7% in Q1 2026 [9]. Overseas revenue overall is above 90% as of Q1. So this is a Chinese company where 60% of revenue comes from the US. This is exactly where the FCC draft is aiming.

But the same disclosures carry numbers pointing the other way. Goods made in mainland China and sold to the US were under 1% of total revenue throughout the track record period. By year: 0.3%, 0.9%, 0.2%, and 0.0% in Q1 2026 [9]. Which means the US-bound volume has effectively already been moved entirely to offshore production. The Singapore entity TeraHop Pte is the hub of overseas production, and the main base for North America-bound goods is Thailand [9][10]. The way Chinese vendors have been adding capacity in Thailand and Indonesia is exactly the layout we covered in April in Chinese Optical Modules Own 7 of the Top 10 Seats.

US revenue is 60%, but mainland-origin US-bound is around 0%. The gap between these two numbers decides the entire effectiveness of this regulation. As the optical communications research firm Cignal AI pointed out, the draft does not yet have a definition of “Chinese” [10]. Do you look at the company’s nationality, or the place of production. The question Cignal posed compresses this ambiguity. Is a module that combines Marvell’s DSP and Lumentum’s optics, assembled in Malaysia, Chinese [10]?

Why does the definition matter this much: because the same module from the same company is a legal import under one criterion and a banned item under the other. Unlike routers or drones, transceivers sit on a layout that a definition clause is perfectly positioned to split: the top suppliers are Chinese by nationality and Southeast Asian by production. One sentence in the Federal Register will decide whether billions of dollars of volume crosses the border.

Prospectus, origin of US-bound shipments and regional revenue pages, 2026-07-22

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SpaceX, the name that ran so hot, has put out its first earnings since going public. Back in June I read the S-1 and wrote a piece breaking the company down layer by layer, and watching this release, I wanted to pull that piece back out and check it against what I had published. The first quarterly filing carries the judgments I had built on the IPO documents, and it is the first material that lets me check how well my thinking actually held up, so I thought it mattered. And if the 10GW compute outlook from this earnings call becomes real, I thought it also matters which side of data center investment we should be looking from. So this piece runs in two parts. The front half is the work of reviewing the judgments made at S-1 time against the first earnings, and in the back half I try to follow the feasibility of the 10GW outlook and the hardware layers that money will flow into. To note just the direction up front, I read this report less as a space company’s earnings and more as the first quarterly report of an AI infrastructure company, and I expect the benefit to arrive first not at SpaceX shareholders but at the ones receiving the parts orders, or the investors around them.

Contents

1. Quarterly Capex of $18.4B, With $15.8B Going to AI

2. Revisiting the S-1, Part 1: Connectivity, the ARPU Decline Has Stopped

3. Revisiting the S-1, Part 2: Space, Seven in Ten Launches Were Internal

4. Revisiting the S-1, Part 3: The AI Segment and the 90-Day Termination Call

5. Rereading the 90-Day Termination Clause: Weakness or Sales Condition

6. Is 10GW Real: Power, Money, Skepticism

7. The Hardware Bill: Power, Optics, and Scale-Across

8. Conclusion, and What Would Prove Me Wrong

1. Quarterly Capex of $18.4B, With $15.8B Going to AI

SpaceX’s capex this quarter was $18.4B, and the AI segment’s share of it was a whopping $15.8B [1]. That works out to 86%, and is that a high number or a low one, what would the answer be? Yes, as you probably guessed, it is quite high. A company that builds rockets and satellites put nearly nine tenths of its quarterly investment into AI data centers.

The August 4 release was the first earnings since the red-hot June 12 listing. Revenue came in at $7.8B, up 92% year over year, net loss narrowed to $541M, about half the level of a year ago, and Adjusted EBITDA was $3.5B [1]. Even with revenue beating estimates by nearly $1B, the stock reportedly slid around 8% after hours [2]. The capex caught the eye before the surprise did. It is the same reaction pattern as the four hyperscaler earnings in late July.

Segment results table from the SpaceX Q2 2026 press release

And on the call, Musk named the destination of that capex. Past 2GW of compute by the end of 2026, and by the end of 2027, to a level closer to 10GW than to 5GW [3]. This from a company at 1.4GW nameplate today [1].

There are two things I want to do in this piece today. One is to review the layer-by-layer judgments built on the S-1 in June’s The Largest IPO in History, One Profitable Layer: Where SpaceX Exposure Really Sits, and the Traps against the first earnings. The other is which hardware layer gets the attention if that 10GW number becomes real, or which one we should be paying attention to.

2. Revisiting the S-1, Part 1: Connectivity, the ARPU Decline Has Stopped

In the June piece I classified Starlink as SpaceX’s only profitable engine, while also writing down as a risk the pricing pressure that had pushed ARPU from $99 to $81 on an annual basis, and down to $66 on a quarterly basis.

Layering the first earnings on top of that, it looks like this. Connectivity revenue was $4.3B, up 66% year over year, operating income $1.7B, up 79%, and subscribers doubled in a year to 12 million [1]. And ARPU held at $66, flat with the prior quarter [1]. There was reporting in May of an attempted price increase, and at least this quarter, the picture that came out was doubling subscribers while thankfully holding the unit price. There is also a side growing faster than consumer. Enterprise & Government revenue grew 108% year over year, and the filing also includes over $6B in multi-year US government contracts won through Starshield [1].

The result of a quick review is that I keep the judgment that the company still has its profitable engine. That said, the decline stopping and the price rising again are different stories. That it stopped at $66 is as far as this quarter’s facts go, and whether this price increase actually shows up in ARPU has to be checked precisely against next quarter’s numbers.

3. Revisiting the S-1, Part 2: Space, Seven in Ten Launches Were Internal

The S-1 contained the language that “to meet our orbital compute goals, we may prioritize our own payloads ahead of US government contracts or third-party customers” [4]. At the time I wrote, based on that language, that the upside for outside listed names in the launch layer was narrow. The first quarter’s numbers show that language in action. Of 38 launches in the quarter, 28 were internal, and of 485 metric tons put into orbit, nearly 400 tons were internal payloads [1]. More than seven in ten launches went to lifting its own satellites, that is, Starlink satellites.

Space revenue grew 29% year over year to $962M, yet the operating loss was $542M [1]. Starship R&D is booked at around $1.1B for the quarter. Flight 12 in May and Flight 13 in July hit their objectives back to back, and Flight 13 reportedly went as far as deploying 20 production V3 satellites [1], so the nature of this loss is closer to deployment speed than failure cost. There is nothing to change in the June judgment on the launch layer.

4. Revisiting the S-1, Part 3: The AI Segment and the 90-Day Termination Call

Now for the main part of this piece. In the June piece I attached a warning to the AI revenue line. The Anthropic contract at $1.25B a month and the Google contract at $920M a month sit at the center of the AI revenue story, but both can be ended on 90 days’ notice, so the headline contract sizes should not be taken at face value. That was the warning [4][5].

In the first earnings, AI revenue was $2.56B, 3.5x year over year. Of that, AI solutions & infrastructure was $2.19B, up more than 4x in a single quarter from $475M [1]. The Anthropic ramp was scheduled across May and June, so the timing lines up. Compute capacity stood at 1.4GW nameplate, up from 1.0GW the prior quarter [1].

But what caught my eye first in this filing was not the revenue number but a definition tucked into the back of the release. SpaceX announced the Cloud Services Agreements newly signed this quarter as $14.1B in contracted sales, and in Note 2 it spelled out how it counts that number. It does not count the full amount written into the contract, only the revenue from the period that cannot be cancelled [1]. Meaning that for a contract that can be ended on 90 days’ notice, even if three years of value is written on paper, only the non-cancellable first few months land in contracted sales. The $45B and $30B deal values the press quotes add up the entire contract term, while the number the company officially tallies counts only the locked-in piece. This is exactly the point I made in June. That as long as the 90-day clause is there, the headline totals should not be taken at face value. With this filing, the company effectively discounted the number that way itself.

Contracted sales definition language in Note 2 of the press release

Up to this point, you could say PhotonCap’s June call was more or less right. But there is a flipped half to this observation. That the 90-day clause may be, rather than a weakness, the very condition that makes this business sell so well. That is where we pick up below.

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Abstract

It is already early August, but to look back and think about AI infrastructure investment and the outlook going forward, I went through the hyperscaler earnings from the last week of July, pulled together commentary from various outlets and X, and prepared my own opinion and analysis alongside it. Alphabet, Microsoft, Amazon, and Meta earnings were all packed into the last week of July. I started writing this piece after seeing the Google Cloud +82% number, and as I wrote, it seems half of the piece turned into checking the underearning story Gavin Baker raised first, that is, the observation that GPU spot rental prices are more than 2x contracted prices, against this quarter’s results. The other half is redrawing and checking the cloud capex hardware map I drew in May with data one quarter later. To note just the direction up front, I see this quarter as the early stage where the supply shortage starts getting reflected in prices, and I suspect the place where that money stays longest is the two layers hyperscalers cannot insource.

Contents

1. Backlog at $514B, but the Stock Fell

2. When the Lease Runs Out: Baker’s Underearning Thesis

3. The Four Hyperscalers’ Results: The Numbers

4. The Boundary Public Materials Can Show

5. Primary Evidence of Repricing: Usage Above Commitments and Backlog Quality

6. The Meta Compute Variable

7. May Map Update: Allocation Tilting Toward L3 and L4

8. As Efficiency Improves, the Bill Grows

9. Conclusion, and the Conditions Under Which I’m Wrong

1. Backlog at $514B, but the Stock Fell

In Alphabet’s July 22 earnings, Google Cloud revenue was $24.77B, up +82% year over year [1]. The prior quarter’s growth rate was +63%, so it got even steeper in a single quarter. A company this large accelerating its revenue growth struck me as worth paying attention to. The backlog, contracted but not yet recognized as revenue, stands at $514B, up more than $50B in one quarter [1]. And yet the stock reacted to the earnings release by falling. The company raised capex guidance again, and quarterly free cash flow flipped negative [1].

To borrow the news framing, the books and the stock went in opposite directions.

This combination is the key question of this earnings season. Record demand is piling up on the books, while the market looks first at “the cash being burned to serve that demand.” Which of the two is the right lens?

So the points I want to discuss in this piece come down to two. One is whether the underearning thesis, that hyperscalers are currently selling compute below market rates, is supported by actual earnings data. The other is, if so, which hardware layer the growing cash flow and capex flow into.

2. When the Lease Runs Out: Baker’s Underearning Thesis

The starting point of this piece is the argument Gavin Baker of Atreides Management laid out in a recent X post and in his Invest Like the Best interview back in May [2][3][4]. The problem statement is his, and in this piece I put my own thinking alongside it and check that argument against this quarter’s primary data.

“TL;DR Spot pricing for renting GPU compute materially above contracted rates implies hyperscalers are underearning while operating cash flow acceleration is an underestimated source of funds for AI capex.”

…

“As contracts roll-off, hyperscale growth rates are going to continue to accelerate as their installed bases of compute reprice higher.”

…

“Hyperscalers are underearning and anyone who signed a contract for GPU compute in 2024 and 2025 is overearning. Operating cash flow will be enough to fund capex but as contracts reprice and cloud growth continues to accelerate then spreads likely come in as well.”

The market may be overreacting to widening hyperscaler credit spreads.

If spot GPU rental prices are at least twice contracted rates, hyperscalers are likely underearning relative to the current value of their installed compute. As older contracts roll off and reprice higher, cloud revenue and operating cash flow could accelerate faster than consensus expects, allowing a much larger portion of future AI capex to be funded internally rather than through debt.

• Customers that locked in GPU compute during 2024 and 2025 are currently overearning
• Contract repricing could reaccelerate hyperscaler growth and operating cash flow
• The real constraint may be power and data-center execution, not access to credit

The more important question may not be whether hyperscalers can finance AI infrastructure, but how quickly they can energize the GPUs and convert that capacity into revenue.

The argument goes like this. The price of renting GPU compute on the spot market, that is, on demand without a contract, is at least 2x the long-term contracted price [2]. Since most hyperscaler revenue comes from long-term contracts signed some time ago, they are effectively selling compute for less than half of what they could charge at today’s rates. Baker calls this underearning, meaning earning less than they could.

Think of a rent-stabilized apartment and the structure clicks. During the lease term, no matter how much market rent rises, what the landlord collects is fixed. If market rent doubles, the landlord gets upset, but there is nothing they can do until the lease ends. Instead, when renewal time comes, the accumulated rise in market rates gets reflected all at once. Or the landlord is expected to raise the price. Baker’s claim is that hyperscalers are now landlords sitting on rent-stabilized leases, and the renewal cycle has slowly started to come around.

Contracted rate vs spot rate repricing concept

So his conclusion follows from there. As existing contracts expire and renew at new prices, the hyperscalers’ entire installed base reprices upward, and growth does not just hold, it accelerates. In fact, multiple private companies are reportedly planning to pay more than 2x per GPU after their contracts expire [2]. He modeled combined hyperscaler operating cash flow growth accelerating from 31% in Q1 to 50% in Q2 [2], and this figure is not a measurement but a calculation mixing his estimates with reported results. Of course, I have not been able to recalculate this model, but I looked for a way to verify the direction and checked whether that direction actually holds. I figured we could just look at whether traces of repricing actually showed up in this quarter’s results.

3. The Four Hyperscalers’ Results: The Numbers

I summarized everything below based on company announcements.

Alphabet (7/22): Total revenue $119.8B, +24%. Google Cloud $24.77B, +82%, beating consensus by more than $2B. Cloud operating income was $8.8B, about three times a year ago. Backlog $514B, with just over half expected to be recognized as revenue within 24 months [1].

Microsoft (7/29): FY26 Q4 revenue $90B, +18%. Azure +43%, with Azure annual revenue crossing $100B for the first time on a fiscal-year basis (+41%). Commercial RPO $678B [5]. Quarterly capex including finance leases was $41B, +69%, and FY2027 capex guidance was reportedly set at $255~260B [6].

Amazon (7/30): Total revenue $200.6B, +20%. AWS $42.2B, +37%, the fastest growth in 18 quarters, with a 39.4% operating margin. The AI business and the in-house chip business each run above $25B annualized [7]. The 2026 capex outlook was raised from about $200B to about $220B [8].

Meta (7/29): Revenue $60.8B, +28%, beating consensus, with an EPS miss. Full-year capex guidance is $130-145B, narrowed from the prior $125-145B by raising the lower end [9]. The lower end is how they showed they have no intention of cutting. AI infrastructure spend was around $31B in this quarter alone, and free cash flow pressure was the theme of the earnings call [10].

Put the four announcements side by side, and cloud revenue growth is accelerating at all three clouds while all four companies raised capex. Two of them saw their stocks slide on cash flow concerns. (In my view, that makes no sense.) You can read this as a picture where the sellers’ growth is speeding up while the buyers’ spending speeds up at the same time. In a market with surplus supply, I doubt these two would show up together.

That ran long, so to sort it out a bit: the premise of Baker’s thesis, that demand exceeds supply and contracted prices lag market rates, and the shape of the four companies’ numbers this quarter show no contradiction anywhere.

Up to this point, this is an extension of what I wrote on May 11 in The Real Beneficiaries of Azure +40%, AWS +28%, GCP +63%: The Hardware Supply Chain Map Behind $580B in Cloud Capex. That piece drew the map of $580B in combined capex flowing into four hardware layers, and one quarter later, every one of those premise numbers has been revised upward.

4. The Boundary Public Materials Can Show

This is as far as public earnings releases and Baker’s public claims can take us. But to use this in investment decisions, there is more that needs checking.

First, whether there is evidence inside the results that repricing has already started rather than being something still to come. As it happens, two candidate pieces of evidence surfaced this quarter. One came out of Google’s earnings call, and the other is the difference in composition across the three companies’ backlogs. The backlogs of $514B, $638B, and $678B are all huge numbers that look like the same unit, but open them up and the contracts inside are different in character.

RPO paragraphs from the Oracle FY26 Q4 release

The other question is where the benefit of that repricing prints larger, in hyperscaler stocks themselves or in some hardware layer. There is a hint in the Oracle paragraphs captured above. The portion where customers prepaid for GPUs or bought and supplied them directly amounts to $75B [11], which means compute buyers have started taking on hardware procurement themselves. Why this paragraph matters is unpacked behind the paywall together with backlog quality.

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People often discuss where the bottlenecks lie. Whether it’s the GPU, memory, or optics. As AI agents gained prominence, the importance of the CPU came to the fore, followed by concerns regarding power supply and land availability. There was also a time when Indium Phosphide (InP) substrates attracted significant attention.

A prime example is AXT, a company that saw tremendous growth this year, with its stock price climbing to around $120. Although the price has recently dropped significantly driven by the Leopold liquidation event and concerns over China-related risks I would like to take a closer look at this stock.

TL;DR

• On July 29, AXT announced a long-term InP substrate supply agreement with Lumentum. A $43.5M deposit lands in cash within a month, another payment of the same size is scheduled for 2028, and capacity is reserved through the end of 2031.

• Lumentum is a company running no fewer than five InP fabs. That means it needs a lot of InP substrates, and this time it decided to buy them prepaid.

• The same week, Lumentum’s CEO said in a public forum that the InP shortage will get worse than what we see in memory. The words and the money came out in the same week.

• To note just the direction up front, I read this contract as evidence of the InP substrate shortage in the optics market, and at the same time I see it as the start button on the cycle clock. The checkpoint dates to monitor, and the reasoning behind them, are laid out one by one later in the piece.

Contents

1. July 29

2. The Structure of the $87M Deposit

3. Who Actually Makes the Substrate

4. The LTA Chain

5. Deposit Economics and the Expansion Race

6. The 1060nm Detour

7. Up and Down the Chain: Layer by Layer

8. Conclusion and the Dates to Check

1. July 29

On July 29, AXT (NASDAQ: AXTI) announced a long-term supply agreement with Lumentum (NASDAQ: LITE) [1]. It covers InP substrates, that is, the indium phosphide wafers that light-emitting laser chips are built on, supplying them through the end of 2031 and reserving a minimum annual capacity for Lumentum. In return, Lumentum pays a $43.5M deposit in cash within 30 business days of signing, and will put in the same amount once more sometime during 2028 [1]. $87M in total.

There was one more statement that came out the same week. Lumentum CEO Michael Hurlston reportedly said on a summit stage in Paris that the InP shortage will become even worse than what the memory side is seeing [2][3]. A number came with it: the gap between demand and supply has widened beyond what was said on the last earnings call, to over 30% [2][3].

Sourcery

BREAKING: Lumentum CEO on How Lasers Are Transforming AI Data Centers

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a month ago · 16 likes · 1 comment

Thank you for sharing, ..

And by coincidence, on the very same day, we ( and ) published a piece summarizing a conversation with Lumentum’s VP of Investor Relations. That content is available for free in A Conversation with Lumentum, and I’ll be bringing its testimony back throughout this article.

The CEO’s words and the company’s money came out in the same week. That is the starting point of this article and the reason I sat down to analyze it.

2. The Structure of the $87M Deposit

Before we get into the contract, it would be good to quickly go over what InP is. Silicon, the protagonist of the semiconductors we know well, CMOS, CPU, GPU, Memory, is hopeless at turning electricity into light. It carries electricity just fine, but its crystal structure leaks the energy away as heat instead of light when it tries to emit.

InP is the opposite: it is a material that converts electricity directly into light, and above all it is practically the only base wafer on which you can stack, defect-free, the lasers and receiver devices for the wavelengths with the lowest loss in optical fiber (1310nm, 1550nm). That is why every optical link in a data center starts on this wafer. As for why neither silicon nor GaAs can take its place, we covered it at length, starting from the material physics, in March’s AXT Inc. (AXTI) Deep Dive: The Hidden Bottleneck in AI Optical Interconnects, so if you need the background, feel free to start with that piece. (The first half is written to be understandable without an engineering degree.)

Now, the contract itself. It is a definitive agreement disclosed via 8-K, meaning a binding contract, not a letter of intent [1]. The two deposits are applied as credits against future shipment payments, so in effect Lumentum is depositing money in advance for the wafers it will buy [1].

It is a contract where the money moves before the goods.

As you well know, there is no reason to do this in a loose supply market. Putting money down first to hold your place, like paying upfront to lock in a purchase, is an action you take exactly when the goods are scarce, or when you believe they will stay scarce. And indeed, Lumentum’s stock slipped after the announcement, and an article ran with a headline calling it a costly supply deal [4]. To be honest, access to that article was blocked and I could not verify the full text, so I am citing it only at the headline level.

That leaves a natural question. Why did a company running five InP fabs have to buy substrates from outside, and prepaid at that?

3. Who Actually Makes the Substrate

Owning fabs and making substrates are different businesses. There is the stage where indium metal, a byproduct of zinc smelting, is grown into single-crystal ingots and sliced thin into substrate wafers; there is epitaxy (the process of depositing crystal layers on the substrate, epi from here on), which stacks the light-emitting layers on that wafer; and then comes the fab, which processes it into laser chips. What Lumentum owns five of is only the last stage. In other words, it has no wafers of its own.

And the substrate companies in the earlier stage are few in the entire world. Japan’s Sumitomo Electric, US-listed AXT, and Japan’s JX Advanced Metals are known to hold most of the world’s supply (we analyzed this down to the supply chain in AXT Inc. (AXTI) Deep Dive: The Hidden Bottleneck in AI Optical Interconnects) [5].

There is a good reason why there are so few substrate manufacturers: InP (indium phosphide) single crystals are notoriously difficult to grow. Because the phosphorus (P) component tends to vaporize and escape near the melting point, high pressure must be maintained throughout the growth process to prevent its loss. Furthermore, the finished crystals are more brittle than silicon. That’s why, while silicon wafers transitioned to 12-inch sizes long ago, InP wafers are still primarily produced in 2- to 4-inch formats, with mass production of 6-inch products only just beginning. The know-how required to produce usable wafers is embedded in decades of accumulated process data, making this a sector that new entrants cannot easily penetrate simply by injecting capital.

The significance of this in the current market cycle is straightforward: there is a long lead time between the announcement of production capacity expansion and the actual shipment of products. Not only does it take time to set up the crystal growth furnaces, but additional time is required to achieve a yield of wafers that meet commercial quality standards. Consequently, these structural characteristics make this stage of the process a frequent source of bottlenecks when demand surges.

Even Coherent, said to be the most deeply vertically integrated among optical players, buys its substrates outside under multi-year contracts and starts from epi in its own fabs [6]. So buying substrates is, in itself, business as usual, and the signal is in how they are being bought. A deposit instead of a purchase order, a six-year reservation instead of spot.

InP value chain layers, from indium metal to laser chip, with the substrate stage highlighted

But here an enormous variable called China comes into the picture. AXT’s production sits in its Beijing subsidiary Tongmei, and since indium-related items are on China’s export control list, every shipment needs a permit. In fact, within the past year there is a track record of one quarter getting crushed by permit delays and then recovering sharply once the permits came through [7].

On top of that, the company has said that data-center-driven InP demand is growing fast inside China as well [7]. With Chinese companies occupying the top ranks of the global optical module market, the same substrates end up contested between Chinese domestic demand and export volumes. China’s optical module market, as those who know it will know, is quite large. We covered it in a free article called Chinese Optical Modules Own 7 of the Top 10 Seats. The fact that the supply line Lumentum just locked in sits inside China’s permit regime is both a condition and a risk of this contract.

In the conversation introduced earlier, Lumentum IR said EML capacity at the two fabs in Japan grew eight-fold in two and a half years. And yet it still falls more than 30% short [2], so isn’t the bottleneck not the speed of making chips, but the substrate in front of it??

4. The LTA Chain

The picture gets bigger if you look at this contract not as a single box but as a supply chain. Early this year, NVIDIA invested $2B in Lumentum in the form of convertible preferred stock, attaching a multi-year purchase commitment [8]. One layer down, Lumentum put an $87M deposit on AXT and reserved capacity through 2031 [1], and AXT in turn raised funds for substrate expansion through an equity offering in the $600M range [2]. The money that started on the side buying optical modules has come down a full three links, through contract after contract, all the way to substrate expansion.

Because each layer’s seller is the next layer’s buyer, every company puts a deposit on the layer below and receives a deposit from the layer above. When the shortage is real, this chain is rational for everyone.

But as you may have noticed, the problem is that the moment the shortage ends, the chain works in reverse too. That story comes after the paywall.

The LTA chain, three contract links from NVIDIA to Lumentum to AXT with deposit and reservation terms

In fact, the existence of this contract was not news. On the May earnings call, Lumentum said it had already secured long-term agreements for substrate, and even explained that the structure included deposits and take-or-pay (you pay even if you don’t take the volume). Only the counterparty was undisclosed. We covered that passage at the time in The 8 Companies Behind Lumentum’s $808M Quarter and put counterparty disclosure on the monitoring list, and this 8-K is the answer sheet. The name was AXT, and the deposit structure was exactly as foreshadowed.

Everything up to here is what anyone can see from public materials. From here on, we stretch the chain up and down: how deposit contracts ended in past materials cycles, when the expansions arrive, and the detour Lumentum itself is building.

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Abstract

In the last week of July, 2026, the public equity book of the market’s hottest fund was forcibly wound down. It is a name anyone who follows stocks has probably heard at least once: Leopold Aschenbrenner’s Situational Awareness handed most of its public equity positions to Citadel even after posting a cumulative 439% return in the first half of the year. Actually, the fund itself did not disappear (private assets such as its Anthropic stake remain), but its leveraged public market exposure was essentially liquidated in one piece. Interestingly, when you open the 13F as of March 31, this book was not merely a set of long positions but a dual structure, laying puts with an underlying reference value of $8.46 billion across semiconductors and AI infrastructure while holding memory and power as longs. Gavin Baker of Atreides, who survived and is still holding the trade, is throwing a similar valuation question while keeping Micron as a top holding. This article carries a question about that question and tries to cover compute and memory among AI infrastructure stocks. And optics too. Why has compute sold expensive while memory sold cheap for 30 years, and why is that price structure shaking now. My thinking, or my lead, leans toward the possibility that the failure of this trade was about position structure and size rather than direction, but I do not want to conclude that on the already-published 13F alone. I see the bottleneck thesis as not ending at memory but extending to optical connectivity.

Contents

1. The Two Books: What the Wound-Down Book Actually Held

2. Why Memory Sold Cheap for 30 Years

3. 2026, Cracks in the Price Structure

4. What Can Replace DRAM

5. What the Bottleneck Really Is: Not Capacity but Access Speed

6. Where Optics Slots In: The Technology That Moves Memory

7. Scenarios and Monitoring

1. The Two Books: What the Wound-Down Book Actually Held

Before the open on July 30, by what is known, a single off-exchange block deal of roughly $16 billion in stock reportedly took place. The seller, as you know, was Leopold Aschenbrenner’s hedge fund Situational Awareness Limited Partnership (SALP), and the buyer was Ken Griffin’s Citadel.

Amid the AI stock plunge, reports followed that prime brokers demanded margin-call-style collateral, and most of the public equity book was cleared in this deal [1][2]. That said, the fund itself was reportedly not liquidated. Assets shrank sharply from a recent peak of about $45 billion to somewhere around $10 billion, but the remaining $10 billion is reportedly centered on private holdings such as the Anthropic stake [3]. What got cleared, it seems, was the leveraged public equity side. The reported leverage was up to about 400% [1], and by the investor letter the one-month loss in July was about 67% (monthly, on a portfolio basis), yet even after taking that drawdown on top of a cumulative 439% in the first half, roughly plus 80% versus the start of the year remained, which is the strange scale of this event (from 5.4x, a July of minus 67% leaves roughly 1.8x, that is about plus 80%, so the arithmetic checks out) [4].

But when you actually open this fund’s Q1 2026 13F filed with the SEC [5], the picture looks more interesting.

Figure 1: The Two Books of Situational Awareness LP, Q1 2026 13F

As is commonly known, this fund did not only buy semiconductor and AI infrastructure stocks. As of the end of Q1, the 13F reported value of the puts placed across the semiconductor and AI infrastructure stack was $8.46 billion, about 62% of the total reported value (roughly $13.68 billion). The semiconductor ETF $SMH at $2 billion, $NVDA at $1.6 billion, plus Broadcom, Oracle, Infosys, AMD, ASML, Intel, Corning, TSMC, and even Micron were on the put list [5][6].

One important caveat. The VALUE of a 13F option is not the option premium or a delta-adjusted net exposure but the reported value of the underlying security. So you must not read $8.46 billion as an actual P&L sensitivity or a net short size. On the other side, the axis of the longs was names like NAND flash SanDisk, a hot memory name of 2026 (over 1 million common shares plus added call options), Bloom Energy in power, CoreWeave, and IREN, CleanSpark, Applied Digital that pivoted from mining to AI hosting [6].

Here is a point I found a little interesting: the biggest memory name on the long side is SanDisk, and SanDisk’s current core business is not the DRAM or HBM that a GPU really needs but, somewhat unexpectedly, NAND flash storage. So the SNDK long can be a bet on the NAND and storage cycle (and on HBF, which comes later), but I do not think this position by itself proves a DRAM or HBM shortage. In this article, as in the title, I classify SNDK not as evidence for the memory long argument but as a somewhat separate, distinct position.

The original filing is not as clean as the title either. Micron, a US HBM player, has both calls and puts on it at once, so you cannot pin down which way it points, and TSMC, the representative foundry player, has both sides too [7].

The 13F distinguishes whether a position is a put or a call, but it does not show strike, expiry, premium, OTC derivatives, or stock shorts, so you cannot fix the fund’s net exposure from this document alone. Still, six tenths of the reported value is semiconductor and AI infrastructure puts, and the directional-long, bottleneck-side names were memory and power. It is a little unfortunate that for SK Hynix, with no US ADR as of the end of March, you cannot judge Korean-listed holdings from the 13F. In July reporting SK Hynix was mentioned as one of the fund’s major loss names, but the holding vehicle (Korean-listed share or ADR) and the timing of acquisition are not confirmed [8][9].

What is interesting is the side that, unlike SALP, survived this scene of extreme fear and is still holding the trade. In Atreides Management’s Gavin Baker’s latest 13F (as of March 31, 2026), Micron is among the top five holdings on a common-stock basis, and next to it sit connectivity-layer names like Ciena, Lumentum, Coherent, and Astera Labs [10]. Because these names are about “connectivity,” they are closely tied to optics, and I also see Lumentum and Coherent, which I like. That said, Atreides is not a pure-long-only book either. In the same filing an index put (QQQ) is actually the single largest reported position, so if you compare with one side’s hedges detailed and the other side’s longs highlighted, the basis becomes asymmetric [10].

SanDisk, which was a strong long position in SALP, appears to be absent from this filing. SNDK is a 13(f) reportable security, but the absence of a reportable long in the end-of-March filing means only that holdings above the reporting threshold are not confirmed, not proof that the holding was zero. That is, a small holding or confidential treatment is possible. As for SK Hynix, there was no US ADR at the time, so you cannot judge Korean-listed holdings from the 13F. This point is a bit of a limit.

On the other hand, in Gavin’s case, from his remarks he publicly pointed out the valuation contradiction that semiconductor equipment stocks trade at roughly 40x next-quarter annualized earnings, while the memory produced through that equipment sits at a mid single-digit P/E [11], and while acknowledging that by the playbook of the past 25 years of memory cycles now is the time to sell, he still stands on the memory side (per summarized conference reporting) [12].

So this article I am writing today is not about “the two funds’ AI long positions.” It is about two different books (different names, sizes, and endings). Is the value of the AI stack moving from compute engines like CPUs and GPUs to the physical bottleneck? One side answered that question with heavy leverage and could not withstand the market’s volatility and decline [4], and the other side keeps the same question at a size it can hold.

I see the trade’s fate as likely decided by position structure and sizing more than direction. That said, net exposure, option terms, and per-position July P&L contribution are not disclosed, so I do not think you can conclude from the 13F alone that “the direction was right and only the size was wrong.”

So then, the two people, Leopold and Baker, why did they see compute as expensive and memory as cheap.

Situational Awareness’s 13F was a dual structure of semiconductor and AI infrastructure puts (reported value $8.46 billion, about 62%) and bottleneck longs, and Atreides’s filing has Micron and the connectivity layer side by side (though there is a QQQ put too). What the two funds share is not a position but a question.

2. Why Memory Sold Cheap for 30 Years

To answer this question, it seems best to first understand why memory was cheap in the first place. To help understanding, let me borrow flour, something we commonly encounter. DRAM is close to flour, and a GPU is, in a way, a premium ingredient handled in a Michelin restaurant kitchen. But it is not standardized.

By contrast, flour has a spec. If it is all-purpose grade 1, whatever mill’s product or brand it is, you generally get bread of the quality you expect. So the baker looks at price rather than the flour’s brand or label. DRAM is a product of a similarly designed market. Once a standards body called JEDEC sets a certain fixed spec for items like DDR5 and LPDDR5, then whether it is a chip made by Samsung or a Micron chip or an SK Hynix chip, among equivalent configurations that have passed JEDEC qualification the substitutability is very high. In other words, what matters is DRAM’s price.

Of course, in a real system density, rank, timing, ECC, PMIC, thermal, and platform qualification (QVL) come into play, and a platform vendor like Intel also runs compatibility validation separately from JEDEC conformance [13]. Even so, commodity DRAM has a relatively low switching cost, so from the buyer’s standpoint there is little reason to weigh brand much, and they end up deliberating over the price tag.

And at the same time supply-side circumstances overlap here. As is well known, a memory fab takes years and tens of billions of dollars to build, but once built it is hard to stop. Because most of the cost is fixed, like depreciation, even in a downcycle it is reportedly better to print and sell one more wafer than to idle. So even if demand rolls over, supply does not, and price falls to near cash cost. Then when supply is cleaned up it becomes scarce again and price jumps, that so-called “cycle” repeated. An industry where price per bit has fallen for over 30 years, an industry where the next bust reclaims the boom’s profits. The market assigning memory a low multiple was precisely the result of learning.

But the Michelin kitchen is a completely different story. A Michelin chef’s dish is bound together with the recipe and the whole kitchen, so you cannot swap it out for the restaurant next door’s dish. What NVIDIA sells is also not a single chip but a system bound together with the CUDA software ecosystem, the developer base, and networking. When you cannot swap it in, that is exactly where pricing power arises. This is, to take a foundry example, how TSMC, holding an overwhelming lead in leading-edge foundry, has protected its margin by the same principle.

Figure 2: Commodity vs Differentiated: Why Logic and Memory Priced Apart for 30 Years

So the market developed a so-called “30-year” habit. A differentiation premium on logic, a commodity discount on memory. In other words, is not today’s gap that Baker pointed out, equipment at 40x versus memory in the single digits, the result of this habit [11]? That said, this P/E comparison may not be apples to apples because the target companies, GAAP versus non-GAAP, and forward basis differ, and the point that the moment memory’s P/E looks lowest may actually be the cycle peak is something I revisit later.

3. 2026, Cracks in the Price Structure

What the two funds, SALP and Baker, saw is probably the gap between this habit and reality. At some point flour prices started moving in a way that is not very flour-like.

By TrendForce’s tally, 3Q 2026 server DRAM contract prices are projected to rise 13 to 18% quarter over quarter, and this is called a “calming” phase, which is to say the prior quarters’ increases were even larger (over 90% in Q1, 50 to 60% in Q2) [14]. SK Hynix CEO Kwak Noh-jung, in an interview around the Nasdaq listing, said 2027 would be the worst year in industry history from a supply standpoint, and that excess demand could continue past 2030 [15]. In other words, it is now not a cyclical industry but structural shortage [16]. The stock price showed the same conclusion. SK Hynix’s Korean-listed share is up about plus 420% over the last 12 months, and even reflecting the pullback from the June peak it has risen nearly 8x (Korean-listed basis, as of 2026-07) [17].

At the center of this DRAM and memory price-structure change is that HBM we know well. HBM (High Bandwidth Memory) is memory that stacks DRAM dies vertically, connects them with through-silicon vias, and places them right next to a compute engine like a GPU, that is, the processor. But one misunderstanding needs to be cleared. HBM is also a JEDEC standard. HBM3 and HBM4 have spec documents too. The point where it diverges from flour is not the presence of a standard like JEDEC but exactly the switching cost.

Stacking method and yield, and thermal management and packaging differ by supplier, qualification with a customer’s chip takes several quarters, and it is sold not on spot but on multi-quarter long-term supply contracts. From the HBM4 generation, the share of advanced logic in the base die at the bottom of the stack grows and some of it goes custom (it differs by supplier and product, and Micron specifies an optional custom base logic die in HBM4E), so a differentiation layer is added. In short, HBM has higher customer-qualification and package-integration cost than commodity DRAM and a higher share of long-term contracts, making it a product where switching suppliers is hard. That is, it shows a character similar to the Michelin restaurant ingredient mentioned above. The path by which, as HBM demand grows, memory gets pushed out into a shared pool beyond the optical connection was covered in a previous article [18].

The market too started putting money on this change. On July 10, SK Hynix listed an ADR on Nasdaq and raised a large amount, one of the largest US listings by a foreign company, with subscription demand more than 7x the supply [19].

But in that very July, something in the exact opposite direction happened. In one month from the late-June peak, SanDisk, a NAND flash flagship, fell over 40%, the neocloud Nebius fell over 46%, and SK Hynix also slipped about 40% from its June peak [8]. In this situation one of the last triggers was China. CXMT, the number four in DRAM, jumped 466% on its first day on the Shanghai listing (over 500% intraday at one point, versus the IPO price) and became China’s most valuable listed company, but the fear that China-origin supply could end this crunch rode that symbolism and hit memory across the board [20].

The point I am curious about is how to interpret this July drawdown. Is this blow to memory across the board a disproof that “memory was flour after all”? Or is it old fear making one last cover in the transition from commodity to a contract-type asset.

To judge it you now have to look not at price but at physics. It is normal capitalist operation for substitutes to appear when a commodity gets expensive, so in memory what becomes a substitute and what does not. That answer is the floor of this whole trade, and the place where optical connection slots in is right there.

Below is the original text of Situational Awareness’s 13F filed on SEC EDGAR on May 18 [5].

Figure 3: Screenshot asset: SEC EDGAR, Situational Awareness LP Form 13F-HR, filed 2026-05-18

HBM, even with a standard, has a high switching cost and is in effect memory sold on a contract basis. The contract-price rise and the July drawdown are two sides of that transition, and the criterion for judgment is not price but physics. (The 13F figures in this section are a March 31 snapshot and do not reproduce the pre-liquidation portfolio of July 30.)

4. What Can Replace DRAM

When prices rise like this, normally a substitute appears. But so far, exceptionally, in memory the force that tries to create a substitute has mostly been blocked by physical constraints, yet let me still look at the candidates.

SRAM: the fastest but takes up too much room (the chip’s footprint). SRAM, used as cache inside the processor, is tens of times faster than DRAM. Told only this it sounds like a very good candidate, but the problem is that storing one bit needs 6T (six transistors). DRAM needs 1T1C (one transistor and one capacitor). The number of bits you can pack into the same physical area differs by an order of magnitude. On top of that, even in the latest logic process, SRAM’s cell area no longer shrinks well because of a fundamental physical constraint.

NAND (as pure flash): the cheapest with ample capacity, but too slow a candidate. Price per bit, NAND is overwhelmingly cheap. But its access time is on the order of microseconds. DRAM is on the order of tens of nanoseconds.

New memory: there have continually been attempts to insert a new layer between DRAM and NAND. Substitutes like PCM, MRAM, ReRAM were floated. The most serious attempt was Intel’s 3D XPoint Optane, but the ending was not good.

HBF (High Bandwidth Flash): SanDisk is emphasizing HBF, which raised bandwidth by giving NAND an HBM-style vertical-stacking interface. At the same time it signed a standardization agreement with SK Hynix [21]. The core claim is that at roughly a similar package height it aims to greatly increase capacity versus HBM (at a similar price band). That said, HBF is not a thing meant to chase DRAM’s ultra-low latency and speed, but an approach to fill inference’s capacity tier far more cheaply. So to put it precisely, it should be seen not as “a replacement for the DRAM cell” but as a candidate for “partial substitution of the HBM capacity burden,” and many take the view that, still at the standardization and development stage, you cannot confirm it as a commercial substitute. And there is an opinion that it has to use optics, and the structure of HBF and its point of contact with optical connection was covered more deeply in a previous article [22].

Figure-Table 1: The Substitute Audit: SRAM / NAND / New-Memory / HBF and Where Each Lands

So then, can you not just make more DRAM itself? Right here is the second physical wall.

One bit of DRAM, as said above, consists of one transistor and one capacitor (1T1C). If you liken charge to water, the capacitor is the bucket that holds that charge. In process terms, this bucket is exactly the problem. If, because of area, you shrink it sideways, the charge it holds drops and reads become unstable from noise, so you have to pull it up long as much as you shrank the side (to keep total capacity). As a result, today’s DRAM capacitor is a pillar whose height is tens of times its width, and the aspect ratio is enormous.

And at the same time, the difficulty of erecting billions of these pillars identically rises every generation. Because it is not a structure where, like logic, shrinking the transistor automatically brings along performance and density, even bringing in advanced equipment like EUV, the efficiency converted into bit growth is not large compared to logic.

In fact the process-generation names testify to this stall. While logic goes down to 7nm, 5nm, 3nm, DRAM only swaps the suffixes 1a, 1b, 1c somewhere in the low 10nm range. That is, there was no big advance in the 10nm range.

Oh, of course, the effect of scaling has not vanished. Recent node transitions still have cases that give bit-density improvement of about 30 to 35% [23]. But the process complexity and cost to obtain that improvement have grown much larger than before, so it would be accurate to say that making economic bit growth as before has become hard.

On top of that, because the capacitor leaks charge, you have to refill it every tens of milliseconds (refresh), and as cells get smaller this maintenance burden grows too. So DRAM’s bit growth, once you subtract the contribution of process transition and yield improvement, comes largely from wafer input and capex. The point is there is no free growth of the kind scaling gives to logic.

As mentioned, DRAM is not easy to make, but that precious, costly wafer that should go to DRAM is now being used for HBM. HBM has large dies, the through-vias for stacking (TSV) take up area, and the yield after stacking several drops multiplicatively.

Micron has stated that, on a same-bit basis, HBM3E consumes about 3x the wafers of D5 [24]. Naturally, from a maker’s standpoint it is rational to allocate wafers first to high-margin HBM, and the more it does, commodity DRAM supply shrinks. As a result of this, it means this cannibalization is a big cause among the supply-side factors of the memory contract-price rise. This is something I see as physically unsolvable until new fabs are completed.

In conclusion, DRAM’s ultra-low-latency seat is still filled only by DRAM, and DRAM’s capacity expansion is possible only with time and money. In the capacity tier HBF has come up as a candidate to partially share the burden, but it is still at the development stage. Kwak Noh-jung’s “past 2030” remark is not exaggeration but a physical reason [15], and it is also the reason it fits when you read the two funds’ positions as memory being not a “chip seller” but a “bottleneck that is hard to expand.”

Key point: SRAM drops out on area, pure NAND on speed, new memory on ecosystem. HBF is an exception as a partial capacity-tier substitute candidate but is still at the development stage. DRAM capacitor physics makes economic bit growth hard, and HBM’s wafer cannibalization squeezes commodity supply.

5. What the Bottleneck Really Is: Not Capacity but Access Speed

Now then, the word bottleneck needs to be made one layer more precise.

In fact the bottleneck is not one but two. One is the speed at which a compute engine like a GPU reaches local HBM (the bandwidth wall), the other is the total memory to hold the model and the KV cache and rack-level utilization (the capacity and utilization wall). This is a thesis I have repeated in this article, and a piece I wrote recently: the three-branch approach to bypassing the memory wall was laid out in detail in a previous article [25].

In the decode phase where an LLM generates the answer one token at a time, each time it makes one token it has to read the model weights and the KV cache heavily. In a single request or low-batch dense decode the per-token throughput limit is set roughly by “memory bandwidth divided by bytes read per token,” so the GPU’s compute engine idles and memory bandwidth sets the schedule. (Bandwidth is limited, but because bytes read per token grow, speed drops and accordingly a situation arises where compute engines like GPUs idle.)

So then, what about not low-batch dense decode but when the batch grows?

Weight reads are amortized across many requests, and depending on MoE, quantization, speculative decoding, attention structure, and context length, I see the bottleneck able to move to compute, capacity, or interconnect. So “bandwidth is unconditionally the only bottleneck” is not the case, and it is especially so under low-batch conditions. To borrow the phrasing of Celestial AI founder Dave Lazovsky, the industry right now is using NVIDIA GPUs as “the most expensive memory controllers in the world” [26]. I also agree with this.

If you accept this diagnosis, compute puts and memory longs are not two different bets but read as two sides of a fundamental constraint by the same system, or of that diagnosis. It is a diagnosis that on the non-bottleneck side (compute) the price carries a bottleneck premium, and on the bottleneck side (memory) the price carries a commodity discount. That is, put differently, the fact that the real bottleneck memory carries a discount rather than the premium it ought to receive, and that compute has a premium, is what Leopold’s book and Baker’s remarks come close to as a structure.

The next variable after this diagnosis is the wiring. If access speed is the bottleneck, where does the technology that changes the wiring itself stand? Right here is the point where optics enters.

6. Where Optics Slots In: The Technology That Moves Memory

Coming back to filings again, in Situational Awareness’s Q4 2025 book there was the optical component company Lumentum, but in Q1 it was fully sold along with Coherent [7]. The reason for the sale is unfortunately not knowable from the filing alone. Valuation burden, risk reduction, hedge adjustment against another position, many readings are possible, and the only certain thing is the fact of the sale.

By contrast, in Atreides’s latest filing, next to Micron, Ciena, Lumentum, Coherent, and Astera Labs still sit side by side [10]. In short, the 13F does not neatly tell the story that “the bottleneck fund holds optics.”

Because optical connection has to be derived not from filings but from technical analysis, from here I try to move not to positions but to a physical story.

An electric link carried over copper, as frequency rises, has channel loss growing sharply as bandwidth and distance grow together, and the equalization and retimer power to correct it swell quickly. There is thermal loss too, of course. This is why an HBM-class-bandwidth interface sits inside the same package as the processor, at millimeter distance.

As a result, the ratio of memory capacity to bandwidth loaded on a single GPU is fixed at packaging time. If you need more memory, the structure is that you have to buy a whole new GPU with compute attached. What Lazovsky’s “most expensive memory controller” line points to seems to be this fixed ratio [26].

But unlike copper, light has this distance constraint much looser.

Optical connection, even crossing meters, has small loss and power penalty versus electric, so in theory you can pull memory out of the package, even into a separate chassis, and make a pool shared by multiple processors. It is not a technology that replaces memory but a new-paradigm technology that changes where memory sits. How this optical memory fabric got tangled with actual stock flows (the SOCAMM selloff and so on) was covered in a previous article [27].

That said, I want to stress that this deals mainly with the capacity and utilization wall and data movement among the two walls divided above, but is not a technology that directly replaces or copies the fundamental problem, local HBM’s latency and bandwidth.

Figure 4: Where Optics Enters the Memory Wall: Network CPO vs Optical Memory Fabric

The company trying to commercialize this inner layer head-on is Celestial AI. At OFC 2025 it presented an architecture implementing memory-compute disaggregation with an optical fabric [28], and module specs are public too. Two HBM3e stacks act as a cache for large-capacity DDR5 so the processor sees HBM’s speed and DDR5’s capacity at once, connected at 7.2 Tbps optical bandwidth per module, and by bundling several such modules it builds a shared memory appliance in the tens of TB range [29].

Marvell announced the acquisition of this company in December 2025 and completed it on February 2, 2026 (about $3.25 billion) [30]. So then, why did Marvell acquire such an optical connection company?

The first commercial application Marvell put forward is not pooled memory but all-optical scale-up interconnect, and the meaningful revenue-contribution timing was guided to the second half of FY2028 (from a $500 million annualized run rate per quarter, doubling thereafter) [30]. That is, optical memory pooling can be read as not the center of the current business but an option on a longer horizon. Seeing $MRVL right now as immediately “optical memory pooling” seems a bit not easy. The vendor-claimed figures of “25x bandwidth and one tenth the latency versus prior CPO” are worth keeping an eye on [31].

From a memory maker’s standpoint, how does the direction of this optical connection technology look?

Even if memory goes out to the shared pool beyond the optical fabric, what fills that pool is still the same three makers’ DRAM, so it ends up raising total DRAM bit demand. At the same time pooling can reduce stranded HBM and raise utilization, playing the role of lowering the total of costly local HBM that must be mounted per accelerator. In some workloads DDR5 or, later, HBF could take a larger share instead of local HBM.

So in the investment picture the position sorts out like this. If the memory long is a bet that “the bottleneck should get expensive,” the optical memory fabric is, I think, a longer-horizon bet that “a premium attaches to the connection that unblocks the bottleneck.”

It got long, so to sort a little: “optical connection is not a technology that replaces memory but one that breaks the fixed ratio of processor to memory and moves memory into a shared pool.” “Marvell’s Celestial acquisition closed in February 2026, the first market is scale-up, memory pooling is the longer option.” That is it.

References & Sources

[1] “AI investor Leopold Aschenbrenner forced to unwind all public stock positions after steep losses, sources say”, CNBC, 2026-07-30

[2] “Citadel buys most of Situational’s stock holdings after AI share rout, sources say”, Reuters, 2026-07-30

[3] “Situational Awareness Drops to $10 Billion on Citadel Pact”, Bloomberg, 2026-07-30

[4] “Situational Awareness’ portfolio sinks 67% in July on AI stock rout, letter shows”, Reuters, 2026-07-31

[5] “Situational Awareness LP, Form 13F-HR, Period 2026-03-31”, SEC EDGAR, filed 2026-05-18

[6] “Leopold Aschenbrenner’s ‘Situational Awareness’ Files 13F Quarterly Investment Disclosure”, Yahoo Finance, 2026-05-18 (secondary summary)

[7] “The Most-Anticipated 13F of 2026: What Leopold Aschenbrenner Actually Owns”, DaveManuel.com, 2026-05-19 (secondary)

[8] “NVDA, NBIS, SKHY, SNDK Stock Losses Reportedly Force Ex-OpenAI Researcher’s $20B Fund To Seek Capital”, Yahoo Finance / Stocktwits, 2026-07-30 (secondary)

[9] “SK Hynix Stock Jumps 14% on Nasdaq Listing”, INDmoney, 2026-07-10 (secondary)

[10] Atreides Management, LP: Form 13F-HR, Period 2026-03-31 (54 holdings; INVESCO QQQ put is the single largest reported position, Micron 760k common shares), SEC EDGAR / 13f.info (accession 0001777813-26-000006), filed 2026-05-18

[11] “15 Key Takeaways From Gavin Baker’s Invest Like the Best 2026 Interview”, Global Data Center Hub, 2026-06-02 (interview summary)

[12] “Sohn New York 2026: Baker and Khaira on the Shortage That Could Save AI From a Bubble”, Hedge Fund Alpha (2026 Sohn NY, Gavin Baker x Jas Khaira fireside; “based on every memory cycle over the past 25 years, now is 100% the time to sell”)

[13] “Intel Memory Validation Results”, Intel (basis for separate platform validation)

[14] “Server DRAM Contract Prices Expected to Rise 13-18% QoQ in 3Q26, Says TrendForce”, TrendForce, 2026-07-09

[15] “SK Hynix CEO Expects Memory Crunch to Last Beyond 2030”, Bloomberg, 2026-07-10

[16] “SK Hynix CEO Sees Worst-Ever Memory Supply Shortage in 2027, Says Demand to Outstrip Supply Beyond 2030”, Reuters via U.S. News, 2026-07-10

[17] “SK Hynix stock’s US listing could signal whether the market can still boom…”, Fortune, 2026-07-05

[18] PhotonCap, “The More Anthropic Buys Micron HBM, the Faster Optical Memory Pooling Arrives”, 2026-06-24 (PhotonCap self-citation)

[19] “SK hynix US listing more than seven times oversubscribed, source says”, Reuters, 2026-07-09

[20] “Chipmaker CXMT’s 466% market debut surge makes it the most valuable China-listed company”, CNBC, 2026-07-27

[21] “Sandisk and SK hynix join forces to standardize High Bandwidth Flash memory, a NAND-based alternative to HBM for AI GPUs”, Tom’s Hardware, 2025-08 (HBF standardization MoU, 8 to 16x capacity, samples 2H 2026)

[22] PhotonCap, “HBF (High Bandwidth Flash) and Optics: The Missing Link in AI Infrastructure”, 2026-01-26 (PhotonCap self-citation)

[23] “How DRAM Changed the World”, Micron (context for node-transition bit-density improvement)

[24] “HBM is Coming for Your PC’s RAM: HBM consumes around three times the wafer capacity of DDR5 per gigabyte”, Tom’s Hardware (citing Micron remarks, HBM3E about 3x wafers)

[25] PhotonCap, “Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains”, 2026-07-26 (PhotonCap self-citation)

[26] “Celestial AI Wants To Break The Memory Wall, Fuse HBM With DDR5”, The Next Platform (original Lazovsky interview)

[27] PhotonCap, “The Cut Was Not HBM: The SOCAMM Selloff and the Optical Memory Fabric”, 2026-06-16 (PhotonCap self-citation)

[28] “Photonic Fabric for Memory and Compute Disaggregation”, OFC 2025 Technical Digest, paper W3D.1

[29] “Marvell bets big on optical I/O with $3.25B Celestial AI deal”, Gazettabyte, 2025-12 (spec at announcement)

[30] “Marvell Completes Acquisition of Celestial AI”, Marvell, 2026-02-02 (acquisition closed, scale-up first, second-half FY2028 revenue guidance)

[31] “Marvell Looks to Acquire Celestial AI”, Optics & Photonics News, 2025-12 (25x / one tenth are vendor claims)

Additional read:

Irrational Analysis

[Market Memo] A tale of two heroes.

Irrational Analysis is heavily invested in the semiconductor industry…

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23 days ago · 104 likes · 12 comments · Irrational Analysis

Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

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On July 29, the top and bottom of the semiconductor supply chain moved in opposite directions. SK hynix ($SKHY) printed a record 60.5 trillion won in quarterly operating profit and still closed down 9.6% in Seoul. That same night, FormFactor ($FORM) delivered a big beat, $258.2M in revenue and $0.82 in non-GAAP EPS, and jumped as much as 17% after hours. The divergence shows how supply expansion can pressure memory pricing while supporting wafer test volumes, and Tower Semiconductor’s ($TSEM) August 4 report is the next check on the foundry side. My lean has not changed: long the fab, packaging, and testing layers.

Contents

1. July 29

2. Where the Selloff Started

3. FormFactor’s Numbers

4. Same Money, Opposite Directions

5. Reviewing the Last Call (Q1 2026)

6. The Next Gate: Tower, August 4

7. Monitoring

1. July 29

July 29 produced two very different screens.

Figure 1: July 29 two screens. SK hynix record earnings and -9.6% close vs FormFactor beat and +17% after hours

Tuesday evening US time, SK hynix reported second quarter 2026 results. Revenue of 79.3 trillion won, up 257% year over year. Operating profit of 60.5 trillion won, up 557%. A 76% operating margin. By any measure, a quarter that belongs in semiconductor history.[1] The stock fell more than 15% intraday in Seoul before closing down 9.6%.[2]

The decline was not a one-day event. The day before, on the 28th, Samsung Electronics lost more than 13%, Tokyo Electron 11%, and Advantest more than 10%[3], and over $1 trillion of market cap evaporated from the world’s largest chip stocks in a single week.[2] One tally has the Philadelphia Semiconductor Index on pace for its worst month since 2008 (per secondary media compilation).[4]

Then on Wednesday after the close, right in the middle of all that, FormFactor reported. Revenue of $258.2M beat consensus, non-GAAP EPS of $0.82 cleared the $0.61 estimate by a wide margin, and the first Q3 guidance the company issued also came in above consensus.[5][6] The stock had fallen 5.5% with the market in the regular session, then reversed after the release, touching a 17% gain after hours before settling back to a 12 to 14% gain (as of 2026-07-29, after-hours basis).[6][11]

In a week when everything was falling, one earnings report produced a double-digit after-hours reversal. That was not random. The two stocks were reacting to different parts of the same cycle.

2. Where the Selloff Started

SK hynix’s numbers were records, but they fell short of the market’s bar. Operating profit of 60.5 trillion won missed consensus by roughly 6%[1][2], and on top of that sat worries about the durability of big tech AI spending and the absence of a shareholder return plan. The decline had more than one cause.

One variable stands out for this story, though. SK hynix said it would lift 2026 capex into the high 40 trillion won range, roughly $31B.[7] That is an increase of about 50% year over year. Capacity does not grow 50% overnight, but the market read it as a signal that medium-term supply expansion is speeding up.

Memory is a pricing business, and today’s record profits exist because supply cannot keep up with demand. When supply expansion accelerates, the shelf life of those profits comes into question. Investors who lived through the 2018 and 2022 downturns do not need much encouragement to sell. Add the capacity worries around China’s CXMT, which listed this week.[8]

Demand fear and supply fear are not the same thing. If demand breaks, every layer of the chain hurts together. Supply expansion hurts the companies exposed to pricing before it hurts the suppliers exposed to unit volumes.

3. FormFactor’s Numbers

Now FormFactor’s quarter, the fiscal second quarter ended June 27, 2026.[5]

Revenue of $258.2M, up 14.2% sequentially and 31.9% year over year, an all-time record. Non-GAAP gross margin of 53.3%, up 1,480bp from 38.5% in the same quarter a year ago. One caveat: that 53.3% includes one-time items such as tariff refunds and precious metal reclamation, and the CFO put the sustainable baseline at roughly 51% at current volumes and mix.[11] Non-GAAP EPS of $0.82 is more than triple last year’s $0.27, and free cash flow came in at $52.6M. Compared with negative $47.1M a year earlier, the improvement in cash generation is hard to miss.[5]

The first Q3 outlook the company has issued also landed well above consensus: revenue of $270M plus or minus $10M, non-GAAP gross margin of 54.0% plus or minus 1.5%, and non-GAAP EPS of $0.86 plus or minus $0.09, against street numbers around $247M and $0.63.[5][6]

The release named its growth drivers explicitly: High Bandwidth Memory (HBM, the high-bandwidth memory stacked next to AI accelerators) and Co-Packaged Optics (CPO, the approach that puts optical components into the same package as the processor), crediting them with driving sequential growth in the Probe Cards and Systems segments respectively.[5] CEO Mike Slessor pointed to four quarters of 30%-plus revenue growth, 1,500bp of non-GAAP gross margin expansion, and a tripling of EPS, describing the company’s position as sitting at “the intersection of high-performance compute and advanced packaging.”[5]

The numbers still leave the day’s question open. In a week when memory was breaking, why did a company whose largest customer was approaching 30% of revenue go up? What the same $31B that sank SK hynix means for FormFactor is the first thing behind the paywall.

Then comes the review of the last call: the gates set in May’s Q1 piece, where SK hynix’s 29.5% went, whether NVIDIA held above 10%, whether the CPO guide moved, all judged against this quarter’s data. Hits, holds, and retractions, on the same standard. And then Tower: where $TSEM sits ahead of its August 4 earnings, and which seat it holds in the long fab, packaging, testing thesis.

Figure 2: FormFactor Q2 2026 key numbers card. Revenue, margin, EPS, FCF, Q3 guide

Key point: A big beat, and a first-issued Q3 guide above consensus. HBM and CPO were named as growth drivers in the earnings release itself.

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Interestingly, $QQQ fell more than 2% on Wednesday. The decline that started off the May highs has now brought the index right on top of its 200-day EMA. The line sits around 648, roughly 2% below the close.

$QQQ is now down more than 11% from the high, and most of that damage came in the last two weeks.

The chart alone doesn’t explain this selloff. Start with what actually happened yesterday.

So, What Happened? (AI summary)

The Fed held rates at 3.50–3.75% at the July FOMC meeting, its sixth straight hold. The hold itself was expected. Going into the meeting, fed funds futures put the odds of a hold around 68%.

The tone was the problem. Three of the twelve FOMC members dissented, and they wanted a hike. Not a cut. A hike. In the press conference, Chair Warsh stuck to his policy of withholding forward guidance and took a hard line on inflation, and he made clear he has no interest in suppressing the recent rise in Treasury yields, saying the Fed is deliberately stepping back to watch the market’s reaction. The Nasdaq 100 and S&P 500 gave back all of their gains during his remarks.

This matters because the market is not waiting for cuts right now. After the meeting, futures priced the odds of a 25bp hike in September in the mid-50% range. Oil is the reason. Crude is up more than 20% in July on the conflict with Iran, and the expected pass-through to headline inflation is what the hawks inside the Fed are pointing to.

The bond market also added to the pressure. The 10-year rose to 4.67% and the 30-year jumped to 5.21%, its highest level in 19 years, while the 2-year actually fell. Long rates rising alone is a steepener, and it reads like the bond market questioning whether the Fed has inflation under control.

Against that backdrop, the Dow dropped 2.19% for its worst day since April 2025, and the Nasdaq fell 1.74%, ending the session more than 10% below its all-time high. Official correction territory, if you care about the label.

The AI and AI Infrastructure Side

The other axis of this selloff is a shift in how the market treats AI capex. As you already have seen, last week, Alphabet (Google) raised its 2026 capex forecast and the stock fell 7%, dragging Amazon, Meta, and Microsoft down with it. Alphabet guided to roughly $200 billion of capex over the next twelve months, and its quarterly free cash flow went negative for the first time in company history. The problem wasn’t that spending fell. The problem was that it kept growing.

Last night’s earnings showed both sides of that trade. Microsoft beat with $90 billion in revenue and held its calendar 2026 capex plan steady, and the stock popped 8% after hours. Spending unchanged, but “the envelope isn’t blowing out” was enough for a relief rally.

Meta beat on revenue at $60.8 billion but missed badly on EPS, raised the floor of its full-year capex guidance to $130 billion, and reported free cash flow of just $784 million. Yes, million. The stock fell 5% after hours.

There is still no sign that demand has cracked. Microsoft has disclosed a backlog of Azure orders it cannot fulfill because of power constraints and demand is outrunning supply. What the market is punishing is not demand. It’s the pace of spending, the disappearing free cash flow, and the fact that more of this buildout is being funded with debt. With the long bond at a 19-year high, that combination compresses multiples.

Where the Chart Sits

A brief word on why QQQ is the chart I’m watching, and not the S&P. The drawdown is simply bigger here. The Nasdaq is more than 10% off its high while the S&P’s decline is shallower, and that gap is the point: this selloff is concentrated in tech, and inside tech, in AI and AI infrastructure names. Those are QQQ’s largest weights. If this is a repricing of the AI trade, QQQ is where it shows up first and where it will resolve first.

On the QQQ daily:

• The pattern of lower highs since May turned into a fast decline over the past several sessions. The 20-day and 50-day are gone, and the 100-day area has given way.

• The 200-day EMA sits around 648–649 and is still rising. Price is about 2% above it.

• 600 (I mean a round number) is the level the index chopped around for months starting late last year. If the 200-day fails, that’s the next level.

• RSI is at 32.4, near the oversold line at 30 but not through it.

• Volume has been building on the down days.

I’ll get to the late-March comparison below. Short version: the shape is similar, the backdrop is not.

The calendar isn’t done either. Amazon reports after the close on Thursday, the last of the four hyperscalers.

That covers what can be verified in the market right now. Below, I lay out why I lean toward calling this a correction, how much weight the March analog can actually carry, and what would change my mind.

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Disclaimer: This article is a joint publication. The management meeting and investment analysis were prepared by Aurelion Research, and the technical comments by PhotonCap. All content is based on publicly available information and the authors’ notes, and is provided for educational and informational purposes only. Nothing herein constitutes investment advice or a recommendation to buy, sell, or hold any security. Interview responses are paraphrased and do not represent verbatim statements by Lumentum or its management. The authors may hold positions in securities discussed. Readers should conduct their own due diligence before making any investment decisions.

Aurelion Research recently met with Kathryn Ta, Vice President of Investor Relations. We (Aurelion Research) found the conversation very useful, and it gave us a clearer view of the central debate around the stock.

Management meeting and investment analysis by Aurelion Research. Technical review comments by PhotonCap.

Aurelion Research’s Methodology: We independently reach out to company management teams. We do not receive compensation from any company covered. The answers from interviews are based on our notes and have been adapted and presented for clarity. They do not reflect the speakers’ exact words and apply Aurelion’s own thinking. We have selected the sections below that we believe are the most relevant parts of our discussion. We believe all information presented is publicly available. This content is for informational purposes only and is not investment advice or a recommendation to buy or sell any security.

AR: Our view, and it is still an emerging one, is that we are compute constrained as a society and may become more so. As models like Kimi K3, GPT 5.6 and the latest Grok get cheaper per token, elastic demand should push total token consumption higher rather than lower. How does Lumentum think about that? Does it shape capacity expansion or the innovation around data center efficiency?

Answer: Lumentum is at the “plumbing“ layer of the data center, two or three steps removed from any token economics. The number they optimise is power efficiency per bit, and the route to it is higher power lasers. The more bits moved per square area of indium phosphide, the more value delivered. Speed and efficiency are the same problem to them; faster transmission is how joules per bit comes down.

On capacity, they are adding as fast as they can. Two fabs in Japan produce most of the world’s supply of EML lasers, and capacity there is up eight-fold in two and a half years. She offered that as representative of adds made elsewhere. Lumentum now runs five fabs, including a new one starting to ramp that is not yet producing wafers. Every site has had tools added, and several have had the building shell expanded to fit more.

Thoughts:

Efficiency as the optimisation target is the right thing to be chasing. Hyperscalers are working on cost per token and that pressure runs all the way down to the “plumbing”.

The useful part is incentive alignment. Higher power and higher speed make the link more efficient and carry higher ASP at the same time. Lumentum gets paid to build what its customers actually need.

One flag. Eight-fold EML capacity in two and a half years cuts against a pure scarcity thesis. Lumentum is racing to relieve the bottleneck that gives it pricing power. We read that as confidence. Management is building for durable demand.

PhotonCap comment: One engineering caveat on the eight-fold figure. Wafer starts and qualified yield at the newest spec are different numbers. A fab-level capacity multiple does not relieve a 200G per lane shortage one to one, because the binding constraint is yield at the highest power bins, not floor space. This is also why PhotonCap reads the margin question differently. Building capacity takes money. Hitting the top bin takes years of practice. That is why the eight fold number overstates the relief, and why the shortage premium itself is not durable while the margin that survives lives in yield and mix, not in the shortage price.

AR: In the same vein, the consensus view is that we are copper constrained, which should pull optics deeper into the compute architecture. Where do you think we are on that migration between racks, into packaging, and eventually on-chip?

Answer: Today’s co-packaged optics is opportunistic rather than forced. Nvidia deploys it because a faster, more power efficient laser frees up power that can be redirected to the GPUs, which buys system performance. Copper has not run out of headroom yet.

She puts copper hitting the wall in late 2027. That is when the first scale-up CPO deployments arrive, or MPO fiber connectors where customers want a different configuration, driven by link lengths beyond roughly three meters connecting rack to rack. Credo and Broadcom argue six meters is achievable. On paper it is, but the power you would have to push through that copper makes it impractical, so the switch to optical happens around that point regardless.

Thoughts:

Voluntary demand is higher quality demand. That framing helps the bull case. You are buying two S-curves. The opportunistic one is largely played out. The scale-up one has yet to begin.

PhotonCap comment: Agreed on the copper framing. Copper’s limit is not a date. It is a cost curve of reach, speed, and power, and Kathy’s answer to the six meter claims concedes it: doable, but the power bill kills it. The same logic cuts through “voluntary.” A data center runs against a fixed power envelope, so every watt saved on networking is a watt handed to the GPUs, and Nvidia’s own material puts CPO at 3.5x lower power than pluggable transceivers. Copper is not forcing this wave; the power budget is. The scarcer power gets, the stronger this demand becomes. The weak spot is not the voluntariness but that it rides on one company’s architecture choice.

AR: Following on the Broadcom point, there are open questions about the long-term winners in optics and whether they end up being the silicon giants who can acquire an optics platform and integrate it on-chip. As value migrates toward integration, how does Lumentum avoid becoming a quality supplier of a commodity input?

Figure 1: Two Waves of Co-Packaged Optics. Figure: PhotonCap x Aurelion

Answer: Three defences, in her framing.

Competition thins out as power ratings climb. Producing 150 to 400 milliwatt lasers at high volume, high yield and high reliability is difficult, and she does not see many players able to do for Nvidia what Lumentum does today.

Second is survivorship. Lumentum and Coherent are the two companies left standing from telecom, an industry she describes as historically punishing to serve. Lumentum’s laser chip expertise came out of acquisitions and out of meeting reliability requirements the hard way. Coherent is stronger at the systems level and is working to catch up on the component side.

Third, China. New entrants are bringing on large amounts of capacity, mostly in lower power lasers. Lumentum ran the comparison internally and found materially higher yields in its finished transceivers using its own lasers, with better spec uniformity unit to unit and better reliability in testing and in the field

Thoughts:

The power argument is the one we believe. Making high-power lasers is hard and few companies can do it well. But saying you win at the top end also admits you may lose at the bottom. We can live with that, because newer designs need more power, not less.

The telecom history is the weakest argument. Surviving 25 years in a rough industry is real, but it says more about the past than about today. Broadcom and Marvell have plenty of money, and they don’t need the best laser in the world. They only need one that is good enough to put on their own chip.

The China comparison came from Lumentum’s own lab. They tested their lasers against Chinese ones and said theirs came out better. That may well be true. Nobody outside the company has checked it. And Chinese suppliers can close the gap over time. China has shown this so many times.

PhotonCap comment: A product map for readers, because reading Lumentum as an EML company misses half of this article. An EML integrates two things on one InP die: a DFB laser that generates light and an electro-absorption modulator that blinks that light into data. It is a finished modulated source, and today’s 800G and 1.6T pluggable transceivers hang off it. That is the line that is sold out right now. A CW laser is the opposite: it supplies unmodulated continuous light, and a modulator on a silicon photonics chip does the data. That is the external light source for CPO and SiPh transceivers, and the high power line built for Nvidia sits here. In short, EML is today’s cash flow and high power CW is the next mix shift. The figure below shows the structural difference.

Figure 2: Two Ways to Put Data on Light. Figure: PhotonCap x Aurelion

Figure 3: SiPho Light Source Architecture Evolution. Figure: PhotonCap x Aurelion

AR: Looking three, five, even ten years out, and thinking about how compute gets organised as a whole, which of Lumentum’s core competencies prevails? Indium phosphide lasers, MEMS, or coherent optics?

Answer: Indium phosphide laser chip manufacturing first, and she was not close on the ranking. She frames it as architecture agnostic. Customers cannot escape needing photons, and those photons will most likely come from indium phosphide whatever the design. Link counts grow either way, which makes it a high growth market. There is a VCSEL branch on the roadmap if chip-to-chip photonics moves that way, though she still expects indium phosphide to be the answer.

MEMS and optical switching second, and she expects it to become another pillar. It already handles spine replacement and cluster scale-out for Google, and it is a high volume opportunity. Being a systems supplier is new territory, although the telecom wavelength switching business is a more complicated cousin of the same problem. The form factor is much larger than telecom, which raises the reliability and performance bar.

Thoughts:

Her point about not caring which design wins is a good answer to the fear that Lumentum gets cut out. However the industry builds these systems, someone still has to make the light. That job is theirs.

She also brought up VCSELs as a backup plan for chip-to-chip links, without us asking. Worth noting she raised it on her own.

The part she left alone: her two strongest areas carry very different risks. The laser chip business works no matter how the systems are designed. Optical switching does not. It depends on which design wins, and the customer base is thin. Google is the risk there.

PhotonCap comment: “A VCSEL branch on the roadmap” is weaker than the reality. Lumentum has manufactured GaAs VCSELs at consumer volume for smartphone 3D sensing for years, with more than 10 billion emitters shipped per company disclosure. At OFC 2026 it showed that base extended to AI: a 1060nm VCSEL and photodetector 2D monolithic array co-packaged with a host ASIC, targeting slow and wide scale-up protocols such as UCIe and PCIe, with operation above 150°C and channel sparing. So what sits on the roadmap is not VCSEL technology. It is commercial adoption in AI chip-to-chip links. The materials angle matters too. VCSELs live on GaAs, not InP, which means Lumentum holds three light source platforms at once: InP EML, InP high power CW, and GaAs VCSEL. That is a stronger architecture hedge than the paraphrase suggests.

Company Introduction: A Different Method of Connectivity

Lumentum is a photonics company that designs and manufactures hardware which senses, generates, switches, and modulates laser light. Lumentum’s core competency is fabricating semiconductor lasers on indium phosphide, a compound semiconductor that emits light efficiently where silicon, an indirect bandgap material, does not. This capacity is directed at numerous end markets, most prominently AI and data centers. Lumentum describes themselves as an industry leader in providing optical and photonic products. Their demand is driven by the expansion of networking capacity for cloud service, AI compute, and data center interconnect.

Inside a data center, countless GPUs communicate with each other to efficiently compute, sending large quantities of data to one another, which is traditionally done with copper wire. However, copper wiring grows energy inefficient at large lengths and high speeds, forcing a shift into optical solutions. Photonics, conversely, converts electrical signals into light and sends them over fiber. Lumentum makes the chip inside this light-based connection in the form of an EML (electro-absorption modulated laser). An EML pairs a continuous-wave DFB laser with an electro-absorption modulator built alongside it on the same chip. The laser itself runs continuously, and the modulator gates that light on and off billions of times per second to encode the data. Keeping the laser at constant output and modulating externally avoids the wavelength drift, or chirp, that comes from switching a laser directly, which is what allows an EML to hold signal integrity at high speed and over distance. It is also what makes an EML exceptionally difficult to manufacture.

Figure 4: Inside an Optical Transmitter Module. Figure: PhotonCap x Aurelion

Figure 5: Lumentum EML product family. Source: Lumentum

They currently hold roughly 60% of the EML market, and are one of the only, if not the sole, supplier of the highest speed version at volume. Revenues have nearly doubled year over year, with margins swinging positive. Nvidia has invested $2Bn in Lumentum convertible preferred stock and has a standing purchase agreement with them. Lumentum has moved upstream from a component vendor to becoming vertically integrated into a components and systems company, with components (laser chips) accounting for roughly 65% of revenues, and systems (transceivers, optical switches, MEMS) accounting for the remaining 35%.

Figure 6: One Company, Four Light Platforms. Figure: PhotonCap x Aurelion

Implications for the AI Trade

Investor sentiment about the AI trade has largely been centered on compute, principally GPUs and memory. However, a cluster of GPUs borders on useless if they cannot communicate with one another quickly and efficiently, because at the scale model training and inference run, a single chip is massively insufficient for a model. Lumentum satisfies this need, connecting GPUs with light. Lumentum’s recent performance serves as a signal for the broader infrastructure buildout, in that their revenues have grown significantly both through higher volume, and elevated ASP with a mix-shift to 200 gig-per-lane speeds. This tells us:

1) The compute bottleneck is not solely concentrated in memory. There are shortages in areas that are multiple orders of magnitude removed from direct token generation.

When thinking about a cluster of GPUs dedicated to AI, the two high-level jobs are compute, and intra-GPU communication. The numerous GPUs that define the cluster need to remain in constant communication to split compute across them. The first two or so years of the AI trade centered around the actual computation needs, with the first constraints being GPUs, then memory, and then power and advanced packaging. While some of these bottlenecks, mainly memory, still persist, sentiment has since moved to a new constraint. Specifically, much of that sentiment has shifted to optics in recent months. Lumentum signals that this bottleneck is real and possibly persistent because its laser chip business has grown both in volume and pricing, which shows that demand is outpacing the physical ability to manufacture the product. Lumentum is the leading provider of indium phosphide chips, which is considerably more difficult to work with than silicon. Lumentum is currently optimizing the number of bits you can transfer per square area of indium phosphide. In an ordinary market, capacity expansion almost always leads to lower ASP. However, Lumentum, by optimizing for more complex and efficient optical technologies, may actually continue to see ASP increase as customers mix shift to newer chips. This is a bullish signal for the AI infrastructure buildout and hyperscaler capex.

2) The optics thesis depends on compute domains growing. It is not fully dependent on a large-scale copper shortage.

Common sentiment around optics use stipulates that copper eventually fails to function or runs out of supply, which then forces migration over to optics, making demand robust. We see this, however, as a slightly misguided mechanism. Jensen Huang, CEO of Nvidia, framed copper as being used for scale-up, and photonics for scale-out, and Broadcom has said that optical scale-up is not quite there yet. This is despite Nvidia’s vast investments in Lumentum and Coherent, while also saying there is a need for copper capacity. With the ongoing rollout of Nvidia’s Vera Rubin GPUs and CPUs, we may begin to see a deepening of constraints outside of just distance or power per meter. Rubin relies on bi-directional signaling to reach its bandwidth targets, and bi-directional signaling over copper degrades substantially at 448G per lane. There is an unknown time-to-market for 448G per lane copper, but optics can scale along modulation, fiber count, and wavelength multiplexing. This means that Kathy’s response to six-meter copper claims is actually directed more at a cost curve based on engineering capabilities rather than a physical wall.

There is a durable source of demand for optics based on the growth of compute domains, meaning the number of GPUs that must operate as one coherent unit. These domains are rapidly outgrowing what copper can serve. Nvidia has begun moving from 72 GPU domains toward as many as 576 by 2027, and copper is already confined on an NV72 rack. Once a domain encompasses multiple racks, linking must be optical regardless of copper’s current efficiency. Thus, the optics thesis necessitates that AI systems continue scaling, not only that copper hits a wall or that 448G copper becomes unattainable. So, as CPO is anticipated to scale up in FY27 or FY28, it can do so in parallel with copper and still see commercial success.

3) If intelligence begins to commoditize and open source models continue to improve, value migrates away from frontier labs into infrastructure, but within infrastructure it does not concentrate evenly.

The cost per unit of model intelligence is persistently decreasing, especially with new open source releases like Kimi K3 and Grok 4.5. If demand for tokens is elastic, which we posit it is, then consumption rises faster than price falls. So, more competitive cheaper-per-intelligence models increase aggregate demand for compute while moving margins away from frontier models. Models would, in this case, become increasingly commoditized, with high competitive pressure and low switching costs. Combined with open-weight models compressing pricing, value migrates toward layers that depend on physical scarcity. This is a widely held conclusion, however, it is normally left at a high level.

Infrastructure is a multi-layer portion of the value creation chain, including power generation and grid capacity, chips, interconnect, and more. Leading edge foundry capacity is arguably the most scarce layer in the entire supply chain, with TSMC being effectively the sole frontier supplier. HBM is also constrained across 3 global suppliers, and behaves as a commodity, with more capacity expected to come online within the next 18 to 24 months. Optical and photonic components are currently in a similar position to memory in terms of viable suppliers and industry barriers to entry, given the underlying material science in indium phosphide fabrication and reliability requirements. However, training is the most communication intensive workload, and the way that optics have traditionally traded is around training economics. Inference is less network intensive, or at least has been historically, so a mix shift toward inference does not translate to a 1:1 demand for optics. But, as inference architecture evolves, this gap may close with things like longer context windows, more intense routing, disaggregated prefill and decode, and higher agentic usage. Inference is also more geographically distributed, which will drive more data center interconnect, regardless of cluster-to-cluster linkage. Optics at large are insulated from model commoditization, because they benefit from bits moved rather than tokens generated across infrastructure.

PhotonCap comment: This gap is already closing. The joint inference solution AMD and Cerebras announced in July is the live example. Helios handles the front half, reading the prompt, and Cerebras handles the back half, generating the answer, so work in progress crosses a network between two machines. What that link is made of has not been disclosed. So this is evidence that inference moves a lot of data, not evidence of any vendor’s revenue. PhotonCap covered the architecture in Same Split, Opposite Directions: Where NVIDIA and AMD Cut the Rack Decides Where Optics Gets Paid, and the data center to data center demand in this paragraph is the axis covered in One Layer Below SemiAnalysis’s Meta Map.

4) Chinese competition is unlikely to be a factor in the near term, though this is the point on which we hold the least conviction.

Chinese competitors do persist, and their technologies currently lag on yield and high-power production. As compute demands skew in favor of energy efficiency, using potentially unreliable Chinese hardware is not particularly viable. Furthermore, with strict import restrictions and bans among US companies demanding compute, Chinese hardware is unlikely to see significant uptake over domestic producers in the near term. We hold this view with less conviction than the three above, and treat it as a live risk rather than a settled question. The evidence supporting Lumentum’s yield advantage is entirely management’s own internal comparison, and Chinese EML production is progressing faster than the near-term view assumes. We set out that counter-argument in the bear case below.

PhotonCap comment: The actual technical point deserves sharpening. The moat is not peak power. It is qualified usable power at operating temperature, multiplied by spectral quality, reliability, and high volume yield. Four terms make the picture concrete. RIN is the small flicker in a laser’s output; with PAM4, which encodes data in four brightness levels, too much flicker makes the receiver confuse levels. COD is catastrophic optical damage, the failure mode where a laser’s own light burns its output facet, and it is the wall you hit first as power climbs. SMSR measures how cleanly the laser emits one wavelength versus stray ones. FIT counts failures per billion device hours; with millions of lasers in a data center, even a slightly high FIT means something dies every day. The point is this. Headline specs are what challengers close first. Distribution tails, noise, and lifetime statistics close last, because they take volume learning and years of field data rather than design. Lumentum’s claimed edge sits exactly there, and for the same structural reason it cannot be externally verified yet.

Bull and Bear Debate

Figure 7: The Lumentum Debate, four bull arguments and five bear arguments with evidence status. Figure: PhotonCap

LITE stock currently sits about 20% below its all-time high. Sellside coverage is roughly split, with shops like TD Cowen cutting its price target to $800 from just over $990, while UBS re-affirmed a hold and Citi reiterated a buy with a $1,100 price target, opening a catalyst watch. Other price targets range from $900 to $1,400 on the sellside. Before looking at the bull and bear cases, it is worth understanding that most of the photonics supercycle has been realized and played out, as photonics stocks at large have seen earnings increases and re-rates over the past 52 weeks. So, the relevant debates revolve largely around the future state of shortage, pricing, and CPO scale-up.

The Bull Case

Folks long Lumentum tend to believe:

1) The shortage is worsening and will continue to do so as compute scales up

Components and laser chips are effectively sold out, as are most chips, while wafer fabs take years to come on line. Management has described this supply and demand imbalance as roughly 30% greater demand than is physically suppliable, which is forcing premium pricing in the near to mid term, and full wafer allocation. Japanese wafer fab capacity is at a premium and fully allocated, while laser chip shipping has more than doubled in volume year over year. A McKinsey study also projects 800G transceiver production falling short of demand by about half in FY27, with shortfalls extending through 2029.

2) Pricing is contractually locked in and skews in favor of Lumentum through FY27

All EML capacity is locked in long-term agreements (LTAs) through FY27, and customers coming back for more than their LTAs cover must pay premium prices, while customers who do not sign LTAs risk losing their entire allocation of supply. General analysts expect double digit price increases in 200G EMLs in FY26 given the lack of second source supply.

3) Optical scale-up is not modeled into short-term consensus and is a second S-curve into which you can buy

LITE’s current business is predicated on scale-out, but management describes scale-up as a game changer that would expand their TAM. They expect first scale-up shipments for CPO in late ‘27. This was also confirmed by what Kathy told us on our call. The bulls see this as incremental TAM on top of a business that is already sold out of supply capacity.

4) CW lasers for CPO are ramping harder than consensus models

This thesis point rebuts the chip selloff in June, and the argument originates with Global Semi Research, who published a direct response to the SemiAnalysis note on June 10. Their supply-chain checks put Nvidia’s guidance to Lumentum and Coherent for high-power continuous-wave lasers at roughly 40MM units in January, rising to roughly 100MM by April and May. That pulls demand forward and back-solves to CPO switch shipments of roughly 200,000 to 300,000 in 2027, scaling toward 600,000 to 800,000 in 2028. It also lines up with TSMC’s COUPE (Compact Universal Photonic Engine) plan. These are channel figures rather than company disclosure, so we weight them accordingly.

The Bear Case

1) Coherent’s 6 inch wafer is a deeply underappreciated competitive threat

Coherent’s competitive product is its 6 inch indium phosphide wafer line. By switching from 4 inch to 6 inch wafers, Coherent produces roughly 2.25 times the usable area per wafer, yielding more laser die at a lower cost per die. Lumentum still runs 4 inch wafers and is trying to catch up. If Coherent’s 6 inch yield closes the gap on Lumentum’s 4 inch performance, this deeply undermines Lumentum’s pricing power. Lumentum even framed its own competitive advantage as bits per square area of indium phosphide, so a competitor with more than twice the usable area per wafer makes direct headway on that metric. Coherent’s indium phosphide lasers are also sold out through 2027.

2) Timing CPO shipments is a risk because they may get delayed

SemiAnalysis published a report to institutional clients on June 9, 2026, arguing that scale-out CPO shipments would be revised down through FY27 and push scale-up to FY29. This implies that the photonics bottleneck trade is over-crowded and disconnected from reality, which caused a relatively violent selloff in June and is one of the most monitored aspects of the bear case. They stated that CPO output is driven by a single ASIC that is very limited, and that ASIC integration is difficult with challenging underlying economics in its current state.

PhotonCap comment: This risk needs splitting by cause. If CPO slips on ASIC or packaging integration while bandwidth demand keeps growing, demand does not disappear. It stays in pluggables longer, and pluggables are EML intensive, which is the line that is sold out today. An integration driven delay pushes CW and ELSFP revenue out while extending the EML cycle. If the delay instead comes from a broader AI capex slowdown, both architectures get hurt. There is also the other side of the same coin. The cannibalization question the call sidestepped, whether CPO eats into the roughly 35% of revenue that is transceivers and systems, flips into a cushion in the delayed CPO scenario. The ladder below shows why: CPO is one rung, and a delayed rung keeps traffic on the rung beneath it. The June selloff punished the whole optical complex without this distinction, which PhotonCap covered in There Is No Such Thing as a ‘CPO Stock’.

Figure 8: The Optical Architecture Ladder. Source: PhotonCap, DSP, LPO, NPO, CPO: The Four Optical Architectures

3) Chinese EML production is progressing fast, and may soon catch up with domestic production qualit

Chinese companies, like Zetta Semiconductor, announced mass production quality EML systems across a variety of types and wavelengths in late 2025. This shows that there are foreign players that have the production capacity and specialization to play in the photonics market. However, getting past US regulatory structures and import restrictions will be difficult. The main battleground for these technologies will likely be in the EU among non-US companies.

PhotonCap comment: Zetta no longer fits either box, not the low power dismissal and not the imminent catch-up call. On public record it announced a mass producible 100G PAM4 EML at OECC 2025 and followed with a 200G per lane device at ACP in November 2025. Device level performance deserves to be taken seriously now. The open question is exactly the logic in the PhotonCap comment above: can it hold the full spec distribution across operating temperature and lifetime, and do unit-to-unit variation and noise behavior like RIN survive hyperscale qualification. That gets proven by years of volume data, not by announcements. PhotonCap covered how profits split between chips and modules in the Chinese optical ecosystem in Chinese Optical Modules Own 7 of the Top 10 Seats.

4) Lumentum capacity should come online in 2028, which may hit a different market

Two new sources of indium phosphide capacity are coming, and they are separate projects. The first is Greensboro, North Carolina, bought from Qorvo and being converted from gallium arsenide to indium phosphide as Lumentum’s fifth indium phosphide fab. Management guided revenue contribution to roughly six quarters out from the May call, which puts it in late 2027 at the earliest. The second is the new U.S. facility funded alongside the Nvidia investment, which is a ground-up build rather than a conversion. However, capacity commitments are being baked into current contracts at peak pricing against volumes that do not arrive for at least another 18 months. LITE is expanding EML production by 40% annually, but if volume growth decelerates by the time new capacity comes on line, Lumentum’s operating leverage will work against them on a substantially larger operating asset base.

5) Customer concentration is high, and they are deeply entangled with Nvidia

Two LITE customers accounted for 26% and 12% of revenues in fiscal Q3 2026. Nvidia is a large customer, shareholder, and owner of rights to future capacity. These roles are fundamentally unaligned, and its position as a buyer is economically larger than its investment stake, so its incentives skew toward price discipline rather than support. Capacity rights also cause tension among other customers whose supplier is entangled with a competitor that has claims on output.

PhotonCap comment: Concentration is a snapshot. Addressable demand is wider. Every camp pursuing CPO needs high power light. AMD’s rack scale expansion creates EML, CW, and pluggable demand. Broadcom is a potential customer and at the same time a platform competitor with its own laser sources. Marvell can be a buyer, an ecosystem partner, and an integration layer competitor all at once. Absent a disclosed design win, though, these are demand paths, not confirmed customers. The reverse direction is also on the public record: second sourcing is in progress, not a hypothesis. NVIDIA’s technical blog names three ELS vendors, Lumentum, Sumitomo, and Coherent. The same day Lumentum got its $2B, Coherent got an identical $2B. Coherent’s OFC 2026 release formalizes its 6 inch InP ramp and a 400mW CW laser, and AAOI announced sampling of a 400mW narrow linewidth laser in December 2025. The time axis is what matters. Competing capacity lands outside the FY27 LTA window, which is exactly where the 2028 capacity argument above picks up.

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Disclaimer: This article is a joint publication. The management meeting and investment analysis were prepared by Aurelion Research, and the technical comments by PhotonCap. All content is based on publicly available information and the authors' notes, and is provided for educational and informational purposes only. Nothing herein constitutes investment advice or a recommendation to buy, sell, or hold any security. Interview responses are paraphrased and do not represent verbatim statements by Lumentum or its management. The authors may hold positions in securities discussed. Readers should conduct their own due diligence before making any investment decisions.

Abstract

NVIDIA cut inside the decode loop. AMD and Cerebras cut between prefill and decode. $NVDA’s own documentation says the Rubin GPU and the LPX rack trade intermediate values on every output token, while $AMD and Cerebras have disclosed nothing about how data moves between their two machines, or over what physical link. Both carry the same label, inference disaggregation. But change where and how often that data moves, and the split of revenue between copper, plug-in optical modules, and switch-integrated CPO changes with it. This piece sorts the disclosed connection specs from the blank spaces, grades the evidence, and narrows down which disclosures would change the exposure of $COHR $LITE $MRVL $AVGO, and in which direction. My conclusion is one notch narrower than “optics wins either way.” The total volume of optics probably grows. Whether that revenue lands in modules, external lasers, CPO optical engines, or switch silicon is decided by where, on each link, light gets created and turned back into electricity.

Contents

1. NVIDIA in December, AMD in July

2. Why One Rack Isn’t Enough

3. They Wrote Down Everything Except the Wire

4. AMD’s 2 Pieces + NVIDIA’s 5

5. Once per Request, Once per Token

6. Inside the Rack: Copper This Far

7. Outside the Rack: Which Kind of Light

8. Not the Link, the Ends of the Link

9. Where Copper Steps Back

10. Scenarios and Monitoring

11. References & Sources

1. NVIDIA in December, AMD in July

NVIDIA’s Groq 3 LPX rack is designed to trade data with the GPU rack next to it every time it produces an output token[1]. AMD and Cerebras split prompt processing and token generation across two entirely different machines[2]. Both camps carved inference into two engines, but they carved in different places, and while NVIDIA’s documents spell out the rhythm of the exchange, AMD’s disclose nothing about the movement at all. The problem: neither company has said what actually connects those racks.

The timeline runs like this. On December 24, 2025, NVIDIA signed a non-exclusive inference technology license with Groq and brought over key personnel including the founder[3]. Neither company disclosed a price; CNBC, citing an investor, reported roughly $20B in cash[4]. Three months later at GTC 2026, NVIDIA unveiled the Groq 3 LPU as the seventh chip of the Vera Rubin platform, presented in a configuration where an LPX rack carrying 256 of these LPUs sits right beside NVL72[1].

Seven months after the license, on July 23, 2026, AMD delivered its answer in the same direction at Advancing AI 2026: a partnership that pairs Helios racks with Cerebras’s wafer-scale chip for ultra-low-latency inference[2]. Two companies that sell GPUs, roughly seven months apart, both put a crack in the same premise, that one kind of GPU rack handles all of inference best.

Not a coincidence. Behind both announcements sits the nature of the inference workload itself. And inside the difference between them, where each camp cuts the rack, sits the question of which segment of optical component demand shows up over the next few years. Why the same split points in opposite directions is the subject of this piece.

2. Why One Rack Isn’t Enough

An AI model produces an answer in two phases. Reading and understanding the question and its context from start to finish is prefill. Generating the answer one word at a time on top of that understanding is decode.

In restaurant terms, prefill is reading the whole order ticket and the recipe at once, and decode is sending out plates one at a time. The reading job favors a big refrigerator that can hold a lot of ingredients at once. The plating job is decided less by fridge size than by how fast the cutting board within arm’s reach can go. Map that to silicon and the fridge is HBM, the board is SRAM. HBM holds hundreds of gigabytes but lives off-chip; SRAM holds only hundreds of megabytes but sits on the die itself, so access is far faster.

To be a bit more precise: prefill chews through a long input in parallel, so compute throughput and HBM capacity are what matter. Decode advances one token at a time in sequence, so per-token data movement and latency are what matter. And the actual division of labor is not as clean as “GPU reads, LPU speaks.” Exactly where the cut lands, and what crosses that cut how often, differs between the two companies, and that difference is the entire paid section of this piece.

NVIDIA’s official material uses this split as-is. The Rubin GPU takes prefill and part of decode on its large HBM, while the LPU takes the latency-sensitive stretch inside decode on 500MB of SRAM per chip and 150 TB/s of on-chip bandwidth[1]. One LPX rack carries 256 of these LPUs, for 128GB of combined SRAM and 40 PB/s of combined on-chip bandwidth[5].

Figure 1: Prefill vs decode, the big fridge (HBM) and the fast cutting board (SRAM)

The natural next question: why not just make HBM faster? The reason it doesn’t work is physics. However close it gets, HBM sits outside the chip, across the interposer (the intermediate substrate that carries the chip and its memory). The distance signals travel through package wiring and the ceiling on pin count mean that raising bandwidth requires more stacks or faster pins, and both bill you in power, heat, and yield. SRAM sits on the same silicon as the compute units, so its cost structure is simply different. This capacity-for-speed trade is not the kind of constraint that process shrinks dissolve, and as we saw in Three Routes Around the Memory Wall, the industry has been engineering detours around it. Rack disaggregation is the most radical form of that detour. When the problem won’t yield inside the chip, you split the machine.

What matters here is that this division of labor is hardening into a hardware purchasing unit, not a software scheduling trick. Not time-slicing inside one rack, but standing up a separate rack filled with different silicon right next door. And once racks split, something has to connect them. That “something” is the rest of this piece.

The way system composition itself changes as workloads move from training to inference to agentic is exactly the diagram from the April piece.

Training vs Inference vs Agentic, the GPU:CPU ratio shift reshapes the system. Reused asset from the April piece

The prequel to this structural shift, how workload bifurcation split the chips across multiple foundries, is in The GPU era ran on TSMC. The inference era runs on multiple foundries. That piece was about who manufactures the chips. This one is about what connects the racks.

3. They Wrote Down Everything Except the Wire

Everything up to here is confirmed by NVIDIA’s and AMD’s own public documents. That inference racks are splitting, which chips go into each rack and how many, how much bandwidth one rack pushes: all of it sits in the manufacturers’ own materials.

Except the one line an investor needs most.

NVIDIA’s LPX technical blog states that the GPU rack and the LPU rack exchange data every time a token gets made[1]. The frequency and the mechanics are described in detail. What is not written anywhere in the document is the physical layer between the two racks, whether that data rides copper or glass. Same on AMD’s side: the spec of the connection between Helios and the Cerebras machine appears nowhere in the announcement[2]. This blank is also a spot the previous piece left open on purpose. Three Routes Around the Memory Wall flagged the disclosure of the interconnect between the two engines as the first data point that would update its middle-shell call, and that disclosure hasn’t come. So instead of waiting, this piece lines up what has been disclosed, segment by segment, and narrows the candidates for the blank.

The blank may look small, but the direction it gets filled rewrites the entire beneficiary list. If it’s copper, this is a connector and retimer market. If it’s light, the road forks again. Plug-in transceiver modules mean revenue for component makers like $COHR $LITE. CPO (co-packaged optics), where the optical parts get packaged onto the switch chip itself, shrinks the socket for plug-in modules on the switch side and redistributes the revenue across switch vendors, optical engines, and the external laser supply chain. If the four form factors are new to you, the whole ladder is laid out in DSP, LPO, NPO, CPO: The Four Optical Architectures and the Light Source Beneath Them All.

The first-order variables that pick copper versus light are distance, signal speed, and power. The meter or so inside a single rack is where copper is cheapest and most stable, and over short runs a direct copper link, with no conversion of electricity into light, can even win on latency. Past the tens of meters that cross a hall, copper’s signal loss stops being manageable and light is the only practical option. The problem is the awkward few meters in between, the next rack over, the next row over. In that zone, the traffic pattern does not pick the medium directly; it tightens the constraints. Occasional bulk traffic leaves you freedom in placement. A loop that never stops shrinks the allowable latency and the number of switch hops, which changes where you can even put the two racks.

Figure 2: Two traffic shapes between split racks. One bulk handoff per request vs a round trip every token, camps unlabeled

Rearrange the two companies’ public documents against those criteria, segment by segment, and you can close much of the blank: which segments are already locked to copper, which segments have which kind of light written down, and which segments are simply empty. At the end of that arrangement, one spot emerges where both camps converge. That spot is where the paid section begins.

Let me show you the paragraph itself first. This is the NVIDIA passage that says the two racks trade data on every single token. Read it to the end and it never says what the data rides on.

Screenshot: NVIDIA LPX technical blog excerpt. Source: NVIDIA Developer Blog, 2026-03-16

Key point: rack disaggregation is a fact settled by public documents. What is not settled is the physical link between the split racks, and the direction of that answer redraws the exposure map of the optical component names.

4. AMD’s 2 Pieces + NVIDIA’s 5

What NVIDIA unveiled at GTC 2026 was not two racks but a POD built from five kinds of specialized racks[6]. Forty racks, 1,152 Rubin GPUs, bound into one supercomputer, and the division of labor inside is what deserves the attention.

NVL72 is the compute engine. It binds 72 GPUs and 36 Vera CPUs over an NVLink copper spine (the bundle of links running vertically up the back of the rack like a backbone) and takes prefill plus the part of decode that decides which slice of context to consult, the calculation called attention[6]. Per NVIDIA, Vera Rubin has entered its full production ramp with partner systems being built and shipped, and broad availability is slated for the second half of 2026[6][7]. LPX handles low-latency generation, the 256-LPU configuration from above[5]. The Vera CPU rack runs up to 256 CPUs per rack, hosting 22,500 concurrent agent sandboxes[6]. BlueField-4 STX is the storage rack that offloads, stores, and serves context memory including the KV cache (the working memory a model piles up to remember the conversation so far)[6], and Spectrum-6 SPX is the networking rack that ties all of these together[6].

Extend the restaurant: kitchen (NVL72), speed line (LPX), front office (Vera CPU), pantry (STX), and hallway (SPX), five rooms carved out of what used to be one. The pantry is the one to stare at. The KV cache, the model’s record of “what I’ve read so far,” moves out of the HBM next to the GPU into its own rack and travels the network, which means memory itself becomes traffic that crosses rack boundaries.

AMD’s announcement is simpler. Helios stands as the high-throughput general engine, and only the latency-critical decode and token generation gets handed to Cerebras’s wafer-scale machine, a PD disaggregation structure that splits prefill and decode at the node level[2]. The joint configuration is expected to be available first through Cerebras Cloud in the second half of 2026[2]. The companies claim up to 5x higher tokens per second per watt for the combined setup, a vendor modeling figure comparing Helios plus WSE against a WSE-only configuration, not against Helios alone and not against an existing GPU rack[2]. No customer benchmark exists yet.

One thing to pin down before moving on. “Five versus two” is not a comparison drawn on the same boundary. NVIDIA’s five counts the entire POD by function, compute through storage through networking. AMD’s two counts only the inference compute path; an AMD deployment obviously has its own networking and storage infrastructure besides. What this piece is comparing is not rack counts but where the inference path gets cut. Read that location through a traffic lens and the camp with more pieces, NVIDIA, is actually the one carrying the tighter requirement. The next section explains why.

5. Once per Request, Once per Token

The two camps cut in different places.

AMD and Cerebras’s PD split cuts between prefill and decode. In a typical PD disaggregation, once the prefill side finishes reading the context, its output, the KV cache, gets handed to the decode side, and the cadence of that handoff is closer to per request than per token[8]. The left panel of the chapter 3 figure: a truck hauling goods from the warehouse to the storefront. That transfer is not free of latency, though. By the arithmetic in DistServe, the paper that formalized PD separation, the KV cache of a single 512-token request runs about 1.1GB, and serving 10 requests per second needs roughly 90Gbps, which is why bandwidth-aware placement is a design precondition; in its experiments, over 95% of requests completed the transfer within 30ms, and that cost lands on the wait for the first token (TTFT)[8]. AMD and Cerebras have disclosed nothing about their own implementation’s data movement or cadence, so this paragraph is PD disaggregation in general[2].

NVIDIA’s side is on the record. What the license[3] bought is Groq’s LPU technology, and AFD (Attention-FFN Disaggregation) is the name NVIDIA gave to the serving structure that pairs that LPU with a GPU[1]. This scheme cuts again, inside decode. The loop runs like this: the GPU computes attention over the accumulated KV cache and hands the intermediate values to the LPU; the LPU executes the FFN (the calculation that turns what was consulted into actual output) and the MoE experts (specialist sub-blocks that divide the labor inside the model) and returns the result to the GPU. In NVIDIA’s own words, this exchange repeats for every single output token[1]. The right panel of the chapter 3 figure: a ping-pong rally between two racks, one volley per word. Dynamo runs the orchestration, and NVIDIA’s own diagram draws the loop spanning both racks[1].

Same word, disaggregation, but the bill arrives at different counters. PD’s transfer cost lands mostly at the request boundary, the wait before the first token appears. AFD’s exchange cost sits inside the token generation loop, so its latency multiplies straight into the feel of every token. Aim at 1,000 tokens per second[1] and the entire cycle for one token, compute and communication combined, is about 1ms. The latency budget for a round-trip exchange has to be far smaller than that.

This is where distance enters. The deeper the exchange sits inside the loop, the closer the two racks must physically stand; the more the cost is paid at the request boundary, the more freedom you have in placement. Where you cut determines the traffic’s character, and the traffic’s character determines the latency budget and allowable distance. Medium selection is decided first by distance, signal speed, and power, and the repetition inside the loop then tightens the allowable latency and hop count further.

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On June 24, Qualcomm used its Investor Day to unveil HBC, an architecture that promises 133TB/s per card (vendor claim) with no HBM in it. Qualcomm presented Microsoft as its Azure deployment partner for HBC, while Meta’s name came attached to a separate multi-generation deal for the C1000 data center CPU. Around the same time, Nvidia put a LUT tensor core format that stores a weight in 3.125 bits into public documentation (the PTX ISA 9.4 developer preview) for the Rubin generation. The two approaches differ in direction but they are pounding on the same wall. The paradox, that every increase in HBM’s cost per byte improves the economics of designs that use less of it, has started showing up as hardware roadmaps and instruction sets. As I was wrapping this piece up on July 23, AMD and Cerebras announced a disaggregated inference partnership that splits prefill and decode across two different memory architectures, and on publication day itself, Samsung-Broadcom’s $200B+ MOU and SK Group-NVIDIA’s $500B+ LOI landed on top. This article audits the three bypass routes (distance, compression, pooling) one by one, and works out which direction each one pushes the DRAM makers and the optics timeline.

Related: $QCOM $NVDA $MU $AMD $CBRS

Contents

1. Intro: Hyperscalers Are Lining Up Behind a Company That Wants HBM Gone

2. Redefining the Memory Wall: Access Speed, Not Capacity

3. The Bypass Splits Into Three Routes

4. Route One, Distance: Auditing Qualcomm HBC

5. Route Two, Compression: Rubin’s 3.125 Bits

6. Route Three, Pooling: Why This Article Leaves It Alone

7. Stress-Testing the Samsung SiPh Thesis

8. The DRAM Makers’ Margin Mix Game

9. So When Does Optics Arrive

10. Scenarios and Monitoring

1. Intro: Hyperscalers Are Lining Up Behind a Company That Wants HBM Gone

A company declared it would take HBM out of the AI accelerator, and the CEOs of Microsoft and Meta showed up in its Investor Day program.

This was Qualcomm’s ($QCOM) Investor Day on June 24. The company laid out a data center roadmap with a target of more than $15B in data center revenue by FY2029 [1], and at the center of it sat an architecture called HBC, High Bandwidth Compute [2]. The idea is simple. Instead of HBM and an interposer, stack LPDDR directly on top of the accelerator die through TSVs. By Qualcomm’s own claims, a single AI250 card reaches 133TB/s, an 18x jump in effective bandwidth over the previous AI200 generation on LPDDR5X [2].

Whether those numbers survive contact with reality is a question for later (claimed and sustained performance are two different things, a principle I repeat every time a vendor announcement comes through). What matters first is the structural shift. Until now, “replacing HBM” lived in conference papers and startup slide decks. Now a top-tier semiconductor company is talking about it on an annual cadence roadmap, and hyperscaler names are attaching to it. The two names attach to different things, though, and they carry different weight. Meta’s side is a signed multi-generation deal, and its subject is not HBC at all but the C1000 data center CPU. Microsoft’s side is Qualcomm introducing the company as an Azure HBC deployment partner on the Investor Day stage [3], while Nadella’s own remarks read closer to an endorsement of the collaboration; Microsoft has disclosed neither deployment timing nor scale through its own channels. I will come back to this distinction, because blurring it means misjudging the size of the announcement. Most announcements these days work that way. The gap between the headline number and the actual scope of the contract is wide, and reading that gap is half the analysis.

A few weeks later, a move in a similar direction came from the opposite camp. The PTX ISA 9.4 document that Nvidia ($NVDA) released with the CUDA 13.4 developer preview carries a new tensor core mode for the Rubin generation (sm_107) [4]: a lookup table scheme that stores each weight as a 3-bit index rather than a value. The caveat is that this is still a preview document, not a GA release. The approach does not remove HBM. It shrinks the bytes you read out of it.

A third piece of hardware reality arrived on July 23, as I was closing this piece. AMD ($AMD) and Cerebras ($CBRS) announced a disaggregated inference partnership [5]. Prefill runs on HBM-based Helios racks, decode runs on the SRAM-based Wafer-Scale Engine (WSE). Two different vendors’ accelerators and memory architectures, announced as one joint inference solution. Availability starts in the second half of 2026 through Cerebras Cloud [5], and in that configuration, a single inference request travels between HBM and SRAM. SemiAnalysis, in its Advancing AI 2026 writeup published the same day as this piece, filed the deal as a strategy similar to the Nvidia-Groq arrangement [6], a sign that a shared pattern is forming across both camps rather than a single bypass.

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a month ago · 129 likes · 3 comments · Bryan Shan, Daniel Nishball, Myron Xie, Wega Chu, Ivan Chiam, Cam Quilici, Cheang Kang Wen, Kimbo Chen, Gerald Wong, Zane Fong, Jordan Nanos, and Dylan Patel

Different companies, different layers of the stack, one bottleneck in the crosshairs, and a roadmap, an instruction set, and a commercial partnership all inside 30 days. Why now, of all times?

Two good pieces have already covered this 30-day window. handled Rubin’s new tensor core from a benchmarking angle [7], and handled Qualcomm HBC from an incentive-structure angle [8]. Both are excellent, and neither references the other. One is an Nvidia piece and one is a Qualcomm piece, after all.

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Vera Rubin NVL72 vs GB200 NVL72? Inference TCO & Architecture Analysis

Vera Rubin NVL72 is the second generation of Nvidia’s rack-scale Oberon architecture, and its gains on inference come from extreme co-design. Early results from engineering samples are encouraging. Vera Rubin NVL72 running DeepSeek R1 delivers 5.4x performance per MW and 5x performance per dollar over GB200 NVL72 today, and the gap is even wider against GB200 NVL72 during its early bringup in 2025. Vera Rubin is still in the early bringup stage now, so we expect the gap to continue widen. Rubin's inference performance will keep improving as software matures, the same pattern we demonstrated for Blackwell in our…

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a month ago · 144 likes · 2 comments · Alec Ibarra, Bryan Shan, Daniel Nishball, Zane Fong, Cam Quilici, Kimbo Chen, Jordan Nanos, and Dylan Patel

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All Along the AI Watchtower

Bob Dylan wasn’t musing about artificial intelligence related capital expenditures when he wrote “All Along the Watchtower”. Still, he managed to summarize the AI value-accrual debate pretty well…

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a month ago · 289 likes · 4 comments · Citrini Semis

The framing that higher HBM prices raise the incentive for bypass architectures comes from the Citrini piece, and I first learned that Rubin carries a new tensor core mode from the SemiAnalysis piece. That much is borrowed. But reading the two side by side, something kept nagging at me. These bypass routes are different roads, so why does the same line item keep showing up at the end of every roadmap? And does the Samsung vertical integration thesis I laid out in an earlier piece survive this current? Neither article asks those questions, so I worked through them myself, recomputing the numbers from primary sources instead of either publication’s paid data. While I was at it, news kept piling up at a rate of one item every two days, so this piece includes things that broke on the morning of publication. I could not pick the timing, but the timing picked the material. Half of the writing turned into verification work as a result.

Key point: bypassing HBM is no longer a concept. In June and July 2026 it showed up as hardware: a roadmap ($QCOM HBC), an instruction set ($NVDA PTX ISA 9.4), and a commercial partnership ($AMD $CBRS), back to back.

2. Redefining the Memory Wall: Access Speed, Not Capacity

There is a principle this series keeps coming back to. The memory wall in LLM decode is an access speed problem, not a capacity problem. To be precise, that is the low-batch decode version of the story. As context grows and concurrent requests pile up, KV cache capacity climbs into the bottleneck too, and that branch gets its own treatment in chapter 6. (Previous piece: The Micron-Anthropic deal and the memory wall)

Figure 1: Compute FLOPs vs Memory Bandwidth Scaling Gap

Compute jumps every generation. The rate at which you can feed data into that compute does not keep up. The decode phase of LLM inference is where this bites hardest. In a dense model, producing each token means re-reading a large share of the weights (MoE reads mostly the active experts, so the total shrinks, but the character of the bottleneck, bytes per second, stays the same), and that is a job decided by memory bandwidth, not by FLOPs. The smaller the batch and the higher the interactivity requirement, the worse it gets. And with agentic workloads spreading, that is exactly the direction the market is demanding. An era that needs tokens fast, cheap, and nonstop is an era of decode, and decode’s bottleneck is the memory wall.

Think of a kitchen. Decode is a job where the chef (compute) spends most of the time fetching ingredients from the fridge (memory). However fast the chef’s knife gets, if the round trip to the fridge takes just as long, plates come out no faster. Over the past decade the industry doubled the speed of the chef’s hands every generation, while the fridge round trip did not manage half that pace. That is the memory wall. Hiring more chefs (adding compute) is not the answer. The plates are not late because of the knife work. Making the kitchen bigger (adding capacity) is not the answer to this particular problem either. The round trip is not slow because the kitchen is cramped. A bigger fridge (capacity) does not fix it. Speed up the trips, cut the number of trips per plate, or move the fridge next to the cutting board. Those three are the answers this article deals with. And all three share one trait: they get more serious as the fridge gets more expensive. The symmetry is worth remembering too. If fridge prices ever break, all three lose urgency together.

Figure 2: The Kitchen Analogy, the Memory Wall as a Round-Trip Problem

HBM is the current answer to this problem. Stack DRAM vertically, lay a wide bus through a silicon interposer, and buy your bandwidth that way. As answers go it has been excellent, and it remains the standard for frontier accelerators. It is also what drove the DRAM makers’ earnings and stock prices this cycle, and the reason this series has tracked advanced packaging all along. But the answer carries a price tag: silicon interposer and advanced packaging cost, power per stack, and above all, supply constraints. HBM is a product that only a few companies and a few lines can make, so when demand piles in, prices do not hold. And this cycle, demand kept piling in. Boil down two years of DRAM earnings calls into one phrase and you get sold out. The rule in this neighborhood is that the more successful the answer, the thicker its price tag gets. That thickened price tag is what you have been watching in the DRAM makers’ income statements. The very reason HBM became the biggest winner of the AI cycle is, to engineers, the incentive to find a way around it.

Let me say this up front: this is not an HBM-skeptic piece. HBM is still the most proven answer on the board. The question is about what comes next, the one created by that answer’s price. Problems born from an answer succeeding get solved differently than problems born from an answer being wrong.

High prices eventually summon their own cure. Usually the cure arrives as added supply. In semiconductors it can also arrive as a change of architecture. The higher HBM’s cost per byte climbs, the more relative value there is in a design that squeezes the same token out of fewer HBM bytes. Citrini Research flagged this incentive structure recently [8] (see Acknowledgment), and translated into this series’ frame it reads like this: if the diagnosis is right, if the memory wall is an access speed problem, then at the silicon and system level the fixes sort into raising access speed (the HBM road), cutting the bytes you must access (the compression road), or shrinking the access distance itself (the distance road). The model side has its own relief valves, GQA, speculative decoding, and so on, but this piece stays on silicon and systems. Each of those model-side techniques deserves an article of its own, and cramming them in here would do them no favors.

Key point: the HBM premium is itself the catalyst for anti-HBM design. If the problem definition (access speed) holds, the bypass narrows to three directions.

3. The Bypass Splits Into Three Routes

Figure 3: Three Bypass Routes Around the Memory Wall

The first route is distance. Cut or eliminate the distance data has to travel. This route is a spectrum, not a point. At the far end sits on-chip SRAM, memory placed inside the compute die itself (this is where Cerebras lives), and next to it sits Qualcomm HBC: LPDDR stacked in 3D on top of the accelerator, so data drops vertically through TSVs instead of crossing sideways over an interposer [2]. If HBC is moving the fridge next to the cutting board, SRAM is building the fridge into the board. Closer is faster, and closer is smaller. It would not be an exaggeration to say that trade-off is the whole story of this route. As we will see later, one commercial configuration announced this week demonstrates the trade-off like a textbook. Nor is it a coincidence that Qualcomm picked this road. This is a company that spent twenty-plus years getting squeezed by power and area budgets in mobile.

The second route is compression. Cut the amount moved rather than the distance. Rubin’s LUT tensor core lives here. Weights get stored in a low-precision format, but instead of plain rounding, a codebook-based non-uniform quantization gets reconstructed inside the MMA (matrix multiply-accumulate, the basic multiply instruction a tensor core executes) [4]. HBM stays, but the bytes flowing out of it shrink. This is not dodging the wall so much as lightening the load that hits it. It is also the next rung on the precision ladder that ran FP16 to FP8 to FP4, except this rung descends differently than the ones before it. How it differs is the subject of chapter 5.

The third route is pooling. Put another memory tier outside the accelerator and tie it in over an electrical interconnect like CXL. This route has a different character. In an era where long context and conversation history keep pushing KV cache out of HBM, the case for this warehouse gets clearer by the month. Where the first two routes attack bandwidth, pooling attacks capacity. Go back to the definition of the memory wall and this route is bypassing a different wall. As it happens, started attacking that wall head-on this week, with a series on solving the KV cache capacity bottleneck through CXL expansion. Their split, capacity expansion versus footprint compression, lines up with this article’s map: their capacity expansion is the same road as my pooling, and their compression differs only in target. They shrink the KV cache; the compression in this article shrinks weights. I read it as a signal that the industry has started drawing the same map independently. Overlapping maps mean the direction is no accident. But the overlap ends at the map. Who is standing on which road, and how much each claim actually weighs, is where things diverge. Vendor slides, public instruction sets, and letters of intent are three different grades of evidence, and weighing them is what the paid section of this article does.

TrendForce

Breaking the Memory Bottleneck Part 1: How CXL Unlocks the Memory Capacity KV Cache Needs

For most of the AI buildout, the scarce resource was compute. In 2026, the binding constraint has shifted to memory, and the pressure point is KV Cache, the working memory of inference. Its footprint grows with every extra token of context and every additional user in the batch, and in the first half of 2026, surging KV Cache demand coupled with limited memory supply resulted in severe memory bottlenecks…

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The three routes share a common backdrop. HBM pricing is what supercharged their economics. Each has its own drivers too, power, packaging capacity, latency, but if HBM cost half of what it does today, the gamble of stacking LPDDR on an accelerator, the acrobatics of packing weights into 3 bits, and the construction project of a separate warehouse would not be drawing this much investment. So the fate of these bypasses is not purely a technology question. It is also a function of the HBM price cycle. One DRAM price chart is enough to confirm the backdrop. You do not even need the chart; counting the recurring words in memory makers’ earnings releases will do. On the very day this piece goes out, two more announcements landed that cement that backdrop. Who got tied to whom, and what those ties mean for the bypass routes, gets sorted out later in the piece. Whether you buy DRAM or sell it, this map is not somebody else’s neighborhood.

That is as far as public information takes the map. But an investment decision needs more than a map. It needs an appraisal of each route. What conditions hang off Qualcomm’s 133TB/s? Where does the 3.125-bit figure come from, and how many percent of real HBM consumption does it actually remove? And above all, once the three routes have divided the workloads among themselves, what remains? The answers decide the DRAM makers’ margin mix, and they decide the timing of the package-level optics entry this series has been tracking. When the bypass grows, does optics get pushed out, or does it just change seats? I lean toward the latter, and the rest of this piece checks that lean one step at a time. The order: appraise the three routes, then set this series’ standing thesis on top of them, then come back to optics at the end. It is a long read, so if you are pressed, chapters 4 and 9 first, then circle back.

Let me show you one thing before the gate. Inside the very announcement that wants HBM gone, there is a section that looks like this.

Screenshot 1: Qualcomm Dragonfly press release, Connectivity section, original capture with highlights / file: qualcomm_connectivity_screenshot.png / caption: “Source: Qualcomm press release, Jun 24, 2026”

800G and 1.6T optical, AOC and AEC, all the way to coherent-lite DSP [2]. A company removing HBM from memory put an optical connectivity portfolio in the same document, as its own separate pillar. Why this list is there, and what it means at the point where the three roads end, is the subject of this article’s final chapter.

4. Route One, Distance: Auditing Qualcomm HBC

Figure 4: HBC Architecture vs HBM plus Interposer, Cross-Section View

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Abstract

Kimi K3, released July 16, is a 2.8 trillion parameter MoE model that activates 16 of 896 experts per token. Its active parameter count is estimated at roughly 50 to 60B (unofficial estimate, technical report not yet published). The trading day after TSMC reported a 77.4% jump in quarterly net income, its Taiwan-listed shares fell 7.3% and the US ADR $TSM fell 2.8%. K3 was less the sole cause of that selloff than a catalyst that amplified AI capex caution already in place. This article works through three calculations from K3’s spec: the memory its weights require (a theoretical floor of about 1.4TB at MXFP4), a KV cache baseline for its 1M token context, and the widening gap in large open-weight MoE models, where total parameters grew about 4x in 19 months while active parameters grew around 1.4x. The conclusion the public spec supports: K3 cuts per-token compute while raising memory and communication load at the same time. The article then maps that load to five supply chain exposure points: die, package, rack, campus, and test. This article is fully free.

Data cutoff: July 20, 2026. K3’s API and architecture overview are public, but the full weights and technical report are not yet released. Some figures, including the 50 to 60B active parameter count and the actual serving footprint, are independent estimates. Moonshot has stated the full weights will be released by July 27. License terms and exact configuration will be updated here once they are public.

Net Income Up 77.4%. The Next Trading Day, Down 7.3%

The trading day after reporting a 77.4% year-over-year jump in quarterly net income [1], a company’s shares fell 7.3% on the Taiwan exchange. That company was TSMC [2]. The same day, the US ADR $TSM fell 2.8% (NYSE close, 2026-07-17), SoftBank dropped 9%, the Nasdaq 100 slipped 1% intraday, and NVIDIA ($NVDA) briefly handed the largest market cap spot to Apple during the session [3].

No single cause explains that selloff. Caution around AI capex and valuations had been building for a while, and the earnings themselves, strong as they were, left cost concerns on the table [2]. But there is little disagreement that Kimi K3, the open model Moonshot AI released on July 16, was the catalyst that amplified it.

The catalyst’s logic is simple: if a frontier-class model becomes available through a low-cost API or downloadable open weights, the case for hardware spending appears to weaken. It is a familiar argument. The same selloff played out in January 2025 with DeepSeek.

And we already know how that experiment ended.

Summary: the logic behind the K3 correction is a rerun of the DeepSeek shock. That experiment already produced a result once.

The Experiment We Already Ran in January 2025

The selloff logic during the DeepSeek shock was “cheaper models mean lower infrastructure spending.” That equation never showed up in hyperscaler capex guidance afterward. You cannot claim the price drop directly caused spending to rise, but the direction was, at minimum, not the one the selloff priced in. What got cheaper was the model, not the infrastructure that runs it.

There is already a framework piece that organizes this structure: ’s analysis of open models and semiconductor demand. Its conclusion, in one line: open models do not shrink the hardware market. What gets compressed is the frontier model developer’s premium, and value moves toward hyperscalers and the semiconductor infrastructure underneath them.

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This article takes that frame as given. What it adds is a different question, worked out in numbers. What does one model like K3 physically require, and how much? And if models like this keep coming, where in the supply chain does that requirement land?

First, let’s separate what the official spec confirms from what is still an estimate.

Calculation 1: 1.4TB of Weights, and That Is the Floor

Here is what Moonshot’s official material confirms: 2.8 trillion total parameters, 16 of 896 experts activated per token, a 1 million token context window, and quantization-aware training from the SFT stage using MXFP4 weights with MXFP8 activations [4]. The active parameter count per token is not in the official material. estimates it at roughly 50 to 60B [8]. A simple 2.8T x 16/896 calculation produces about 50B, but that arithmetic assumes the parameters are spread uniformly across routed experts. In reality the 2.8T total also includes always-active attention, embeddings, routing, and shared components, so the correct expression is common parameters plus 16/896 of the routed-expert parameters. Because Moonshot has not disclosed the split between common and routed-expert parameters, the exact active count cannot yet be calculated from the official specification (unofficial external estimate).

Start with the memory the weights require. A naive conversion at 4 bits per parameter gives 2.8T x 0.5 bytes = about 1.4TB. That number is not a conservative estimate. It is a theoretical floor: raw payload with scale metadata, alignment, and communication buffers stripped out. The actual serving footprint is larger. At FP8-class precision, the figure is 2.8TB.

Put that against the nominal capacity of the current top accelerator and the scale becomes visible. NVIDIA’s Blackwell Ultra (B300/GB300) carries 288GB of HBM3E per GPU [7]. Dividing nominal capacity alone, 1.4TB is 5 GPUs’ worth and 2.8TB is 10. That is not a minimum deployment count. KV cache, activations, and parallelism overhead stack on top, and as we will see, Moonshot itself recommends a much larger configuration. Scaled to a GB300 NVL72 rack of 72 GPUs, nominal rack HBM is 72 x 288GB = about 20.7TB [7], and one copy of K3’s FP8-class weights occupies more than 13% of it as a resident.

Compare with the previous generation and the slope shows. Kimi K2 was 1.04 trillion total parameters [5]. Total parameter count grew 2.7x in twelve months.

This article’s title comes from here. The routed experts selected per token are 16 of 896, a ratio of 1.8% [4]. That ratio does not equal 1.8% of total FLOPs. Attention, the router, and shared paths keep their own compute. But the structure is clear. The model limits the active parameter set to an estimated 50 to 60B per token, yet because the router can call any expert on the next token, a high-throughput serving system needs all 2.8T weights reachable at low latency, in accelerator memory or a tier close to it. Offloading or caching some experts elsewhere is possible. The price is latency and throughput.

A library analogy helps. Active parameters are the books open on the desk for this one token. Resident weights are every book that has to stay on the shelves. Only 16 of the 896 librarians are working, but since nobody knows which one the next visitor will ask for, all of them have to sit in the waiting room. Compute cost tracks the 16 at work. Memory cost tracks the size of the room.

Figure 1: The K3 asymmetry, 16 of 896 routed experts activate per token while the full 2.8T parameter set must remain rapidly accessible

Investment read: 16-of-896 routing sparsity limits the active parameters per token, but the serving system still needs low-latency access to all 2.8T weights. With actives growing far more slowly than totals, the bottleneck’s center of gravity expands from compute alone into a system problem spanning memory capacity, bandwidth, and interconnect.

Weights, though, are half the serving memory story. The other half is created not by the model but by usage.

Calculation 2: KV Cache, the Second Memory That Usage Creates

K3’s context window is one million tokens [4]. Context carries a memory cost: the KV cache, which stores the attention keys and values of every token the model has read.

One thing to be clear about first. The calculation below is not K3’s actual KV memory. It is a counterfactual baseline: what K3 would look like if it were a standard GQA attention model. In a standard architecture, KV cache size is roughly 2 (K and V) x layers x KV heads x head dimension x context length x precision. Assume a typical frontier-scale configuration (author estimate: 60 layers, 8 GQA KV heads, head dimension 128, FP8) and a single 1M token session comes to about 123GB. That is over 40% of one B300’s nominal HBM, occupied by a single user’s conversation.

K3’s actual memory requirement is likely lower than this standard-GQA baseline. K3 is a hybrid attention design combining KDA (Kimi Delta Attention) with Gated MLA, and KDA exists precisely to cut this cost [4]. The size of the reduction cannot be calculated until the layer mix and state structure are disclosed.

Line up what the labs chose and the direction converges. DeepSeek compressed the KV cache with MLA [6]. Moonshot rebuilt attention itself with KDA. MoE sparsity cuts per-token compute, and MXFP4 quantization-aware training cuts bits per parameter [4]. Nearly every frontier architecture improvement of the past two years points the same way: not adding FLOPs, saving bits. Watch where the labs concentrate their engineering and you can read where the bottleneck sits.

KV has one more property that weights do not. Weights are a fixed cost per serving replica. KV and state are a variable cost that grows with active sessions and context length. They scale with usage, not with the number of models. The pattern so far: each time compression lowered the per-session cost, longer contexts and more concurrent sessions filled the space it opened. There is no guarantee the pattern holds. But what happened right after K3’s launch, as we will see below, was at least not the opposite.

Summary: under a standard GQA counterfactual, one 1M token session is about 123GB (author estimate). K3’s actual figure is likely lower, but the reduction cannot yet be quantified. Still, the fact that architecture work keeps converging on memory tells you where the bottleneck sits.

Calculation 3: Totals Grew 4x. Actives Grew About 1.4x

How many more models like this are coming? The sample here is not all open models. It is the largest open-weight MoE snapshot at each point in time. Dense models and small MoE are not in this sample.

December 2024, DeepSeek-V3: 671B total, 37B active, a 5.5% activation ratio [6]. July 2025, Kimi K2: 1.04T total, 32B active, 3.1% [5]. July 2026, the same weekend Moonshot shipped K3 at 2.8T, Alibaba introduced its 2.4 trillion parameter Qwen3.8-Max-Preview with an open-weight release planned [9]. Take K3’s active parameters at Ken Huang’s 50 to 60B estimate [8] and its activation ratio is 1.8 to 2.1%.

Over 19 months, total parameters grew 4.2x while active parameters grew 1.35 to 1.62x on the estimate range. The activation ratio walked down from 5.5% to 3.1% to around 2%. Back in the library, the shelves grew 4.2x over 19 months while the librarians on duty grew about 1.4x. Each generation grows the active parameter set far more slowly than the total parameter count, while the parameter set that must remain reachable keeps growing. This gap is the most important chart in this article.

Figure 2: Total vs active parameters, selected large open-weight MoE snapshots, Dec 2024 to Jul 2026

Three forces push the trend: compute constraints, competitive density, and self-hosting.

Compute constraints first. Sparsity is the cheapest way to scale model size in a compute-scarce environment. Reuters notes that US export controls have made access to computing power a key constraint for China’s AI developers [9]. When FLOPs are hard to secure, a sparse MoE that runs a bigger model on the same compute is less a choice than a forced direction. What the controls aimed to block and where demand actually grew sit in different places. Squeeze the compute, and the architecture grows toward memory.

Competitive density. It is no accident that Alibaba shipped a 2.4T model the same weekend K3 arrived [9]. Everyone from the large platforms down to startups like DeepSeek and MiniMax is in the same race [3], and a race on total scale has no incentive to stop.

Self-hosting. Moonshot has stated the full weights will be released by July 27 [4]. There is no official license announcement yet, so the actual self-hosting terms need confirming after release. If the weights land as planned, the serving infrastructure demand that has so far lived inside frontier labs gets recreated in enterprises, governments, and sovereign clouds. Everything that closes the gap between “can download a 1.4TB model” and “can run it” is hardware spending.

And just before this article went out, the most direct data point on this logic arrived. On July 19, Moonshot paused new subscriptions, saying K3 demand had approached the limits of its existing clusters within 48 hours, and allocated available compute to existing paid users [9]. A signal pointing in the exact opposite direction of “cheap open models reduce infrastructure demand,” and it came from the company that built the model.

Summary: totals up 4.2x, actives up around 1.4x. As long as that gap holds, incremental demand shifts disproportionately toward memory capacity, bandwidth, and interconnect. Not away from compute, but beyond compute alone. And the company that built the model paused new consumer subscriptions over capacity constraints three days after launch.

Where the Bottleneck Shows Up: Die to Test

Break this demand down by supply chain exposure point and five layers remain. This is an exposure map, not a time sequence. Capacity reservations, HBM production, rack networking, DCI, and test equipment orders all move in parallel, each on its own lead time. PhotonCap has covered each layer separately, so each one links to the relevant analysis.

1. Die: foundry capacity. More resident bits mean more wafers for the DRAM dies and the base and logic dies under every HBM stack, and as optical interconnect moves into the package, dedicated silicon photonics capacity. Capacity is a resource with lead times measured in years, so the land grab starts before the bottleneck makes headlines. What happened at the foundries before the laser shortage became news: Everyone Saw a Laser Shortage. The Money Went to the Foundries First.

2. Package: HBM. As K3’s arithmetic shows, the variable is not price per bit but total bits shipped. And the memory wall is not only a capacity problem. Bandwidth, latency, and the energy cost of moving those bits can constrain serving economics even when nominal capacity is enough, which is why growing capacity and growing bandwidth pull on different supply chains. Why HBM demand and optical memory pooling diverge: The More Anthropic Buys Micron HBM, the Faster Optical Memory Pooling Arrives

3. Rack: scale-up interconnect and InP. With 896 experts split across accelerators, the router’s per-token expert calls generate traffic between accelerators. Moonshot itself recommends deploying K3 on supernodes of 64 or more accelerators, noting that inference efficiency benefits from larger high-bandwidth communication domains [4]. That is a structure where scale-up domain bandwidth decides serving economics. Optics enters at the distances copper cannot reach, and the more optics wins, the more InP sells: The More Silicon Wins, the More InP Sells

4. Campus: coherent DCI. If self-hosting and inference diffusion actually spread across multiple sites, traffic between sites grows with them. Self-hosting that stays inside a single datacenter or a single cloud gives this layer limited benefit. The switch that turns this layer on is multi-site distribution. Why scale-across is a different market with a different frame: One Layer Below SemiAnalysis’s Meta Map

5. Cross-cutting: test and measurement. Test is not a final step. It runs across wafer, die, package, module, and link manufacturing at the same time. Whoever wins the four layers above, every new HBM stack and every new optical link ships only after it passes test: Compute Is the New Oil. So Who Builds the Drilling Rigs?

Investment read: the five layers are parallel exposures, not a sequence. The land grab shows first where lead times are longest (foundry capacity), and volume shows first where demand tracks usage directly (HBM, scale-up optics).

Closing: The Two Things This Correction Is Discounting Together

Damnang explains why open models do not destroy semiconductor demand. Kimi K3 shows, in its spec, where that demand goes. A structure that limits the active parameter set to an estimated 50 to 60B per token while requiring access to 2.8T weights. A total-versus-active gap that widens every generation. And a capacity shortage notice three days after launch.

The conditions that would weaken this picture belong on the record too. Expert offloading and caching working better than expected, reducing what must sit in accelerator memory. Another step up in quantization density. Self-hosting delayed by concentration in cloud APIs. KDA-class architectures cutting far deeper against the baseline than assumed. The breakdown of K3-driven demand into listed-company exposure across HBM, InP light sources, coherent DCI, and test equipment, along with the indicators to watch for each, continues in the four pieces linked above.

Even granting those conditions, this correction is discounting the model layer’s premium compression and the demand for HBM, optical interconnect, and foundry capacity at the same multiple. I do not think those two point the same way.

The fiercer the competition gets at the model layer, the more the hardware layer sells to whoever wins.

Acknowledgment

This article’s starting point is Damnang’s analysis of open models and semiconductor demand.

Damnang’s Substack

The Open-Source AI Era: Will Hyperscalers Keep Buying Chips?

Semiconductor investors have had a run of unsettling news…

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a month ago · 39 likes · 3 comments · Damnang

References & Sources

[1] TSMC, “TSMC Reports Second Quarter EPS of NT$27.25”, Jul 16, 2026.

[2] Bloomberg, “Chip Stock Rout Deepens as TSMC Selloff Drives Taiwan Correction”, Jul 17, 2026.

[3] Fortune, “Markets experience new DeepSeek shock after Moonshot AI releases Kimi K3”, Jul 17, 2026.

[4] Moonshot AI, “Kimi K3: Open Frontier Intelligence”, Jul 16, 2026.

[5] Moonshot AI, “Kimi K2: Open Agentic Intelligence”, arXiv:2507.20534, first submitted Jul 2025.

[6] DeepSeek-AI, “DeepSeek-V3 Technical Report”, arXiv:2412.19437, Dec 2024.

[7] NVIDIA, “Inside NVIDIA Blackwell Ultra: The Chip Powering the AI Factory Era”, NVIDIA Developer Blog, 2025.

[8] Ken Huang, “Demystifying Kimi K3: The Three Algorithms Behind the #1 Frontend Coding Model”, Substack, Jul 18, 2026.

[9] Reuters, “China’s Moonshot pauses Kimi subscriptions amid hot demand, IPO push”, Jul 20, 2026.

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Disclaimer: This article is an independent, engineering-driven technical analysis published by PhotonCap. All content is based on publicly available information and is intended for educational and informational purposes only. Nothing herein constitutes a recommendation to buy, sell, or hold any security. The author may hold positions in securities discussed and may transact at any time without notice. Readers should conduct their own due diligence before making any investment decisions.

Abstract

Between June 2 and June 4, 2026, three stocks peaked within three days of one another. Ciena and Cisco closed at all-time highs, and Nokia printed a 52-week high. By July 17, Ciena had corrected 40.3% from its peak close, Nokia 39.9%, and Cisco 13.9%. All three are the classic incumbents of the scale-across coherent layer, the optics that link one datacenter to another. And the split is telling: the two companies with the highest optical exposure fell roughly 40% in lockstep, while Cisco, with the lowest exposure, gave back only 14%. This piece compares what each company actually holds, what the correction priced in, and when and where the numbers that will judge this correction arrive. The first gate is Nokia’s Q2 report on July 23. Tickers: $CIEN $NOK $CSCO.

Contents

1. Intro: the ones that rose most fell most

2. The layer these three stand on: a recap of the two optical fights

3. What each of the three incumbents holds

4. Nokia: four DSPs and two very different checks

5. Cisco: the dot-com relic whose coherent business just had a record quarter

6. Ciena: a correction at a supply-constrained company

7. Scenarios and three gates

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1. Intro: The Ones That Rose Most Fell Most

Here are the trailing 1-year returns (as of the 2026-07-15 close).

Ciena ($CIEN) +406.6%. Nokia ($NOK) +141.0%. Cisco ($CSCO) +68.1%.

And here are the drawdowns from each June peak close to the July 17 close (unadjusted closing prices).

Ciena -40.3% ($627.00 → $374.41). Nokia -39.9% ($16.85 → $10.12). Cisco -13.9% ($130.00 → $111.94).

Start with the peak dates. On a closing basis, Ciena and Nokia topped on June 2 and Cisco on June 4, while Nokia’s intraday 52-week high of $17.45 printed on June 3. Three stocks peaked within three days of one another, and over the following six weeks they split into two groups. Ciena and Nokia, the two names with the heaviest optical exposure, fell roughly 40% by almost identical amounts. Cisco, where optics is one business among several, gave back only 14%. It looks like coincidence. It is not. There is a reason for this split, and that reason is the subject of this piece.

One scene captures what kind of correction this was. On June 4, Ciena reported quarterly revenue up 40%, adjusted EPS nearly quadrupled, and a raised full-year guide. The print beat consensus. There was no guidance cut and no ugly headline. The stock still fell 13.7% that day ($620.37 → $535.63), then dropped another 8.9% the next day, for a two-day cumulative decline of more than 21%. The results were not the problem. Even a raised guide could not fill the price and the expectations that had been stacked in front of it. And the July leg down that followed was not a Ciena-specific event; it came with a repricing across the entire AI optics complex.

So the question becomes this. Did the correction break the scale-across demand thesis, or had the price simply run ahead of the thesis? To answer that, we first need to pin down exactly which layer these three companies stand on.

Summary: three peaks within three days in early June, then a six-week correction. High-optical-exposure Ciena and Nokia both fell about 40%, while low-exposure Cisco fell only 14%. The trigger was not deteriorating results.

2. The Layer These Three Stand On: A Recap of the Two Optical Fights

In our last piece, we laid out why there is not one optical fight inside an AI datacenter but two. Inside the rack (scale-up) it is a CPO fight; between datacenters (scale-across) it is a coherent DCI fight. The distance-based layer split itself was first drawn in our April NVIDIA-Marvell piece, and if terms like CPO, LPO, and NPO are new to you, the optical architecture primer is a good place to start. Meta’s blueprint linking campuses at distances up to 2,000 km (a SemiAnalysis model estimate) was the first concrete evidence that demand for the second fight is opening at gigawatt scale.

The hardware market that receives that demand is shifting in ways the numbers confirm. Per Cignal AI, standalone coherent WDM pluggable revenue grew 37% to reach $1.8B in 2025 (Cignal AI rounds this to a $2B market in its headline), a category that has compounded at 71% annually since 2021. WDM pluggables are projected to exceed $5B by 2029 at a 30% CAGR, the single largest growth driver in optical hardware, and the near-term catalyst is the volume deployment of 800ZRx modules into AI-driven scale-across networks.[1] (In this piece, 800ZRx is used as the market-research umbrella covering the OIF-standard 800ZR and vendor-specific 800ZR+ families.) Scale-across architectures demand 5x to 20x the bandwidth of legacy DCI, and North America posted record optical revenue in 2025, growing more than 30% and overtaking China by a wide margin as the largest optical market.[1]

In the last piece we noted that Marvell and Coherent had adopted scale-across as their own official language. That language has now spread to one more company. In its May earnings materials, Cisco classified its new design wins using the phrase “P200 scale-across” directly on its official IR slides.[2] This is no longer an analyst’s frame. It has become the suppliers’ own product taxonomy.

Which brings us to the cast of this piece. Coherent technology is the craft that carrier-backbone equipment makers spent decades refining. Ciena and Nokia (including the Infinera lineage) are direct descendants of that craft, and Cisco joined it in 2021 by acquiring Acacia, a company of that lineage. The three incumbents in the networking sense, Ciena, Nokia, and Cisco, are the cast of this piece.

Summary: scale-across coherent pluggables are a market growing from $1.8B in 2025 to $5B+ by 2029, and the frame has become the suppliers’ own official product taxonomy.

3. What Each of the Three Incumbents Holds

Standing on the same layer does not make them the same company. Each arrived here by a completely different path.

Ciena is the one whose revenue is most directly exposed to the optical network investment cycle. It owns its coherent DSP line, WaveLogic, and fields a lineup that spans both line systems and pluggables: WL6e-based 1.6Tb/s coherent solutions, WaveLogic 5 Nano 400G and WaveLogic 6 Nano 800G coherent pluggables for metro DCI, and 1.6T coherent-lite aimed at campus and inside the datacenter.[3]

Nokia completed the vertical structure of this layer by acquisition. It closed the Infinera deal on February 28, 2025, scaling up its optical networks business, and the company itself framed the acquisition as accelerating growth into datacenters, North America, and webscale customers.[4] What Infinera brought was InP (indium phosphide) PIC technology and fabs, and combined with Nokia’s existing silicon photonics, the result is an optical front-end structure with a foot on both material platforms.

Cisco is defined by the combination of in-house switching and routing silicon alongside coherent DSP and optics under one roof. Silicon One sits in the fights inside the rack and the building (scale-up, scale-out), while Acacia, acquired in 2021, sits in scale-across with its coherent DSP and silicon photonics. So the fact that Cisco’s drawdown is the shallowest of the three is better read not as superior defense, but as scale-across simply being the smallest share of the whole company.

Which brings us back to the observation from the intro. Ranked by purity of scale-across exposure, the order is Ciena, Nokia, Cisco (this purity is the author’s qualitative assessment based on disclosed revenue segments, product mix, and order disclosures, not an accounting measure). Optics is the center of Ciena’s business, one part of Nokia’s group, and one of several businesses at Cisco. And in this correction, the two high-purity names fell roughly 40% side by side while low-purity Cisco stopped at 14%. What the market discounted was not any individual company’s results but scale-across exposure itself. Of course, the attribution is not that simple. Nokia’s +141% in particular carries a meaningful contribution from the AI-RAN and NVIDIA narrative, so part of its -39.9% may be that narrative unwinding rather than optics. Why that distinction matters is something we sort out in the Nokia chapter of the paid section, where we split the two checks apart.

One question deserves a preemptive answer. Why is Marvell ($MRVL), the other headliner of this layer, not in this comparison? Marvell is not a classic equipment maker; it entered this market as the merchant-DSP-and-pluggable insurgent, and PhotonCap has covered it separately several times, including in the last piece. In this article Marvell appears not as a fourth card but as the yardstick against which the three incumbents are measured. Where exactly it becomes the yardstick is confirmed with numbers in the paid section.

Figure 1: Distance-based three-layer map (scale-up / scale-out / scale-across) with the three companies’ product positions overlaid

Everything up to here, though, is a map anyone familiar with the public record could draw. The real question is not the map but the clock. Even with exposure pointing the same way, the numbers each company must prove in this correction are completely different. Nokia has to bridge the gap between a product roadmap that reaches GA in 2027 and its optical growth rate right now. Cisco has to show its coherent business is genuinely growing at triple digits. Ciena has to show how fast a record backlog converts into revenue. And all three already have dates on the calendar for those numbers. The first one lands days after this piece is published.

What is written on each company’s card, and what to check on which date. That is where the real body of this piece begins.

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Abstract

The price of G.652.D bare fiber in China went from RMB 15.5 per fiber-km in May 2025 to RMB 81.9 in May 2026, roughly 5x in a year [1]. Not because silica ran short. Because AI datacenters are adding optical paths faster than preform and high-count cabling capacity can keep up. And this shortage does not move on one global price. In the US, local production and hyperscaler qualification set the price. In China, domestic supply and demand is pushing bare fiber up. Japanese makers sit between the two, raising prices on high-density cable. In the last piece I covered the paradox that the more silicon photonics wins, the more InP light sources sell. This one is about the road the light has to travel. I convert Korea’s 8.4GW and the global pipeline into fiber strand counts and core-km, and break down which company takes which value pool. One preview: even as transceivers jump from 800G to 1.6T, fiber demand does not fall. Why that happens is the back half of this article. The tickers this time: $GLW, $APH, Fujikura (5803.T), Furukawa (5801.T), Sumitomo Electric (5802.T), YOFC (601869.SS), and Taihan Fiberoptics (010170.KQ).

Contents

1. 190GW Does Not Flow Into One Supply Chain

2. Where the 16x and 36x Multipliers Actually Come From

3. Converting GW into Core-KM

4. The Regional Supply Map: The Spec Is Open, the Door Is Shut

5. Same Shortage, Different Price Zones

6. The Fiber Paradox

7. Scenarios

Optical fiber that sold for RMB 15.5 per fiber-km now sells for RMB 81.9.

That is Chinese G.652.D bare fiber, the standard single-mode fiber before cabling. Goldman Sachs flagged the number in a June note on YOFC: roughly 5x between May 2025 and May 2026 [1].

What makes a 5x move in fiber strange is not the raw material. It is the production structure. Optical fiber is fused silica, SiO2. Silicon and oxygen make up three quarters of the Earth’s crust by mass, and even the ultra-high-purity synthetic silica used for fiber is not a scarce mineral. The money sits in the process, in synthesizing and drawing the preform, not in the ingredients. Which is why fiber spent decades at a few dollars per fiber-km, one of the cheapest components in telecom infrastructure, and why it became the poster child for cutthroat bidding during the Chinese oversupply of the 2010s. A 5x print in that market is not a raw-material shock. It means datacenter demand, rising carrier tender prices, and a production mix shift toward higher-value products are squeezing existing capacity all at once [1].

And this is not just a China story. In the US, industry participants are warning that fiber availability will tighten sharply in 2026 [2]. In Japan, Fujikura, the best-performing stock in the Nikkei 225 in 2024 at +400% [3], climbed more than 160% again in 2025 [4]. This is a company that started in 1885 making silk and insulated wire [3]. The same material is heating up on three continents at once, and it is not a wafer or a laser. It is a strand of glass. A component the industry spent two decades treating as a throwaway line item is suddenly the thing hyperscalers sign multiyear contracts to secure.

Figure 1: Three Continents, One Material - Fiber Price, Supply, and Stock Signals

In the last piece, after watching UMC and Tower both announce 300mm silicon photonics expansions on the same day, July 14, I wrote that the next bottleneck was not wafers but InP light sources. Silicon cannot make light.

The More Silicon Wins, the More InP Sells: Why UMC and Tower Both Expanded 300mm on the Same Day

But that piece had one seat left deliberately empty. The light a laser makes has to travel somewhere. Between transceiver and transceiver, rack and rack, building and building. That entire road is glass.

If InP is the bottleneck on the side that makes light, fiber is the bottleneck on the side that carries it. Same cycle, different physical location, and as we will see, a different supply structure and a different way prices move. InP was a narrow, deep bottleneck, wafers and epi, with suppliers you could count on one hand. Fiber looks like the opposite: a wide, shallow bottleneck. Companies make it on three continents, and yet prices are printing 5x and hyperscalers are locking up years of capacity in advance. Why that happens is the problem this article works through.

Bare fiber up 5x in China, supply warnings in the US, and in Japan the 2024 Nikkei champion Fujikura up another 160% the following year. Raw-material scarcity cannot explain these signals. What you need to watch is supply, demand, and capacity.

1. 190GW Does Not Flow Into One Supply Chain

Start with demand. Sightline Climate tracks 777 large datacenters and AI factories above 50MW announced since 2024, a project pipeline of roughly 190GW [5]. It is an announcement-based count, so much of it is still on paper, and the same dataset carries a caveat: of the 16GW slated to come online in 2026, only about 5GW is actually under construction [5]. Still, the number is more than enough to read direction. The reason to look at this 190GW by region is that the fiber supply chain is tied to regional qualification and production footprints. Why it is tied that way is a paid-section question. Here, the point is simply that there are three separate invoices.

United States. The core of demand. Corning’s Optical Communications revenue grew 36% year over year in Q1 2026 to around $1.85B [6], and enterprise sales grew 58% year over year in Q3 2025, driven largely by strong adoption of Corning’s Gen AI products [2]. The shape of the contracts has changed too. In January, Meta signed a multiyear agreement with Corning worth up to $6B and took the anchor-customer seat at the Hickory, North Carolina plant [7]. On June 8, Amazon announced a multiyear, multibillion-dollar supply agreement with Corning [8]. In between, the Q1 earnings call disclosed two more hyperscaler contracts of similar size and duration to Meta’s [7]. Components that used to be bought quarter by quarter are now being reserved years of capacity at a time. When a buyer locks in a specific plant as its anchor customer, it is no longer purchasing a commodity. It is renting a supply chain. The CEO of STL’s optical networking business says the US needs to add another 213 million fiber-miles by 2029. With roughly 160 million miles installed today, that means laying more than everything laid so far, inside four years [2].

Korea. On June 29, the government announced an 8.4GW AI datacenter plan with SK (5GW), GS (2.4GW), and Naver (1GW). 550 trillion won, groundbreaking targeted for the first half of 2028, staged operation from 2029 [9]. On top of that, on June 8 Naver and NVIDIA announced an AI factory anchored at GAK Sejong: 55MW in the first half of 2027, then 100MW, 200MW in 2028, and eventually gigawatt class [10]. One gigawatt is about 4x the maximum capacity of GAK Sejong [10]. An announcement is not a groundbreaking, but a national demand block has landed on the invoice in gigawatt units. And 8.4GW is more than 4% of the 190GW global pipeline Sightline tracks [5], one of the largest single-country plans anywhere.

China. Even with access to leading-edge US GPUs locked behind licenses and running at a trickle [11], the build continues on domestic accelerators, and that demand is part of what sits behind the 5x bare fiber move [1]. YOFC guided H1 2026 net profit up 711% to 914% year over year [12]. A fiber company guiding profit up eight-fold in a single year was not a sentence anyone would have written before this cycle. And unlike the equity moves in the US and Japan, this one is earnings, not multiple expansion.

All three regions announce demand in gigawatts. What differs is the supply chain. These three invoices go to three different sets of factories.

The 190GW pipeline is one number, but from fiber’s point of view it is three invoices, from the US, Korea, and China, each handed to a different supply chain.

2. Where the 16x and 36x Multipliers Actually Come From

Network topology decides how much fiber an AI datacenter eats.

Cloud datacenters already carry heavy east-west traffic between servers. What changes in an AI training cluster is not the existence of east-west but its intensity. A dedicated training back-end fabric gets built separately from the front-end network, every GPU gets a high-speed NIC, and oversubscription gets pushed toward zero. A near non-blocking design means the spine-facing uplink bandwidth matches the total GPU-facing downlink bandwidth of the leaves. That is a bandwidth statement, not a link-count statement; actual link counts depend on port speeds and switch radix. And as clusters grow and tiers get added, aggregation links keep stacking on top of the GPU-facing links.

That is where the vendor multipliers come from. One caveat first: these multipliers are vendor estimates with different baselines. Corning’s head of fiber and cable says a 72-GPU node like NVL72 needs 16x more fiber than a traditional cloud switch rack [2]. STL’s CEO says an AI rack needs roughly 36x more than a legacy CPU rack [2]. Different denominators, so you cannot merge them into a single “16x to 36x” range. What they share is the conclusion that the order of magnitude changes whichever baseline you pick. AFL, the cable assembly house, gets more concrete in its reference architecture: up to 1,152 fibers feed a single NVL72 rack, and leading AI sites are deploying ultra-high-count cables that pack 6,912 fibers into one jacket [13]. Telecom cables run tens to a few hundred fibers. This is a different class of product. And the number of companies that can even build this class of cable is small. Folding and rolling ribbons to pack thousands of fibers into one jacket is each maker’s weapon in its own right, and it is where the commodity story about fiber quietly stops being true.

Figure 2: Why AI Fabrics Eat Fiber - Back-End Fabric, Oversubscription, and Vendor Multipliers

The signal that this layer has been promoted to an investment target has already fired. NVIDIA made four direct photonics investments this year: Coherent, Lumentum, and Marvell in March, $2B each, and then the fourth on May 6 was Corning. Per the official announcement, the deal bundles a multiyear commercial and technology partnership with a 10x expansion of US optical connectivity capacity, three new plants in North Carolina and Texas, and more than 3,000 jobs [14]. On the equity side, NVIDIA paid $500M for warrants (15M shares at $180 plus a 3M-share pre-funded warrant) that could ultimately give it a position worth up to roughly $3.2B if fully exercised [15]. Separately, Jensen Huang described an additional multibillion-dollar prepayment to help fund Corning’s new US factories. The first three companies make and process light. Only the fourth builds the road the light travels on. I covered the structure and meaning of that deal in a separate piece in May.

Coherent, Lumentum, Marvell, and Now Corning: NVIDIA’s 4 Photonics Bets and the Path of Light

So reading gigawatt announcements as fiber demand is not a metaphor. It is arithmetic. Gigawatts set the accelerator count, accelerators set the rack count, and topology multiplies the racks. Every step in that chain is a number you can put a range on, which is exactly what the next section does.

That is as far as public sources take you. In the paid section, I convert this demand into actual strand counts and core-km, work through why a market that looks like a standardized commodity keeps new suppliers out, and then calculate why the 1.6T transition does not shrink fiber demand. The last question matters most. Like the Silicon Paradox in the InP piece, there is one result here that runs against intuition. One hint up front: the answer lives in how fast clusters are growing, not in the transceiver roadmap.

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