Abstract

Applied Optoelectronics ($AAOI) has surged 1,440% in one year. Starting from a $2 bottom in 2023, the stock broke through $150 in April 2026. This company originally made cable TV (CATV) equipment. This article analyzes the structural backdrop behind AAOI’s EML (Electro-absorption Modulated Laser) transceivers rapidly capturing 800G market share, and examines whether this position can hold against SiPh (Silicon Photonics) based solutions as the industry moves to 1.6T/3.2T. We compare AAOI’s valuation, technical positioning, and risks against competitors including Lumentum ($LITE) and Coherent ($COHR). Related tickers: $AAOI, $LITE, $COHR, $MRVL, $TSEM, $GFS.

Contents

1. Intro: Why AAOI, Why Now

2. What is AAOI: From CATV to AI

3. Anatomy of the Orders: $300M+ in Contracts

4. EML vs SiPh: 800G Works, But What About 1.6T?

5. Competitive Landscape: LITE, COHR, and Innolight

6. Valuation and Risks

7. Scenario Analysis & Monitoring Points

8. Closing

9. References & Sources

1. Intro: Why AAOI, Why Now

Today (April 10), Lumentum CEO Michael Hurlston told Bloomberg: “The capex numbers from the U.S. hyperscalers are enormous, and there seems to be no end in sight. We would be sold out through all of 2028 within two quarters.”[1] Orders filled through 2028. A month ago, he said “sold out through end of 2027.”[2] Visibility just extended by another year.

This is not just a Lumentum story. The entire optical component market has entered a structural supply shortage. And right in the middle of that shortage, an unexpected beneficiary has emerged.

Applied Optoelectronics, $AAOI.

Stock price a year ago: $10. Now: $150. The rally has real substance behind it. The question is how long that substance lasts.

This article covers how AAOI pivoted from a CATV parts company to an AI optics stock, what the recent $300M+ order wave actually looks like, and whether its EML technology base can survive the SiPh transition. We compare against LITE, COHR, and others along the way.

2. What is AAOI: From CATV to AI

To understand AAOI, you need to start with its history. This is not the company’s first time in the spotlight.

The First Cycle: 2017 Glory and Collapse

Founded in 1997 by Dr. Thompson Lin, AAOI originally made optical transceivers, headend equipment, and lasers for CATV (cable TV) networks. HFC (Hybrid Fiber-Coaxial) network backbone equipment, basically the plumbing behind cable internet.

Then 2017 hit. During the early cloud buildout, demand for 40G/100G transceivers (modules that convert data into optical signals and send them over fiber) surged, and AAOI’s stock shot to $100. The main customer at the time was Amazon.[3]

What followed was the problem. Larger competitors moved in, and AAOI’s revenue structure, heavily dependent on Amazon, collapsed along with the customer relationship. The stock fell 91% from $100 to $8.50 (August 2019).[4] That was not the bottom. After a brief post-COVID bounce, it hit an all-time low of $1.48 in July 2022.[4]

The Pivot: CATV Cash Cow + Data Center Transition

AAOI in 2022-2023 was essentially a CATV company. As of Q3 2025, CATV still accounted for 66% of total revenue.[5] Data center was at 24%. In September 2022, the company even agreed to sell its Chinese factories to Yuhan Optoelectronic for $150M, planning to double down on CATV (the deal was terminated in September 2023 due to CFIUS issues).[34]

The turning point came in late 2023. A strategic supply agreement with Microsoft kicked off a serious pivot toward 400G/800G data center transceivers.[3]

This is where AAOI’s core strength showed up. The company is vertically integrated. It handles everything from InP (indium phosphide) semiconductor crystal growth to EML laser chip fabrication to final transceiver module assembly, all in-house.[3] Most transceiver companies buy their laser chips externally. AAOI makes its own.

Current State: FY2025 Results

Full-year 2025 revenue was $455.7M, up 82.8% year-over-year.[6] Annual revenue mix:

• CATV: 53.8% (Digicomm at 53.1% of annual revenue)

• Data Center: 42.9% (Microsoft at 31% of annual revenue)

• Telecom/FTTH: the remainder[7]

The quarterly picture tells a different story, though. In Q4 2025, data center grew rapidly, shifting the composition. Q4 top 3 customers: CATV customer at 39%, data center customer at 31%, another DC customer at 21%, totaling 91%.[15] On a full-year basis, Digicomm was at 53%, but as data center surged in Q4, CATV’s relative share dropped. This ratio will flip further in 2026.

Q4 2025 revenue hit $134.3M, a quarterly record, with near break-even on a non-GAAP basis (EPS -$0.01).[6] We will revisit the customer concentration numbers in the risk section.

Key takeaway: AAOI hit $100 in 2017 and crashed to $1.48. Now it is in its second cycle, with a CATV cash cow funding a data center pivot. Vertically integrated EML laser manufacturing is the core asset.

Now that we know what the company looks like, let’s look at what actually moved the stock. The orders that poured in starting March.

3. Anatomy of the Orders: $300M+ in Contracts

Here is what happened to AAOI in the span of one month starting March 2026:

Over $300M in orders landed in one month. For context, AAOI’s full-year 2025 revenue was $455.7M. More than double the existing backlog stacked up in a single month.

CFO’s Direct Quote

From the Q4 2025 earnings call, CFO Stefan Murry:

“This revenue level is limited by our production capacity and supply chain, not market demand, which we believe is much larger.”[11]

Revenue is capped by production, not demand. They can sell everything they make.

2026 Guidance

Based on these orders, management guidance for 2026:

• Annual revenue exceeding $1B (119% growth from $455.7M in 2025)[6]

• Non-GAAP operating profit above $120M[6]

• Non-GAAP profitability starting Q2 2026[6]

• Q1 2026 guidance: revenue $150-165M, non-GAAP net loss $0.3-7M[12]

Longer-term targets are even more aggressive. Year-end target of 500,000 units/month across 800G and 1.6T. Mid-2027 monthly transceiver revenue potential estimated at roughly $378M (100G/400G ~$90M, 800G ~$217M, 1.6T ~$71M).[13]

Who is Buying?

Officially, the announcements only say “major hyperscale customer.” The market believes it is Oracle and Microsoft.[14] The 10-K explicitly names Microsoft as the key data center customer for 2025[7], and the 1.6T order is widely attributed to Oracle.[14]

The CFO directly stated on the earnings call that of the projected $1B in 2026 revenue, subtracting ~$300M in CATV leaves ~$700M in data center, and the majority of that will come from two large hyperscalers, with roughly equal weight by year-end.[15]

Capacity Expansion

To fulfill these orders, AAOI is running three parallel tracks:

1. Sugar Land, TX new facility: Groundbreaking February 2026, targeting mid-to-late 2026 operations. Texas laser capacity to triple by mid-2027[13]

2. Taiwan facility expansion: Existing transceiver assembly line expansion

3. Automated production lines: Expanding U.S. production share (over 90% of 800G/1.6T component value is already non-China sourced)[13]

Funding is coming via a $250M ATM (At-The-Market) offering set up on February 26, expanded to $500M on March 12.[16] Approximately 2.48 million shares were already sold for $250M in proceeds.[16]

Key takeaway: $300M+ in orders arrived within a single month, and management is guiding for $1B+ in 2026 revenue. Most of that revenue will be concentrated in two hyperscalers.

That covers “what is happening at AAOI right now.” The orders are real. Capacity expansion is underway.

But here is a question worth pausing on. AAOI’s transceivers are EML-based. With the industry moving toward SiPh, can this technology base survive into the 1.6T and 3.2T generations? And where does AAOI stand relative to Lumentum and Coherent, both backed by $2B from NVIDIA?

The analysis continues below.

4. EML vs SiPh: 800G Works, But What About 1.6T?

Read more

Hollow-Core Fiber (HCF) has carried the label “someday technology” for years. Loss records were broken annually, and lab demonstrations piled up. But the mood at OFC 2026’s Th1J and W1F sessions is different. Microsoft, Nokia Bell Labs, and Sumitomo Electric are each answering the same question from different angles. What must be solved to deploy HCF in real networks?

For context, as of early 2026 Microsoft has deployed over 1,280 km of live Azure HCF with zero field failures [5][6]. AWS has also begun production HCF deployment across roughly 10 data centers [7]. The loss number race is over. YOFC has reached 0.04 dB/km [9], and Microsoft reported 0.091 dB/km operational loss (over 1,200 km of production fiber) in Nature Photonics [8]. However, the real significance of that paper may lie not in the loss record itself, but in securing a physical platform for WDM (Wavelength Division Multiplexing) scale-up through the combination of nonlinearity removal, ultra-low dispersion, and low latency [10]. The remaining hurdles are CO₂ gas absorption, inter-modal interference (IMI), manufacturing yield, and cost. The four papers reviewed here are the cards each organization has played against these four challenges.

Four Papers at a Glance

HCF vs SMF: System Design Comparison

Note on measurement conditions: Distances and capacities are not directly comparable due to differing experimental methods (straight-line vs recirculating loop) and fiber types. All values are as reported by the respective authors.

From here, I examine what each paper actually demonstrated and what these results mean for HCF commercialization.

1. Microsoft Azure Fiber: Beating GLA over 442 km

Read more

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Two Fronts

Datacenter optical interconnects are pushing density on two fronts simultaneously. One is scaling IM-DD (Intensity Modulation / Direct Detection) lane rates from 200 Gb/s to 400 Gb/s. The other is scaling coherent pluggables from 800 Gb/s to 1.6 Tb/s. The two fronts look independent, but they are deeply entangled. Once 400G/lane IM-DD becomes prevalent, routing systems will shorten the electrical traces between the switch ASIC and the optics, accelerating CPO/NPO adoption. At that point, coherent line optics get pushed out of the router chassis and back into standalone transport platforms.

Six papers from OFC 2026 map the current technical coordinates of these two fronts. The thesis: 400G/lane IM-DD and 1.6T coherent pluggables are each approaching their physical limits, and the tradeoff structures for pushing past those limits are fundamentally different. Not a single one of the six papers showed a measured link demonstration.

Six Papers at a Glance

IM-DD vs Coherent: Technology Positioning

From here I break down each paper’s technical substance, cross-compare across papers, and extract structural insights for the value chain.

1. Broadcom: Pushing the Physical Ceiling of 400G/Lane with DD EML

Read more

Aehr Test Systems reported Q3 FY2026 revenue of $10.3M, down 44% YoY. But bookings hit $37.2M with a book-to-bill over 3.5x. The real signal for SiPh investors: Aehr now has at least two production-stage silicon photonics customers ordering wafer-level burn-in systems, up from one. This article breaks down why WLBI is structurally mandatory for SiPh devices heading into CPO/optical I/O packages, connects today’s results to the Three Pillars test infrastructure framework, reads the undisclosed customer identity signals, and examines the technical breakout on the weekly chart.

Contents

1. Why This Matters for the SiPh Thesis

2. The WLBI Logic for Silicon Photonics

3. Reading the Customer Identity Signals

4. Connecting to the Test Infrastructure Stack

5. The Financial Picture

6. Chart: The Breakout

7. Bottom Line

Aehr Test Systems (NASDAQ: AEHR) just reported Q3 FY2026 results. Revenue was $10.3M, down 44% YoY. Net loss widened. On the surface, a forgettable quarter.

But the real story is in the bookings: $37.2M, book-to-bill over 3.5x. And within that number, silicon photonics is emerging as a structurally significant demand driver alongside AI ASICs.

Why This Matters for the SiPh Thesis

Aehr’s earnings call delivered two discrete silicon photonics data points that deserve close attention.

First, a new SiPh customer win. Aehr disclosed a major new customer order for high-power FOX-XP wafer-level burn-in (WLBI) systems targeting hyperscale data center optical interconnects. The customer is developing silicon photonics-based transceivers for data center networking and optical I/O. This was not a qualification unit. It was an initial order for multiple FOX systems covering both qualification and production, a distinction that signals commercial intent rather than exploratory evaluation.

Second, a follow-on order from the existing lead SiPh customer. This included both a new high-power FOX-XP system and an upgrade of an existing FOX system to the latest high-power, fully automated configuration. Upgrading existing installed base to higher-power specs is a capacity expansion signal, not a one-off purchase.

These two data points together suggest that at least two separate silicon photonics companies are now in volume or near-volume production trajectories requiring dedicated burn-in infrastructure.

The WLBI Logic for Silicon Photonics

Read more

Introduction

The AI infrastructure race has moved beyond chip design into packaging.

No matter how fast GPU and switch ASIC performance scales, the optical interconnect that moves data off-chip becomes the bottleneck if packaging cannot keep pace. Co-Packaged Optics (CPO) attacks this bottleneck head-on by pulling the optical engine inside the switch package, minimizing electrical interconnect length, and improving both bandwidth and power efficiency simultaneously.

The question is “on what substrate, and how do you attach the chips?” The answer to this question determines the path to CPO commercialization.

This installment analyzes technologies that answer this question in different ways, drawing on four papers presented at OFC 2026 and one foundational journal paper. Corning demonstrated its “glass platform” through two OFC papers, with a 2023 JSTQE paper providing the underlying technology base. UC Davis / Lawrence Berkeley National Lab presented the world’s first 3D hybrid-bonded EPIC demonstration with solder completely eliminated. Sumitomo / PETRA introduced a compact InP-on-Si PIC that resolves the L-band coherent receiver trade-off through heterogeneous integration.

All five papers share a single core message: packaging technology determines system performance.

Five Papers at a Glance

CPO Packaging Technology Comparison

From here, I analyze each paper individually, examining where each technology sits in the CPO packaging stack, its limitations, and structural insights across the full value chain.

1. Corning: Redesigning CPO on Glass

Read more

AI clusters are doubling in scale every year. Meta’s current ORv3 rack connects 72 GPU nodes over a copper backplane. The ORW rack, soon to be deployed, scales to 144 nodes. The next generation exceeds 256 nodes, pushing single-rack power past 1 MW [1]. At this scale, copper-based electrical interconnects hit walls simultaneously across power, bandwidth density, and routing complexity.

CPO (Co-Packaged Optics) as an alternative is not a new story. What is new is that Meta drew a public baseline at OFC 2026: “For optical technology to be compelling, it must be reliable and performant while offering comparable cost and power efficiency to electrical solutions.” All three conditions must be met, or it does not get used. This single framing defines the entire CPO session at OFC 2026.

In Part 2, we examine five papers from OFC 2026 that cover four segments of the CPO value chain: external laser sources (Furukawa), link margin compensation (Lightmatter QD-SOA), transceiver systems (Lightmatter BiDi), field reliability (Meta/Broadcom), and photodetectors (Marvell/McGill). Each addresses a different layer, but they share one underlying question.

“CPO has entered the stage where it must prove operational viability, not just performance. And there are still significant gaps in that proof.”

Five Papers at a Glance

Cross-Comparison

From here, we analyze each paper individually, examining where each technology sits in the CPO value chain, its limitations, and structural insights across the full chain.

1. Meta/Broadcom: What 36 Million Hours Tell Us, and What They Don’t

Read more

Two Ways to Read a Conference Paper

Every conference paper has two layers. There are the numbers the authors put front and center, and there are the quieter signals buried in the body text. Read the seven papers that Samsung, GlobalFoundries, and NVIDIA presented at OFC 2026 side by side, and you begin to see that the gap between those two layers varies considerably across institutions.

The silicon photonics foundry race toward 200G/λ is no longer primarily a device performance competition. It is a contest of system integration completeness and ecosystem maturity. And in that contest, where the three players actually stand looks somewhat different from what their press releases suggest.

Seven Papers at a Glance

Samsung vs. GlobalFoundries Platform Comparison

(Note: MRM BW comparisons are sensitive to bias voltage and detuning conditions — direct comparison requires care)

From here, I break down what each institution’s papers actually show, what they do not show, and where the gap between official announcements and paper content lies.

Read more

Abstract

In March 2026, NVIDIA invested a total of $6B across Lumentum (LITE), Coherent (COHR), and Marvell (MRVL). This article decomposes the three investments by Scale-Up / Scale-Out / Scale-Across layer and analyzes the structural purpose of each deal. The focus is Celestial AI’s Photonic Fabric technology, acquired by Marvell for $3.25B. We examine the measurement basis behind the “25x bandwidth vs. CPO” claim and analyze three engineering resistance points on the path to volume production: yield, light source integration, and thermal management. A scenario-based value chain beneficiary/risk positioning map shows the asymmetric upside structure of LITE/COHR and the high-variance position of MRVL.

Contents

1. Intro

2. Background: Three Stages of AI Infrastructure Scaling

3. Section 1: NVLink Fusion, Why NVIDIA Opened Its Proprietary Interconnect

4. Section 2: Why Marvell Became the First NVLink Fusion Partner

5. Section 3: Celestial AI Photonic Fabric, the Technology and the Distance to Volume Production

6. Section 4: LITE + COHR, Why NVIDIA Locked Down the Laser Supply Chain

7. Section 5: Strategic Structure Analysis, the $6B Blueprint

8. Insights / Investment Implications

9. Closing

10. References & Sources

Intro

Three pieces of news dropped before March was even over.

On March 2, NVIDIA announced a $2B investment in Lumentum Holdings (NASDAQ: LITE). The same day, another $2B into Coherent Corp (NYSE: COHR).[1][2] On March 31, an additional $2B into Marvell Technology (NASDAQ: MRVL).[3]

$6B in a single month. All directed at photonics and optical interconnect infrastructure.

If you read these numbers as simply “NVIDIA locking down the optical supply chain,” you’re only seeing half the picture. Here’s the thesis of this article.

NVIDIA is transitioning from a company that sells GPUs to a platform company that designs the entire connectivity architecture of the AI factory. And photonics is going into every layer of that architecture.

To see this structure clearly, you first need to understand three scaling concepts, and then take a separate look at the Celestial AI technology bet tied to Marvell. In particular, Celestial’s claim of “25x bandwidth and 10x lower latency versus CPO” needs to be examined with proper context.

Today we map the full $6B investment structure layer by layer, and analyze the Celestial AI technology at the core of the Marvell deal from an engineering perspective.

Background: Three Stages of AI Infrastructure Scaling

Scale-Up, Scale-Out, Scale-Across: They Sound Similar but They’re Completely Different Problems

There are three directions for scaling AI infrastructure. This distinction forms the backbone of the entire article, so let’s get it right up front.

Scale-Up is the approach of connecting accelerators more tightly within a single compute domain. Inside a single rack, GPUs or XPUs are bound together through a unified memory-semantic fabric so they operate as one massive compute engine. NVIDIA’s NVLink is the canonical example. Connection distances range from meters to tens of meters, and copper (AEC, Active Electrical Cable) can physically handle these distances.[5]

Scale-Out is the stage of connecting rack to rack within a data center. InfiniBand and Ethernet are the primary protocols, and distances extend from tens to hundreds of meters. Copper can’t keep up, and PAM4-based optical transceivers (400G, 800G, 1.6T) become essential. This is precisely why CPO (Co-Packaged Optics) switches are gaining traction.[5]

Scale-Across is data center to data center, campus to campus, region to region connectivity. Distances stretch from 2 km to thousands of kilometers. Without coherent ZR/ZR+ technology, this is simply not possible. As AI models begin exceeding the power limits and physical space of a single data center, demand at this layer is growing rapidly.[6]

Each layer demands completely different specifications for bandwidth, latency, and power efficiency. Scale-up requires multi-TB/s ultra-low-latency fabrics. Scale-out prioritizes switching capacity and energy efficiency. Scale-across depends on coherent modulation capable of surviving hundreds to thousands of kilometers.

Map NVIDIA’s $6B worth of partners onto these three layers, and the investment structure becomes much clearer.

NVIDIA’s $6B optical investment is not simply supply chain insurance. It is a structural design to bind optical architecture to its own ecosystem across every layer, from scale-up to scale-across.

Section 1: NVLink Fusion, Why NVIDIA Opened Its Proprietary Interconnect

NVLink’s Role: Making the Entire Rack Act as One GPU

NVLink is the high-speed direct-connect fabric between NVIDIA GPUs. If PCIe is a peripheral bus connecting GPUs to the CPU, NVLink is a memory-semantic interconnect that lets GPUs communicate directly as if sharing memory.

The Blackwell generation’s NVLink 5 supported 1.8 TB/s bidirectional bandwidth per GPU. In the GB200 NVL72 rack, connecting 72 GPUs in an all-to-all topology yields 130 TB/s of aggregate bandwidth.[7] That’s one NVLink domain, and NVIDIA describes GPUs within this domain as operating like a single massive accelerator.

The Rubin generation steps up to NVLink 6. Bandwidth doubles to 3.6 TB/s bidirectional per GPU, and the Vera Rubin NVL72 rack supports a total of 260 TB/s of scale-up bandwidth.[8] For model architectures like MoE (Mixture-of-Experts) where all-to-all communication is frequent, this bandwidth difference directly translates to processing speed.

NVLink Fusion: Open the Ecosystem, but I Write the Rules

NVLink used to be a proprietary interconnect exclusive to NVIDIA GPUs. Starting in 2025, NVIDIA began opening this fabric to third-party silicon under the name NVLink Fusion.[4][9]

Here’s how it works. External XPUs connect to the NVLink fabric through a UCIe (Universal Chiplet Interconnect Express) bridge. NVIDIA provides the UCIe-to-NVLink bridge chiplet, and XPU designers can operate within the same scale-up fabric alongside NVIDIA GPUs.[9] In the NVLink Fusion ecosystem, NVIDIA provides the Vera CPU, ConnectX SuperNIC, BlueField DPU, NVLink interconnect and switches, Spectrum-X switches, and OCP MGX-based rack architecture. Partners layer custom XPUs and NVLink Fusion-compatible scale-up networking on top.[3]

Why open a proprietary fabric? Hyperscalers (Amazon, Google, Microsoft, etc.) are already deploying their own custom AI accelerators. Trainium, TPU, Maia. They have the motivation to route around NVIDIA’s expensive GPUs. At the same time, the UALink consortium, led by AMD, Intel, Google, Microsoft, AWS and others, is pushing an open interconnect standard.[26]

NVIDIA’s response: “Don’t use my GPU if you don’t want to. But play inside my NVLink fabric.” Hyperscalers get to use custom silicon optimized for their workloads while keeping NVIDIA’s software stack and proven rack architecture. NVIDIA, in turn, holds the interconnect standard and maintains attach rate (the ratio of ancillary product and service revenue per GPU sale) on NICs, DPUs, switches, and software.

NVLink Fusion is not about maximizing GPU sales. It’s a structure for NVIDIA to keep defining the AI factory architecture standard. It looks open, but NVIDIA writes the rules of that openness.

Section 2: Why Marvell Became the First NVLink Fusion Partner

The Position Fits Perfectly

In this deal, Marvell provides two things: NVLink Fusion-compatible custom XPUs and NVLink Fusion-compatible scale-up networking. The partnership also includes AI-RAN collaboration for 5G/6G telecom infrastructure, but this article focuses on optical interconnects.[3]

To understand “why Marvell,” you need to look at what portfolio they’ve built over the past 3 to 4 years. Marvell started as a communications semiconductor company and has transformed into one covering the full scope of data center AI infrastructure. In FY2026, data center revenue accounted for 74% of total revenue ($6.1B), and total revenue grew 42% year-over-year to $8.2B.[10] In custom XPU programs (contract design of hyperscaler custom silicon, such as Google TPU), they’ve built a substantial track record. As of the FY2026 earnings, over 18 XPU and XPU-attached sockets are in volume production, and a pipeline of over 50 new design opportunities is in progress with more than 10 customers.[10]

Their optical DSP portfolio fills all three scale layers:

A semiconductor company that covers all three scale layers with an optical portfolio is rare in the industry.

Celestial AI Acquisition: A Major Bet on Scale-Up Optics

In December 2025, Marvell announced the acquisition of Celestial AI for $3.25B ($1B cash + $2.25B stock), and the deal closed in February 2026.[11]

The technology Celestial AI developed is a platform called Photonic Fabric. At its core is OMIB (Optical Multi-Chip Interconnect Bridge), an optical die-to-die interconnect technology that handles package-level, system-level, and rack-level connections entirely through optics.[11] Marvell’s thesis is that this technology can break through the physical limits of copper in the scale-up domain.

For context, the 9-meter 800G AEC that Marvell and Infraeo demonstrated at the OCP Global Summit is symbolic.[12] Pushing copper to 9 meters is an impressive achievement. Previous 800G AEC products topped out at 3 to 5 meters, and nearly doubling that distance to the maximum demonstrated at a conference means we’re looking at the ceiling of current technology. At the same time, it signals that copper can’t go much further. PAM4 signals suffer sharply increasing attenuation in copper as frequency rises, and extending distance requires additional power and retimers to compensate. 9 meters is effectively the upper bound of what copper can sustain at 800G with current technology. As XPUs scale from tens to hundreds within a scale-up domain, the transition from copper to optics is a physical inevitability.[5]

Celestial’s Photonic Fabric targets exactly that inflection point. Marvell plans to integrate it into their custom XPU architecture, designing scale-up domains that connect hundreds of XPUs across racks using optics.[13]

Marvell being chosen as the first NVLink Fusion partner is not a coincidence. Custom XPU design capability, an optical DSP portfolio covering all three layers, and the next-generation scale-up optical technology secured through the Celestial AI acquisition all lined up at once.

Section 3: Celestial AI Photonic Fabric, the Technology and the Distance to Volume Production

Read more

NVIDIA’s string of multibillion-dollar investments in Lumentum, Coherent, and Marvell over the span of a single month signals that the SiPh optical interconnect supply chain is moving into serious production mode. Before any of those wafers can go into CPO packaging, they have to pass wafer-level test (WLT). On March 17 at OFC, Teradyne introduced the Photon 100, a purpose-built integrated ATE for SiPh. A natural question for any investor: does this threaten the existing SiPh test equipment players? This article answers that question directly. The SiPh WLT ecosystem is divided into three non-overlapping roles: burn-in screening (AEHR), wafer optical probing (FORM), and optical measurement (KEYS). Photon 100 is not a competitor to any of them. It fills a position that did not previously exist. And when you consider where Teradyne sits in the broader semiconductor ATE market, this move carries a structural message for the entire SiPh test ecosystem.

Contents

1. Why SiPh Testing Is So Demanding

2. The Three Pillars: AEHR, FORM, and KEYS

   • Aehr Test Systems: Burn-In Screening

   • FormFactor: Wafer Optical Probing

   • Keysight Technologies: Optical Measurement

3. Teradyne Photon 100: What the Announcement Actually Means

4. Summary: The Three Companies

5. How Big Is This Market, and How Does It Grow

6. Closing

NVIDIA announced three optical partnerships in the span of a month.

On March 2, it announced strategic partnerships with both Lumentum (LITE) and Coherent (COHR), investing $2 billion in each alongside multi-year purchase commitments.[1] On March 31, it added Marvell (MRVL) to that list, again with a $2 billion investment.[2] The Marvell announcement explicitly includes joint development of “optical interconnect solutions and silicon photonics technology” on top of the NVLink Fusion-compatible custom XPU collaboration.

All three partnerships point at the same thing: SiPh-based optical interconnects as the backbone of next-generation AI infrastructure. Lumentum and Coherent now need to produce lasers and optical components at scale, and every one of those wafers has to pass test before it goes anywhere near a CPO package. You cannot secure Known Good Dies (KGD) without wafer-level test.

So who does the testing?

This article covers the three companies that own the SiPh wafer test ecosystem. It also breaks down what Teradyne’s (TER) Photon 100 announcement actually means for them, and where the market goes from here.

1. Why SiPh Testing Is So Demanding

CPO integrates GPU dies with Photonic Integrated Circuits (PIC) into a single package. If a defect shows up after packaging, you scrap the entire module, which can run thousands of dollars. Securing KGD before packaging is not optional; it is the entire reason WLT exists.

Two specific challenges make SiPh WLT uniquely difficult.

First, the compound semiconductors used as light sources, particularly Indium Phosphide (InP)-based laser diodes, are highly vulnerable to thermal degradation. Burn-in testing, applying concentrated electrical and thermal stress to screen out early failures (infant mortality), is mandatory.

Second, aligning a Fiber Array Unit (FAU) to the grating couplers on the wafer surface requires nanometer-level precision. FAU coupling efficiency is a determining factor in SiPh device performance,[3] and even slight misalignment produces insertion loss. Automating this alignment at production scale is the single biggest bottleneck in SiPh high-volume manufacturing.

Two core challenges for SiPh WLT: burn-in screening for compound semiconductors, and automating nm-level optical alignment.

2. The Three Pillars

The SiPh WLT line breaks into three distinct layers. Each has a dedicated player, and none of them overlap.

Aehr Test Systems (AEHR): Burn-In Screening

Aehr Test Systems is a pure-play wafer-level burn-in (WLBI) company.

InP-based laser diodes are susceptible to both electrical and thermal stress. The goal of burn-in is to apply that stress early and hard, forcing weak devices to fail before they reach packaging. Doing this at the wafer level, before individual die separation, is what WLBI is about. The cost of discovering a defective laser after it has been packaged into a CPO module is far higher than catching it at the wafer stage.

Aehr’s core platform is the FOX-XP, capable of applying up to 3,500 watts per wafer in a high-power burn-in configuration while processing nine wafers in parallel. That high-power FOX-XP configuration is already installed and running in production at a world-leading SiPh IC supplier.[4]

On March 31, the same day as the NVIDIA-Marvell partnership announcement, Aehr disclosed a significant new customer win. A major new customer described as a global leader in networking products and a major supplier to the data center optical transceiver market placed an initial order for SiPh WLBI systems.[4] The customer is developing SiPh-based transceivers and Optical I/O products for hyperscale AI and cloud data center deployments. The order covers a FOX-XP system configured for nine wafers in parallel, a WaferPak Auto Aligner, multiple FOX-NP systems, and full production sets of WaferPak Contactors. Shipment is scheduled within Aehr’s fiscal Q4 ending May 29, 2026. The customer has already provided a forecast for additional systems, with follow-on orders possible as early as later this calendar year.

Aehr CEO Gayn Erickson highlighted that the customer purchased systems for both engineering qualification and high-volume production upfront, which reflects the urgency of the ramp already underway. As SiPh laser wafer production volumes increase, WLBI demand follows directly.

FormFactor (FORM): Wafer Optical Probing

FormFactor is the industry standard for SiPh wafer probing. Its distributor PSI Solutions lists the CM300xi-SiPh as the “Industry standard for vertical coupling to wafer-level grating couplers,”[5] and the system is currently in use at over 100 leading SiPh device manufacturers worldwide.[6]

The CM300xi-SiPh has a six-axis precision hexapod motion stage from Germany’s Physik Instrumente (PI) built directly into the system.[7] This handles the active alignment of the FAU to the wafer’s grating couplers at nm-level precision. FormFactor’s official documentation lists both PI (positioning) and Keysight Technologies (measurement instrumentation) as “Preferred Partners” for SiPh WLT,[8] which tells you a lot about how the ecosystem is structured.

On top of the PI hexapod, the system ships with the Pharos probe card,[9] SiPh-Tools software, and the OptoVue autonomous calibration system, all packaged into a solution that is ready for production measurements immediately after installation. FormFactor’s own description: “first verified integrated measurement solution on the market that enables engineering and production-proven, optimized optical measurements right after installation, without further development.”

In December 2025, FormFactor acquired Keystone Photonics, a specialist in optical coupling technology for SiPh probing.[10] Management described the acquisition as reinforcing their “lab-to-fab” position, meaning test continuity from early R&D through high-volume production.

Keysight Technologies (KEYS): Optical Measurement

Keysight handles the optical measurement side as FormFactor’s official Preferred Partner, supplying the instruments that actually send and receive optical signals and extract measurement data.[8]

At the wafer level, that means Tunable Laser Sources (TLS) and Power Meters (PM) for measuring insertion loss (IL) and polarization-dependent loss (PDL), alongside Optical Spectrum Analyzers (OSA). At the package and module level, it means BERTs and oscilloscopes for verifying the signal integrity (SI) of 800G and 1.6T transceivers.

Historically, customers buying CM300xi-SiPh systems sourced these instruments separately, integrated the software themselves, and maintained the multi-vendor stack on their own. That worked well enough in engineering environments. At HVM scale, that integration burden becomes a production bottleneck.

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3. Teradyne Photon 100: What the Announcement Actually Means

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POET Technologies dropped its Q4 2025 results on March 31, and the market responded with a 16.93% surge to $5.94 at close. That reaction alone tells you the headline loss number wasn’t what investors were reading. On the surface, a $42.7M net loss against $341K in revenue looks brutal. But that framing misses the structure of this quarter entirely.

This piece breaks down what the numbers actually say, what the product roadmap signals, and what investors tracking the silicon photonics value chain should be watching in the next two quarters.

The Loss Is Not What It Looks Like

Of the $42.7M net loss, cash out the door from operations was $11.6M. The rest is accounting.

The single largest line item — $30.6M — was a non-cash fair value adjustment on derivative warrant liabilities. These are warrants originally denominated in Canadian dollars, which get remeasured every quarter based on stock price movements. POET’s stock rose during Q3, warrants were issued, and the accounting math produced a large non-cash charge. Subsequent to year-end, the company repriced the majority of those CAD-denominated warrants to their USD equivalent. That action effectively eliminates this recurring noise going forward.

The other notable non-cash item: a $6.85M loss on acquiring the remaining 24.8% of SPX (its Singapore subsidiary) from SAIC, completing full internalization of that operation.

Strip both items out and you are looking at a company burning roughly $11-12M per quarter in real cash — against a $430M cash balance. That is approximately 37 quarters of runway at current burn, before any revenue ramp is factored in. Even if quarterly cash burn tripled from here, the runway still exceeds three years.

The cash pile matters. $225M raised in Q4 alone, plus an additional $150M in January 2026, with all three financing rounds executed at prices higher than prior rounds. Institutional investors stepped in at progressively higher prices. That is not nothing.

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Over the past few weeks, PhotonCap has consistently maintained its spot in the Substack Tech Rising. I’m deeply grateful for the overwhelming support from this community. It is incredibly humbling to see this research being read by professionals across leading quantitative funds, institutional investors, and the semiconductor industry.

I’m writing this quick note to give you a final heads-up.

The early supporter permanent lock-in rate ($8/month or $80/year) ends on March 31 as I mentioned here:

Starting next month, the new pricing of $20/month ($150/year) will take effect for all new subscribers to reflect the depth of the institutional-grade research provided here.

If you’ve been finding value in the free posts and have been considering upgrading, now is the best time. By upgrading before the March 31 deadline, your price will be locked in at $8/month forever.

You can see the details about me: https://photoncap.substack.com/about

Thank you again for reading and supporting PhotonCap.

Cheers,

PhotonCap

As of OFC 2026, organic electro-optic (EO) polymer modulators are simultaneously entering the PDKs of major SiPho foundries. Within two weeks, LWLG (Perkinamine) and NLM Photonics (Selerion) initiated integration at Tower, GlobalFoundries, and SilTerra. This article analyzes how organic EO polymers overcome the ~50 GHz bandwidth ceiling of silicon depletion modulators, the technical differences between Perkinamine and Selerion (guest-host vs crosslinkable thermoset glass), foundry-by-foundry PDK integration status, a fair comparison with TFLN (including CTE thermal stress concerns), and the hurdles remaining before commercialization. From an investment perspective, we map the value chain across LWLG (the only listed pure-play), TSEM, GFS, and ***, and present a H2 2026 event calendar.

Contents

1. Intro

2. Background: Why Silicon Alone Is Not Enough

3. The Materials Race: Perkinamine vs Selerion

4. Foundry Integration Status: Who Is Using Whose Material?

5. Hurdles Remaining Before Commercialization

6. Investment Implications

7. Closing

Intro

It has been a week since OFC 2026 wrapped up. One of the most striking themes at this year’s show in LA was organic electro-optic (OEO) polymer modulators.

On March 16 alone, three press releases dropped. NLM Photonics announced a 1.6T/3.2T SOH (Silicon-Organic Hybrid) PIC tapeout at GlobalFoundries (GFS) AMF HP process [1] and validation of SOH modulators on Tower Semiconductor’s (TSEM) PH18M platform via an MPW run [2]. On the same day, LWLG announced integration of its modulator platform into the GDSFactory PDK for GFS’s silicon photonics platform [3]. Two material companies opening PDKs at GFS and Tower simultaneously.

Five days earlier, on March 11, Lightwave Logic (LWLG) announced a development agreement with Tower Semiconductor [4]. And on March 3, it unveiled an EO polymer modulator platform available through a Luceda Photonics PDK on the SilTerra foundry [5].

Here is what happened in the span of two weeks: two organic EO material companies began integration at three SiPho foundries simultaneously.

I covered the LWLG-TSEM development agreement in a previous article [6]. Today, I am widening the scope to look at the organic EO polymer material category itself. Why these materials are getting attention now, who is competing with what technology, how foundries are moving, and what investment implications emerge from this trend.

Core thesis: Organic EO polymer material companies are racing to secure PDK slots at major SiPho foundries, and the foundries are embracing this as an opportunity to expand their modulator menu. Organic EO polymers do not replace silicon. They extend silicon into performance territory that silicon alone cannot reach.

Background: Why Silicon Alone Is Not Enough

Before we jump in, a quick word on what “organic EO polymers” actually are. Most materials familiar in semiconductors and optoelectronics are inorganic: silicon, lithium niobate, InP, GaAs. These are crystalline materials with atoms arranged in regular lattice structures. They are well understood, stable, and thoroughly covered in textbooks. Polymers, by contrast, are carbon-based organic macromolecules. Think plastics. They can be deposited onto silicon wafers through solution processes like spin coating, and they process at low temperatures. The traditional weakness has been degradation under heat and light. The reaction “an organic material for optical modulators?” is understandable.

So why are SiPho foundries paying attention to this organic material now? Let’s start with the market context.

According to LightCounting Research estimates cited by LWLG CEO LeMaitre in the Q4 2025 earnings call (3/5), silicon photonics’ share of optical transceiver revenue rose from 10% in 2018 to 33% in 2024, and is projected to cross 50% for the first time in 2026 [7]. The 100G+ Ethernet optical transceiver and CPO market is expected to grow from ~$16.5B in 2025 to ~$26B in 2026, marking two consecutive years of 60% growth [7]. 1.6T transceiver revenue alone is projected to exceed $1B in 2026, with 3.2T volume production slated for 2028 [7].

Silicon photonics is taking over the transceiver market at a rapid pace. So why is there talk of “silicon alone not being enough”? The modulator’s physical limits.

To understand this article’s context, we need to start with how silicon photonics modulators work.

Most commercial silicon modulators today use carrier depletion. A reverse bias is applied to a PN junction, widening the depletion region, changing the free carrier density, and altering silicon’s refractive index to create phase modulation [8]. This is known as the Free-Carrier Dispersion (FCD) effect.

The problem is that this effect is inherently weak. Because the refractive index change (Δn) is small, you need modulator lengths of several mm and drive voltages of several volts to get sufficient phase shift. On top of that, FCD is not a pure phase modulation. It also produces electroabsorption, which degrades signal quality at high speeds [8].

As a result, silicon modulators hit an EO bandwidth ceiling around 50 GHz [8]. This limit comes from a combination of photon lifetime and RC time constant constraints. A comprehensive IEEE JSTQE review of SOH/POH modulator technologies reaches the same diagnosis [9]. Until now, that was fine. For 100G/lane, 50 GBaud PAM4 was sufficient. But 200G/lane and 400G/lane change the picture. Hitting 100 GBaud or even 200 GBaud PAM4 requires EO bandwidths above 100 GHz, and silicon depletion modulators simply cannot get there.

One point to make here: why drive voltage matters.

Power efficiency is a core metric in AI datacenter optical interconnects. The industry roadmap (OIF and others) targets around 5 pJ/bit for next-generation links. High modulator drive voltage means high driver IC power consumption, which eats into the total transceiver power budget. Ideally, you want a modulator that can be driven directly at CMOS logic levels (sub-1V). That is how you eliminate or minimize the driver, which is the path to LPO (Linear Pluggable Optics).

So what are the alternatives?

Both TFLN and organic EO polymers use the Pockels effect (linear change in refractive index proportional to electric field) instead of silicon’s FCD. FCD changes carrier density to alter the refractive index, an “indirect” approach. The Pockels effect changes the refractive index directly through the applied electric field. The response is inherently fast, and pure phase modulation is possible, which means better signal quality. But silicon crystals have centrosymmetry, so the Pockels effect does not exist in silicon. To use it, you need to place a non-centrosymmetric material like LiNbO₃ or organic EO polymers on top of silicon.

TFLN (Thin-Film Lithium Niobate) is already commercializing rapidly through companies like HyperLight, and it has real strengths in bandwidth and material stability. As an inorganic crystal, it does not have the thermal degradation or photo-oxidation issues that organic materials face. That is a significant advantage.

But TFLN is not completely free from reliability concerns either. A study published in Applied Optics in March 2026 by CEPREI (China Electronic Product Reliability and Environmental Testing Research Institute) is interesting. They applied temperature cycling tests (-30°C to 95°C) to TFLN MZMs, and after 168 cycles, insertion loss spiked by ~3 dB, exceeding the failure criterion [10]. The root cause is residual stress accumulation from a ~15x CTE mismatch between the LN thin film (CTE ~7.5x10⁻⁶/K) and the SiO₂ cladding (CTE ~0.5x10⁻⁶/K). This stress alters the waveguide’s effective refractive index through the stress-optic effect, causing mode divergence and light leakage [10].

Some caveats apply. The tested device specs (Vπ 3.5V, BW 20 GHz) are significantly behind the current TFLN state of the art (VπL < 2 V·cm, BW > 100 GHz). Only 1 out of 3 samples failed. And it is unclear whether the observed defects were generated by temperature cycling or were pre-existing fabrication artifacts. Still, this study provides counter-evidence to the assumption that TFLN, being an inorganic crystal, is “inherently safe.” If organic EO polymer’s reliability risks are photo-oxidation and depoling, TFLN’s reliability risk is CTE-mismatch-driven thermal stress fatigue. Both sides carry their own reliability challenges.

Beyond reliability, TFLN has other structural disadvantages. LiNbO₃ crystal supply is concentrated in China, and its high relative permittivity (~28-30) makes RF-to-optical velocity matching difficult [8]. Most importantly, from a foundry’s perspective, TFLN integration requires high-temperature processing and heterogeneous material handling that are hard to reconcile with existing CMOS lines.

Organic EO polymers take a different approach. A slot waveguide is formed on the silicon wafer, and EO polymer is deposited into the narrow slot. This is called the SOH (Silicon-Organic Hybrid) platform [8]. The polymer is deposited via spin coating or solution processing at below 150°C, which means it can be inserted at the BEOL (Back-End-Of-Line) stage of a silicon foundry [8][11]. Since you build the SiPho chip first and then add the polymer in the final step, contamination risk to the foundry line is relatively low.

LWLG uses an analogy with OLEDs. Just as organic emitting materials in OLED displays are deposited onto TFT backplanes, EO polymers are deposited onto SiPho wafers as a “post-process” [11]. From a foundry’s perspective, this is an option to boost modulator performance one level up while keeping the existing SiPho process line intact.

Key takeaway: In the 400G/lane era, the physical limits of silicon depletion modulators (~50 GHz, multi-V drive) are becoming clear. Organic EO polymers offer a Pockels-effect-based path to high-speed (100 GHz+), low-voltage (sub-1V) modulation through a CMOS BEOL-compatible process.

The Materials Race: Perkinamine vs Selerion

Two companies are pushing the hardest to commercialize organic EO polymers right now. Lightwave Logic (LWLG) with Perkinamine, and NLM Photonics with Selerion. Both target hybrid integration with silicon photonics, but their technical approaches and go-to-market strategies are distinctly different.

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Welcome back. This is PhotonCap.

In Part 1, we looked at the 1,000x mode mismatch between optical fibers and chips, then compared six coupling techniques (edge, grating, evanescent, freeform, cantilever, and photonic wire bonding) and their trade-offs.

Part 2 widens the lens. “Who is packaging CPO, with what F2C (Fiber-to-Chip) technology, at which foundry, and with which components?” We map the entire value chain. We compare the coupling choices behind NVIDIA, Broadcom, and Marvell’s CPO switches, examine how four foundries are baking F2C into their process flows, trace why M&A is accelerating in this space, and walk through the real-world assembly challenges of photonic vias, glass substrates, epoxy shrinkage, and thermal stress.

Section 9 (CPO architecture comparison) is free. Section 10 onward is for paid subscribers.

9. CPO Architecture by Product: Who Chose Which F2C Approach?

Let’s see how the coupling techniques from Part 1 are actually showing up in real products. NVIDIA, Broadcom, Intel, and Marvell are shipping or demoing CPO switches. Lightmatter and Ayar Labs are pursuing optical I/O chiplets and interposers. Nubis (now Ciena) is doing 2D surface coupling. Xscape Photonics is tackling on-chip multi-wavelength lasers. That’s at least eight competing approaches to F2C.

NVIDIA Quantum-X800 / Spectrum-X Photonics

NVIDIA unveiled two silicon photonics CPO switches at GTC 2025 [1][2].

Quantum-X800 is the InfiniBand platform, built around a 28.8 Tbps ASIC (107 billion transistors, TSMC 4N) surrounded by six optical sub-assemblies. Each sub-assembly carries three engines, for a total of 18 x 1.6T silicon photonics engines [3]. Each engine takes CW-DFB laser light from an ELS (External Light Source) and modulates it with 200 Gbps micro-ring modulators (MRM) [2][3].

The F2C story here centers on TSMC’s COUPE (Compact Universal Photonic Engine) platform. A PIC (65nm process) and EIC (6nm process) are 3D-stacked via SoIC-X, with vertical O-band grating couplers on the surface coupling to fiber through micro-lens arrays [2][4]. COUPE reports fiber-array coupling loss at the 0.3 dB level [4]. The Quantum-X800 uses COUPE Gen 1 (1.6 Tbps engine for OSFP), with initial shipments in late 2025 and volume ramp in 2026 [4][5]. This design leans heavily on the grating coupler advantages from Part 1 Section 4: 2D arrays anywhere on the chip surface, plus wafer-scale passive alignment.

Per NVIDIA’s official blog, the F2C supply chain includes TSMC (COUPE process), SPIL (packaging), Lumentum/Sumitomo/Coherent (ELS assembly and optical alignment/test), Corning/Senko/Browave/TFC (connectors and fiber assemblies), and Foxconn/Fabrinet (system assembly) [2]. Quantum-X InfiniBand ships H2 2025. Spectrum-X Ethernet (SN6810: 102.4 Tbps) ships 2026 [1][2].

Broadcom Bailly / Davisson

Broadcom has the most generational depth in CPO. Three generations shipped so far [6][7]. Gen 1 TH4-Humboldt (2021) was a learning platform: Tomahawk 4 at 25.6 Tbps, a hybrid mix of optical (4x 3.2T SCIP engines) and electrical (32x QSFP112) channels. Tencent ran the initial deployment.

Gen 2 TH5-Bailly was the industry’s first volume-production 51.2 Tbps CPO Ethernet switch. Eight 6.4T SiPho optical engines, and Meta validated it with millions of hours of field testing [7]. The F2C structure uses TSMC COUPE, same as NVIDIA, and Corning supplies the Photonic Grade FAU, specialized fibers (including CPO FlexConnect), and high-density connectors [8]. Corning positions alignment precision to PIC waveguides as their core differentiator [8].

Gen 3 TH6-Davisson (BCM78919) started shipping in October 2025. 102.4 Tbps, 200G/lane, doubling Bailly’s bandwidth [6][7]. Sixteen 6.4T Davisson DR optical engines on TSMC COUPE Gen 2 [6]. Package size grew to roughly 120mm x 120mm, and the laser module now uses the ELSFP form factor, making it field-replaceable [6][7]. This tracks closely with OIF (Optical Internetworking Forum) standardization efforts, which suggests Broadcom is aiming for interoperability rather than a closed ecosystem. Power is 3.5W per 800G port, more than 70% lower than pluggable optical interconnects [6]. A Gen 4 CPO (400G/lane) is already in development [6].

Intel OCI (Optical Compute Interconnect)

Intel’s F2C philosophy is fundamentally different from the rest of the CPO field. The key differentiator: no External Light Source (ELS) needed [9][10].

Intel’s OCI chiplet integrates DWDM laser arrays and semiconductor optical amplifiers (SOA) directly on-chip in a single SiPho PIC [9]. Instead of pulling laser light from an external module (the NVIDIA/Broadcom COUPE + ELS approach), Intel has internalized this with over 25 years of hybrid laser-on-wafer technology. The production track record: 8 million+ PICs shipped, 32 million+ on-chip lasers [9].

The Gen 1 OCI chiplet demonstrated at OFC 2024 delivers 4 Tbps bidirectional, PCIe Gen5 compatible, pushing 8-wavelength DWDM (200 GHz spacing) across 8 fiber pairs for 64 channels at 32 Gbps each [9]. Power consumption is 5 pJ/bit, 3x more efficient than pluggables (~15 pJ/bit), with a roadmap to 32 Tbps [9]. Like Ayar Labs’ UCIe chiplet, it targets universal co-packaging with any SoC (CPU, GPU, IPU).

From an F2C standpoint, Intel’s other big contribution is the Detachable Optical Chiplet Connector [10]. Published by Psaila et al. in JLT (2023), this uses a glass-integrated waveguide Optical Bridge to connect the PIC to fibers in a detachable configuration [10]. Insertion loss is under 0.4 dB, repeatability is within +/-0.05 dB across multiple mate/demate cycles, and it survives 260C solder reflow [10]. That last point matters a lot. It means you can run the full electronic packaging flow (reflow included), then attach the optical connector afterward, and everything still works. This is a fundamental workaround for the epoxy shrinkage problem we’ll cover in Section 13.

Intel also holds 600+ patents on glass substrates [11], making it a core IP holder for the glass-based CPO story in Section 12.

Marvell TX9190

Marvell demoed the TX9190 liquid-cooled CPO switch at OCP Global Summit 2025, jointly with Jabil [12][13]. The base ASIC is the Teralynx 10 (51.2 Tbps), the same die already in volume production for copper switches [12]. The TX9190 is the CPO version with co-packaged optical engines.

Marvell’s F2C approach has evolved across generations. In Nagarajan et al.’s 2023 IEEE JSTQE paper, the architecture heterogeneously integrates DRV/TIA/DFB lasers on a SiPho interposer in 2.5D, then edge-couples a PLC (Planar Lightwave Circuit) fiber array assembly. Coupling loss was under 1 dB [14]. But the TX9190 (OCP 2025) uses SENKO’s Metallic PIC Coupler (MPC) [13]. The MPC is a microlens-based detachable connector that couples vertically to the PIC surface, the same family as the SSC + trench + microlens architecture that SENKO and GFS announced at ECOC 2025 [15]. In other words, Marvell appears to have transitioned from PLC FA (edge) to MPC (vertical coupling). Each XPU connects to four 6.4T light engines, each engine carrying two 36-fiber MPCs [13]. Per tray: 4 XPU × 4 engines × 2 MPC × 36 fibers = 1,152 fibers. Marvell’s blog quotes over 36,000 fibers at the rack scale [13]. Working backward, that corresponds to roughly 32 trays (36,000 / 1,152 ≈ 31.25).

Nubis Communications (now Ciena)

Nubis was founded by Peter Winzer in 2020 and acquired by Ciena for $270M in 2025 [16].

The F2C differentiator is 2D surface coupling [17]. This fundamentally sidesteps the “beachfront bottleneck” from Part 1 Section 3.3. Thirty-six fibers (32 data + 4 ELS) sit in a 3x12 2D array and couple through grating couplers on the chip surface [17]. The optical engine itself measures 5mm x 7.5mm, housed on a 15mm x 15mm XT1600 module substrate [17]. Full-duplex 1.6 Tbps at under 4 pJ/bit [16][17].

A 2025 Optics Express paper published the measured performance data [18]. The SDA (Silicon Die Assembly) measures 6.9mm x 8.5mm, running 16 x 106.25 Gbps full-duplex linear-drive, achieving a chiplet edge I/O density of 246 Gbps/mm (SDA edge basis, scalable to Tbps/mm with 2D arraying), operates at up to 85C case temperature without significant degradation, reaches 2 km on standard SMF, and bridges 58 dB of total electrical link loss between TX and RX SerDes using built-in analog equalization [18]. Achieving this without a DSP retimer is the key point. Nubis/Ciena partnered with Samtec to announce the 200G/lane Vesta 200 6.4T CPX (copper and optics interchangeable in the same footprint) [19].

Lightmatter Passage

Lightmatter differentiates with a 3D photonic interposer approach [20][21]. Passage M1000 is a multi-reticle active photonic interposer exceeding 4,000mm², delivering 114 Tbps total optical bandwidth [20]. It’s made of 8 tiles with reconfigurable waveguide mesh and optical circuit switching (OCS) built in [20][21].

From an F2C perspective, M1000 completely eliminates the beachfront bottleneck. It provides electro-optical I/O from anywhere on the surface to die complexes stacked above, with 256 fibers edge-attached [20]. Modulation uses micro-ring modulators with 16-wavelength WDM [21]. Foundry is GFS GF Fotonix, packaging by Amkor [20]. The ELS is Lightmatter’s in-house Guide light engine (16 wavelengths) [20].

Passage L200 is the 3D CPO chiplet: 32 Tbps (L200) / 64 Tbps (L200X), with UCIe interface support [21]. Shipping expected in 2026 [21].

Ayar Labs

Ayar Labs takes the “optical I/O chiplet” approach. Not a switch-specific CPO, but a universal optical chiplet [22][23].

The Gen 3 TeraPHY chiplet is fabricated on GFS 45SPCLO 45nm SiPho, delivering 8 Tbps bidirectional [22][23]. It’s the industry’s first UCIe (Universal Chiplet Interconnect Express) optical chiplet, protocol-agnostic across CXL, NVLink, UALink, and Ethernet [22]. Modulation is MRM with 16-wavelength WDM, using the SuperNova DFB 16-wavelength ELS [22]. F2C is edge coupler + detachable optical connector, coupling at the PIC facet with post-assembly detachability [23]. At TSMC OIP 2025, Alchip and Ayar Labs demoed a prototype integrating 2 accelerators + 8 TeraPHY chiplets + 8 HBM stacks, reaching 100+ Tbps scale-up bandwidth per accelerator [24].

Xscape Photonics: Multi-Wavelength Comb Laser

Xscape Photonics is not an F2C play per se, but it affects CPO light source architecture, so it’s worth a brief mention. Backed by NVIDIA and Cisco, this U.S. startup built an on-chip optically-pumped multi-wavelength laser (ChromX) on Tower’s PH18 platform [25]. It supports CWDM/DWDM grids and claims scalability up to 128 wavelengths [25]. In a DWDM CPO world where you want terabits per fiber, reducing the connector and fiber count through wavelength multiplication is a real benefit.

Key takeaway: NVIDIA and Broadcom are converging on TSMC COUPE (grating coupler + micro-lens). Intel built a standalone path with on-chip lasers + glass optical bridges, eliminating the ELS entirely. Marvell is transitioning to SENKO MPC (vertical coupling), Lightmatter and Ayar Labs take edge-coupler chiplets on GFS, and Nubis/Ciena pushes 2D surface coupling for density.

10. Foundry F2C Strategies: Baking Coupling into the Process

Section 9 covered F2C at the product level. Now let’s go one layer deeper: how foundries are embedding F2C solutions into their process flows and PDKs. The question is not just “who makes SiPho,” but “how does the foundry design coupling loss and alignment tolerance at the process level?”

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Intro

Sivers Semiconductors (OTCMKTS: SIVEF) surged +63.62% and QD Laser (TYO: 6613) jumped +33.39% over the past five days. What do these two microcaps have in common? They’re both light source suppliers for silicon photonics (SiPho).

Silicon photonics has a fatal weakness. Silicon can’t efficiently generate light. It’s an indirect bandgap material. You can make waveguides, modulators, and even detectors (by adding germanium), but the one thing you can’t make from silicon or silicon nitride (SiN) alone is a laser.

So every SiPho chip needs a III-V compound semiconductor (InP, GaAs, etc.) laser source attached to it from the outside. This “light source integration” problem is the most fundamental bottleneck in SiPho. It’s the primary reason packaging costs are high, form factors are large, and yields are lower than they should be.

Different approaches mean different risk-reward profiles. Japan-based QD Laser (TYO: 6613) uses GaAs-based quantum dot (QD) lasers, Sweden-based Sivers Semiconductors (STO: SIVE / OTCMKTS: SIVEF) uses InP-based DFB lasers, and US-based Aeluma (NASDAQ: ALMU) is growing III-V materials directly on 300mm silicon wafers through monolithic integration.

Today I’ll examine these two surging stocks alongside Aeluma, comparing all three across technology, strategy, and financials, while mapping the full optical module architecture from Gen 1 (EML) through Gen 4 (monolithic).

1. Background: Why SiPho Light Sources Matter Right Now

As AI datacenters scale, demand for optical interconnects is growing rapidly. Bandwidth requirements between GPU clusters are climbing from 800G to 1.6T, 3.2T, and eventually 6.4T. Copper wiring simply can’t keep up on power efficiency and distance.

The mainstream approach today is pluggable transceivers. But as bandwidth climbs, traditional pluggables based on externally modulated lasers (EMLs, Electro-Absorption Modulated Lasers) are hitting their performance ceiling [28]. Next-gen GPU architectures are pushing toward co-packaged optics (CPO), and CPO requires external light sources (ELS).

For a sense of market scale: LightCounting estimates the total integrated optical device market will reach approximately $30B by 2026, with SiPho-based products accounting for roughly half of that [2]. Northland Capital Markets analyst Tim Savageaux sees the ELS market alone as a $1B+ annual opportunity [3].

This brings us to the key question. How do you build the light source, and how do you deliver it to the SiPho chip? Datacenter transceiver light source architectures sit on a multi-generational evolutionary path. Understanding this framework is essential to seeing where the three companies fit.

Gen 1: EML (current standard, InP pluggable, supply-constrained)

An EML (Electro-Absorption Modulated Laser) integrates a DFB laser and an electro-absorption modulator (EAM) onto a single InP chip. The laser generates light and modulates data simultaneously. Modulation quality is high (low chirp), making it ideal for longer-reach transmission. It’s the current standard for 800G DR8 and 1.6T modules.

The problem is power consumption, heat, and cost/supply. An 800G EML module requires eight 100G EML lasers at ~$10+ each, bringing the laser cost alone to $80-100+ per module [28][29]. On top of that, NVIDIA has pre-allocated massive capacity from key suppliers like Lumentum and Coherent, pushing delivery lead times beyond 2027 for non-NVIDIA customers [28]. Estimates suggest 800G transceiver production could fall 40-60% short of demand through 2027 [28]. The Buy American momentum combined with this capacity crunch likely explains the recent sharp rally in Applied Optoelectronics (NASDAQ: AAOI), one of the few US-based EML producers with domestic manufacturing.

Gen 2: CW laser + SiPho (the EML alternative, scaling fast)

A CW (Continuous Wave) laser is a simple DFB laser that emits a steady, unmodulated beam. Think of it as a lightbulb that just shines constant light. The CW laser sits externally, while modulation, reception, wavelength multiplexing, and other optical functions are handled by the SiPho PIC. Data modulation is performed by either MZM (Mach-Zehnder Modulator) or MRM (Micro-Ring Modulator) on the SiPho chip. MZM splits light into two arms and uses phase differences to create constructive/destructive interference, encoding 1s and 0s. MRM uses a resonant structure for a smaller footprint and lower power, but is more temperature-sensitive and requires active feedback control [30].

The key advantage is cost reduction and high-volume production through CMOS processes. CW lasers are far simpler than EMLs, costing only ~$8-10 per chip, and multiple suppliers can produce them. A typical 800G/1.6T SiPho module requires 2-4 CW light sources (~70mW for 800G, ~100mW for 1.6T), bringing the total laser cost per module to just $20-40, less than half of the $80-100+ for EML-based modules [29]. The SiPho chip can be manufactured at CMOS fabs like GlobalFoundries, Tower, and TSMC, providing excellent scaling [30].

However, since this is still a pluggable form factor, electrical signals must travel from the switch ASIC to the front-panel transceiver over copper PCB traces. The signal loss over this distance and the power consumption of DSP/retimers to compensate for it are substantial. Of course, InP substrates for the CW lasers themselves still depend on a small number of suppliers like Sumitomo and AXT (NASDAQ: AXTI).

This DSP power problem gave rise to LPO (Linear Pluggable Optics). LPO removes the DSP entirely from inside the pluggable module, relying instead on the switch ASIC’s SerDes signal conditioning. The module’s TIA (Transimpedance Amplifier) and Driver operate in linear mode, simply passing the signal through. Since CPO adoption faces high barriers in packaging complexity, chiplet ecosystem maturity, and test/yield, LPO emerged as a pragmatic bridge: “skip the DSP, stretch pluggables through the 800G-1.6T generation.” The tradeoff is interoperability: without DSP signal conditioning, performance can vary across different host platforms.

The EML shortage is accelerating the CW+SiPho transition. LightCounting projects SiPho-based transceivers will exceed 50% market share by 2026 (up from 33% in 2024) [30]. Both Sivers’ InP DFB lasers and QD Laser’s quantum dot lasers are positioned as CW light source suppliers in this architecture. That said, I have some reservations about whether QD Laser’s quantum dot lasers have actually secured a competitive position in the SiPho datacenter market. More on this later.

Gen 2.5: NPO (Near-Packaged Optics, transitional)

A transitional step before full CPO. The optical engine moves from the switch front panel onto the main board near the ASIC, shortening electrical trace length. What’s notable is that Broadcom’s NPO uses VCSELs (Vertical-Cavity Surface-Emitting Lasers), not SiPho+CW lasers [36]. It operates over multimode fiber (MMF) for short-reach AI scale-up links (a few meters). Compared to CPO’s SiPho engines, VCSEL-based NPO is far simpler to package and leverages existing VCSEL supply chains and MMF infrastructure for faster production ramp. At OFC 2026, Broadcom announced a 3.2T VCSEL-based NPO solution [36].

The tradeoff: VCSELs are limited in reach and bandwidth due to their multimode nature, so rack-to-rack and longer distances still require SiPho-based CPO (Gen 3). NPO is a pragmatic bridge: “get past the copper wall without CPO’s complexity.”

Gen 3: CPO + ELS (next-gen, 2026-2028 ramp)

In co-packaged optics (CPO), the SiPho engine sits right next to the switch/GPU ASIC on the same substrate. But lasers are temperature-sensitive, so instead of placing them next to the hot ASIC, you put them in a separate module outside the package. That’s the external light source (ELS) [31].

Separating the laser means you can replace it if it fails, and thermal management improves. Several major products use this architecture: NVIDIA’s Quantum-X800 CPO (InfiniBand, TSMC COUPE SiPho platform + Lumentum lasers, shipping H2 2025), Broadcom’s Bailly (TH5-based 51.2T CPO Ethernet switch, the industry’s first volume-production CPO), and Marvell’s TX9190 (Teralynx-based liquid-cooled CPO switch, demoed with Jabil at OCP 2025) [30][31]. Broadcom is already shipping its next-gen CPO, TH6-Davisson (102.4Tbps, 200G/channel, TSMC COUPE) [35]. CPO ELS demands much higher output power (400mW class, roughly 4x standard CW) and stable operation at high temperatures (50C+) [30]. For more on why NVIDIA invested $4B in Coherent/Lumentum and a comparison of laser/optical module company specs, see my previous article [33].

The POET-Sivers partnership targets exactly this Gen 3 architecture [1]. QD Laser’s quantum dot lasers have excellent high-temperature stability in theory, but their current product output (5-16mW) is far below ELS requirements (400mW class), making near-term ELS market entry unlikely.

Gen 4: Monolithic III-V on Si (long-term, 2030+)

Growing III-V material directly on the Si wafer so no separate laser chip is needed at all. Instead of the “external laser + SiPho chip” approach of Gen 2/3, the laser is built into the SiPho chip itself. If successful, it minimizes packaging cost and achieves ultimate scalability, but lattice mismatch and defect density challenges are still being resolved.

Aeluma is betting directly on Gen 4.

Where the three companies sit

Architecture Timeline QD Laser Sivers Aeluma Gen 2. CW + SiPho pluggable Mainstreaming now CW source (QD CW) Core position (InP DFB CW) N/A Gen 3. CPO + ELS 2026-2028 Power gap limits near-term entry POET partnership N/A Gen 4. Monolithic 2030+ Related foundational tech N/A Core position

Key takeaway: Light source architecture is evolving from Gen 1 (EML) to Gen 2 (CW+SiPho) to Gen 3 (CPO/ELS) to Gen 4 (monolithic). The EML shortage is accelerating this transition, and the three companies are positioned at different stages along this evolutionary path.

2. Technology Deep-Dive: Three Solutions

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Introduction

On March 12, Hunterbrook Media and Citrini Research dropped reports at the same time. Citrini published “Let There Be Light,” an optics/connectivity basket update for paid subscribers [16], while Hunterbrook released their investigative deep dive on Himax, “Stealth Supplier for NVIDIA’s Optics Revolution,” for free [1].

The price action told a story. HIMX started moving well before the report came out, climbing from $7.4 on March 6 to $9.15 by March 11. On March 11, when the report dropped, the stock spiked to $12 intraday before pulling back hard in the afternoon.

By March 13, it was down again to $9.84. Volume on March 12 hit 36 million shares, roughly 30x the daily average [17]. The fact that the stock was already running before the report landed is worth thinking about, especially given that Hunterbrook Capital disclosed a long position in HIMX [1].

“About 36 million HIMX shares exchanged hands on Thursday, about 30 times the stock’s average trading volume. Himax shares have gained for four consecutive sessions, rising 60%.”

The report makes two big claims. First, that Himax is the “sole supplier” of microlens arrays for NVIDIA’s CPO (Co-Packaged Optics) platform. Second, that Himax is likely supplying LCoS microdisplays and waveguides for Apple’s upcoming smart glasses.

Citrini also has photonics names in their own paid basket [16]. Both reports are high-quality research, but both come with financial interests attached. Keep that in mind.

The core thesis of this article: Himax being the sole microlens supplier for TSMC’s COUPE Gen 1 and Gen 2 is real. But the market is overestimating the scope of that monopoly. Microlens arrays are one layer inside the FAU. V-grooves and FAU assembly are commodity work. And when you zoom out to the full NVIDIA CPO ecosystem, COUPE is not the only path.

Today, I am going to walk through the four patents Hunterbrook cited, the Tianfeng Securities analysis, NVIDIA’s official CPO partner list, and the actual competitive landscape.

Background: CPO and FAU, Why They Matter

At GTC in March 2025, Jensen Huang laid out a striking number: networking alone inside a million-GPU AI factory would consume 180 megawatts. That is because each GPU needs six pluggable transceivers, each burning roughly 30 watts [2].

“The question is: how do we scale up now to millions of GPUs?” said the CEO. “Because if we have a million GPUs [we need] 6 million transceivers [consuming] 180 megawatts.”

NVIDIA’s answer is CPO. Instead of converting electrical signals to light in a separate external box, CPO handles the conversion right inside the network switch package. This eliminates the external transceiver and cuts power consumption by about 3.5x. It runs on TSMC’s COUPE (Compact Universal Photonic Engine) platform and uses micro ring modulators (MRM) [2][3][20].

This is where the FAU (Fiber Array Unit) comes in. The COUPE optical engine shoots data-carrying laser light straight up. Something has to bend each beam 90 degrees and couple it into horizontal optical fibers thinner than a human hair. That “something” is a prism and a microlens array sitting inside the FAU. The V-groove substrate that holds the fibers in precise alignment is also part of the FAU [3].

For reference, you can see exactly where the FAU sits within a CPO module in our teardown of Marvell’s TX9190 at my latest article.

Himax manufactures the optical components inside this FAU (microlens arrays + prisms + V-groove substrates) using nanoimprint lithography (NIL). Instead of grinding lenses one at a time, NIL presses a mold into a glass wafer and stamps out hundreds of units in a single shot. Lenses on one side, 45-degree prisms on the other, all patterned simultaneously for tight alignment and high throughput. FOCI then assembles these components into finished FAUs and delivers them to TSMC [1][4].

And there is analyst confirmation backing this up. Digitimes, citing Tianfeng Securities analysts, reported that Himax is the sole microlens array supplier for both COUPE Gen 1 and Gen 2. FOCI exclusively supplies the FAUs (ReLFACon) for both generations, and a second source is unlikely before Gen 3 [18].

“Tianfeng Securities analysts noted heightened visibility for TSMC’s COUPE development, with Himax confirmed as the sole micro-lens array supplier for COUPE’s first and second generations. FOCI will exclusively supply FAUs (ReLFACon) for both generations.”

The timeline is specific. Gen 1 COUPE is scheduled for mass production in 2H 2026, with AMD as the first adopter. NVIDIA’s Rubin Ultra is likely to be the first product on Gen 2 COUPE, with production slated for late 2027 to early 2028 [18].

“The first-generation COUPE is set for mass production in the second half of 2026, with AMD poised as the initial adopter. If Nvidia’s Rubin and Rubin Ultra chips enter mass production by late 2026 and 2027, the Rubin Ultra is likely to debut TSMC’s COUPE technology.”

Bottom line: CPO is a must-have for AI data center power efficiency, and the FAU is not just bending light. It is the critical gateway for fiber-to-chip coupling (https://substack.com/@photoncap/p-190357700), connecting rack to rack, GPU to GPU. Himax being the sole microlens supplier for COUPE is real. The question is whether the scope of that monopoly is as wide as the market thinks.

1. What the Four Patents Actually Tell Us About Himax’s Technology

Hunterbrook built their case around four patents: two from Himax, one from FOCI, one from TSMC. I read all four in their original USPTO filings. (Thanks to @latent_value7 (X).)

Himax NIL Patent (US 2026/0003130 A1)

https://www.documentcloud.org/documents/27867115-himax-patent-nil-process-us-20260003130-a1/

https://www.linkedin.com/in/sam-kuo-32069b110/

Published January 2026, this is Himax’s core claim. It is a divisional patent split from parent application 18/371,249, and as Hunterbrook correctly identified, this divisional covers the nanoimprint lithography (NIL) manufacturing process [1][4]. Specifically, it describes using NIL to stamp V-groove substrates and lens/prism components on glass wafers at the wafer level, a method well suited for high-volume production.

One thing to keep in mind here: NIL itself is not proprietary to Himax. Companies like Canon (

SemiAnalysis

Nanoimprint Lithography: Stop Saying It Will Replace EUV

Every 6 months or so, we see another round of headlines about nanoimprint lithography disrupting EUV…

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5 months ago · 95 likes · 1 comment · Jeff Koch and Dylan Patel

), EVG, and SUSS MicroTec sell NIL equipment commercially, and the process is already widely used across the semiconductor and optics industries. What sets Himax apart is not the NIL “technology” per se, but the WLO (Wafer Level Optics) production experience they have built up since the late 2000s, more than 15 years of yield know-how [5]. That accumulated production expertise is most likely the real reason they locked in the COUPE sole-supplier position.

FOCI Lens-Type Fiber Array Patent (US 2026/0036750 A1)

https://www.documentcloud.org/documents/27867114-us-20260036750-a1/

Filed by FOCI Fiber Optic Communications in October 2024 and published February 2026. This patent describes a passive alignment structure using slide rails and protruding ribs that automatically position two fiber array modules at the correct focal length [6].

Here is what caught my eye: this patent makes zero mention of Himax. FOCI has its own independent IP covering the FAU structure. Himax supplies WLO components to FOCI, but FOCI is not structurally dependent on Himax to make FAUs.

TSMC FAU Inspection Tool Patent (US 2025/0383260 A1)

https://www.documentcloud.org/documents/27867117-tsmc-patent-inspection-tool-us-2025383260-a1/

This one was personally the most interesting to me. Filed by TSMC in June 2024 and published December 2025, it describes a 5-mode integrated inspection system specifically for FAU quality control in CPO applications [7].

The five inspection modes are: (1) visible camera for defect/pitch detection, (2) IR camera for 3D core pitch scanning, (3) beam profiler for MFD (Mode Field Diameter) measurement, (4) power meter for insertion loss, and (5) active alignment against a golden FAU reference.

Why does this matter? Because TSMC is building its own verification infrastructure for externally sourced FAUs. No specific supplier is named anywhere in the patent. The system is designed to accept FAUs from any supplier that meets spec. This is the opposite direction from single-supplier lock-in.

Hsia, Harry, et al. “EPIC-BOE: An electronic-photonic chiplet integration technology with IC processes for broadband optical engine applications.” 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024.

Hunterbrook pointed out that the FAU schematic in TSMC’s patent matches the Himax FAU structure. That is correct. But the vertical coupling FAU design (prism bending light 90 degrees into horizontal fibers) is an industry-standard architecture, not something unique to Himax [19].

Take, for example, Chinese company Meisu (https://www.meisuoptics.com/products/2d-fiber-arrays-assemblies/), which already manufactures 2D collimator arrays and 2D fiber arrays [21].

The 22-Channel “Smoking Gun”

Hunterbrook’s strongest circumstantial argument: the Himax patent shows exactly 22 lenses in its array diagram, and the TSMC inspection patent depicts 22 channels (ch1 through ch22). In the fiber optics world, 22 is a non-standard number (standard counts are 12, 16, 24, 32, 48, 64). This suggests both patents are describing the same component [1].

It is an interesting observation, and I personally give it high marks. But patent drawings use illustrative numbers. According to Hunterbrook, a separate Himax prism testing patent (TW I896409 B) explicitly states “16, 22, or 50 lenses, but the number is not limited thereto” [1]. The 22-channel overlap across multiple patents is worth noting, but it falls short of definitive proof.

Bottom line: Himax’s NIL production experience is a real capability backing their COUPE microlens monopoly. But NIL itself is a widely available process, TSMC’s inspection patent signals a structure that allows for long-term supplier diversification, and FOCI holds independent FAU-structure IP separate from Himax.

2. The Scope of the Monopoly: What the Market Is Missing

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Intro

One headline dropped right after the close today (March 11, 4:30 PM ET).

Lightwave Logic (NASDAQ: LWLG) and Tower Semiconductor (NASDAQ: TSEM) signed a development agreement. The deal: integrate LWLG’s electro-optic (EO) polymer modulator reference designs into Tower’s PH18 silicon photonics PDK (Process Design Kit) [1].

The market had already spoken before the formal announcement. LWLG rose +15.14% (+$0.66) during the regular session, and the official press release came right after the close (4:30 PM ET) [1]. In extended-hours trading, the stock hit a high of $7.28 (roughly +67% from the previous close of ~$4.36). The stock moving before the announcement suggests the market was already sensing and front-running the deal.

Here’s why this matters:

Tower Semiconductor — the foundry rapidly expanding its silicon photonics presence — just made its first formal bet on EO polymers as the “next-gen modulator material.”

The timing is worth noting. Just nine days ago (March 2), NVIDIA announced $2 billion investments each in Lumentum and Coherent — $4 billion total — for advanced optics R&D and US manufacturing [21]. Jensen Huang personally framed it as building “the next generation of gigawatt-scale AI factories” through silicon photonics [21]. And now, today, the TSEM-LWLG agreement drops. This isn’t an isolated event — it’s part of an accelerating chain of signals that AI optical infrastructure is entering a new phase.

Over the past 12 months, TSEM has been steadily building out its silicon photonics (SiPho) ecosystem. NVIDIA collaboration for 1.6T optical modules. Scintil for DWDM lasers. Salience Labs for optical switches. Each of those partnerships addressed a key layer of AI datacenter optical infrastructure. And today, a “materials” layer was added to that stack.

Today we’ll use TSEM’s SiPho strategy as our anchor to walk through LWLG’s technical moat, what this agreement really means, and where we go from here.

Background: TSEM’s SiPho Buildout

Starting with the financials

Tower Semiconductor’s Q4 2025 earnings were impressive. Revenue of $440 million (all-time record), up 14% YoY and 11% QoQ [2]. Full-year 2025 revenue came in at $1.57 billion, up 9% from 2024, with net income of $220 million [2].

But here’s the number that really jumps out. TSEM’s silicon photonics revenue went from $106 million in 2024 to $228 million in 2025 — more than doubling in a single year [3]. That’s roughly 15% of total revenue, but in terms of growth rate, SiPho has been the primary growth driver for the company. CEO Ellwanger noted on the earnings call that of the $82 million company-wide revenue increase from Q1 to Q4, about $40 million flowed through to net income — an incremental net margin of roughly 49% at the corporate level [3]. This isn’t a SiPho-only figure; it reflects the overall mix improvement as higher-value photonics revenue became a larger share of the total.

¹ SiPho revenue figure as cited in TSEM’s earnings call. Appears to be reported separately from SiGe RF infrastructure revenue, though exact segment definitions should be confirmed against official IR materials.

CEO Russell Ellwanger called it “value-based growth.” Translation: they’re selling expensive chips, and lots of them.

What’s even more telling is the forward investment. TSEM announced a total of $920 million in CapEx for SiPho and SiGe expansion. The plan targets full installation and qualification of all equipment by Q4 2026, with full production starts commencing in 2027. At completion, SiPho wafer starts are projected to reach 5x+ the Q4 2025 monthly run-rate [4]. The long-term financial model targets $2.84 billion in revenue by 2028, with 39.4% gross margin and 31.7% operating margin [5].

Why do these numbers matter?

$920 million in CapEx is roughly 60% of TSEM’s annual revenue. This isn’t just a capacity expansion — it’s a declaration that the company is transforming its identity from “specialty analog foundry” to “AI optical infrastructure foundry.”

And backing up that declaration, TSEM has been systematically building its SiPho ecosystem over the past 12 months. Here’s the timeline:

See the pattern?

Alcyon provides design tools (IP blocks), LightIC expands into new markets (LiDAR), NVIDIA serves as end-customer validation, Scintil delivers light sources (lasers), Salience Labs handles optical switching, and LWLG brings the modulator material. All running on a single SiPho platform.

The NVIDIA collaboration stands out to me the most. Having Gilad Shainer, Senior VP of Networking at NVIDIA, personally comment on the announcement signals that this isn’t just an MOU — it’s embedded in an actual infrastructure roadmap [8]. Tower’s SiPho platform offering 2x data rates versus prior solutions, combined with 300mm wafer capacity secured through an arrangement with Intel,² paints a picture of genuine scale-up capability.

² Tower’s corporate description references “a 300mm capacity corridor in Intel’s” facility. Industry media reports this as Intel’s New Mexico site, but the exact facility location and current operating arrangement should be confirmed via Tower IR materials.

Key Takeaway: TSEM doubled its SiPho revenue in one year and declared a $920M CapEx transformation into an “AI optical foundry.” Six strategic partnerships in 12 months cover the full stack — design, light sources, switching, modulators, LiDAR, and end-customer validation.

LWLG: The Technical Moat of EO Polymers

What is Perkinamine®, and why should you care?

Lightwave Logic is, in one sentence, a “materials company for optical modulators.” Its core product is Perkinamine®, a proprietary electro-optic (EO) polymer.

An optical modulator converts electrical signals to light signals — an essential component for any data transmission over fiber optics in datacenters. The modulator’s performance directly determines transmission speed and power consumption.

Here’s how Perkinamine® stacks up against the mainstream alternatives:

• Niobium and indium are not rare-earth elements per IUPAC definition (they are transition/post-transition metals), but both are classified as critical minerals with high China supply chain dependency. LWLG uses “rare-earth-free” in its PR [12], though “critical-mineral-independent” is more scientifically precise.

As the table shows, LWLG’s real competitor is not bulk LiNbO₃ but TFLN. TFLN matches or exceeds EO polymer bandwidth (145GHz for intensity modulators) and achieves a Vπ of ~1.4V. EO polymer’s differentiation comes down to two things: sub-1V drive voltage (even lower than TFLN) and native BEOL compatibility — the ability to spin-on directly in existing SiPho fabs without separate chiplet bonding steps.

Three key points here.

First, sub-1V drive voltage. Conventional silicon modulators need 3–5V; Perkinamine® operates below 1V [11]. This matters because power consumption scales with the square of voltage. In AI datacenters, power is money.

Second, BEOL (Back-End-of-Line) compatibility. Perkinamine® can be “spun on” during the standard CMOS back-end process [11]. No new equipment, no separate fab. For a foundry, this is enormously attractive — just add a process step to your existing line.

Third, no critical mineral dependency. LWLG markets Perkinamine® as “rare-earth-free” [12]. Strictly speaking, the competing materials’ niobium (LiNbO₃) and indium (InP) are not rare earths but critical minerals — yet both carry significant China supply chain exposure. Perkinamine®’s organic polymer structure avoids these dependencies entirely, providing a geopolitical risk hedge.

Commercialization Progress

LWLG tracks its commercialization through a publicly disclosed “Design Win Cycle.” Currently, four Fortune Global 500 companies are in Stage 3 (prototype to final product) [13].

Key milestones:

• Nov 4, 2025: First Fortune 500 company enters Stage 3. Additional unnamed foundry secured [14]

• Nov 25, 2025: Second Fortune 500 company begins technical program for 400Gb/s CPO with custom Perkinamine® [15]

• Jan 12, 2026: Dr. Aref Chowdhury appointed CTO (Nokia Network Infrastructure ($10B revenue) VP Strategy & CTO, previously Nokia Optics CTO) [16]

• Jan 15, 2026: MOU with QPICs for EO polymer PDK for quantum processors [17]

• Feb 24, 2026: Fourth Fortune 500 company enters Stage 3, targeting 200Gb/s and 400Gb/s [13]

• Mar 11, 2026: Tower Semiconductor development agreement for PH18 PDK integration [1]

Here’s where the puzzle clicks. In November 2025, LWLG announced it was adding an “unnamed silicon photonics foundry” beyond its existing AMF collaboration [14]. Today, Tower Semiconductor was formally revealed as a partner [1]. The timeline, context, and technical specs all align — the “unnamed foundry” was almost certainly Tower.

Financial Snapshot

LWLG is still pre-revenue. After completing a $35 million public offering in December 2025, the company holds approximately $70 million in cash [18]. Per the most recent SEC filing (Q3 2025 10-Q), average monthly expenditures are approximately $2.2 million [24] — implying a runway of roughly 2.5–3 years. (Earlier 10-K filings cited $1.7–1.8M/month; the increase reflects rising spend as commercialization efforts accelerate.)

Market cap sits around $630 million [1]. That’s a meaningful premium for a pre-revenue materials company, which tells you the market is pricing in significant commercialization expectations.

Key Takeaway: Perkinamine® has three technical moats: sub-1V drive, BEOL compatibility, and critical-mineral independence. Four Fortune 500 companies are in Stage 3, and the $70M cash position provides ~2.5–3 years of runway.

TSEM × LWLG Agreement — The Core Is PDK Registration

Let me boil today’s announcement down to one sentence: LWLG’s EO polymer modulator just got added to Tower’s PH18 silicon photonics “menu.”

A PDK (Process Design Kit) is essentially a foundry’s catalog of available building blocks. LWLG’s modulators going into the PH18 PDK means that every Tower SiPho customer can now drop EO polymer modulators into their designs without separate material qualification or process development [1]. The adoption barrier lowers significantly. The target specs: 110GHz+ bandwidth, 400G per lane — two to three generations ahead of current commercial silicon modulators (40–50GHz) [1].

What makes this more than a typical MOU, how it fits in the competitive landscape, and what it means for investors is covered below.

TSEM × LWLG Agreement Breakdown — Why This Matters

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Every time AI semiconductors come up, it’s always the same three names: Nvidia, AMD, Broadcom. Important companies, sure. But I think the real money is increasingly moving elsewhere.

On March 5, 2026, Marvell Technology (MRVL) released its FY2026 Q4 results, and it only reinforced my conviction: the real bottleneck in AI infrastructure is no longer the GPU — it’s the pipeline that moves the data. And at the heart of that pipeline is optics.

This isn’t just a quarterly earnings surprise. I see it as a landmark that stamped the arrival of the second wave of the AI hardware supercycle onto global capital markets.

Today I’m anchoring on Marvell’s earnings to take apart the entire optical interconnect value chain — from deep tech analysis to competitive dynamics, TAM estimates, geopolitical risks, and investment strategy.

1. The Numbers

Marvell Q4 revenue: $2.219 billion (+22% YoY, all-time record) Full-year revenue: $8.195 billion (+42% YoY) Excluding the divested automotive Ethernet business, organic growth was +45% Data center segment: 74% of total revenue, $1.65 billion in Q4 — an all-time high

So far, so good. But the really striking number is this:

Custom silicon revenue surged from $0 just a few years ago to $1.5 billion in FY2026. Volume production started in FY2025, and revenue doubled year-over-year in FY2026.

What this means is that Marvell is no longer just a merchant chip vendor — it’s been elevated to a strategic co-design partner for hyperscaler core compute architectures like AWS’s Trainium2 and Google’s Axion CPU. From $0 to $1.5B in just 2–3 years. Let that sink in.

And management’s guidance is aggressive:

• FY2027: Revenue approaching $11 billion (+30%+ YoY)

• FY2028: Revenue $15 billion, Non-GAAP EPS $5+ (longer-term target from prior investor communications)

This $11B number has been revised upward repeatedly. At a JPMorgan investor call in September 2025 it was ~$9.5B, then raised to ~$10B at the December earnings call, and now bumped up another ~$1B. Management attributes this to continued upward revisions in cloud CapEx forecasts and accelerating bookings. And this outlook doesn’t include any revenue contribution from the recently acquired Celestial AI or XConn. This is purely organic growth.

Let me walk through why this isn’t just talk. But first, one critical framing — where exactly is ‘optics’ in these earnings?

① The violent upward revision of interconnect (= optics) guidance:
30% → 50%+: This was the single most emphasized point in the earnings call. CEO Matt Murphy stated: “We expect our interconnect business to grow more than 50% year over year, well above our prior expectation of 30% growth.” The vast majority of Marvell’s interconnect revenue comes from pure optical products: 800G/1.6T PAM4 optical DSPs (Ara), coherent DSPs (Electra), and COLORZ 1600 DCI modules. When the company’s overall guidance is +30% but the optical segment alone is +50%+, that’s financial proof that optics is hard-carrying the entire company’s results. This interconnect growth revision is the primary engine that lifted the overall FY2027 forecast from $10B to $11B.

② 1.6T optical DSP ‘Ara’ enters volume production ramp:
Management stated that “1.6T solutions entered production in the second half of fiscal 2026” and that they “expect 1.6T revenue to ramp very rapidly in fiscal 2027.” Q4 data center revenue of $1.65B (all-time record) was explicitly attributed to “sequential growth across optical interconnects, custom silicon, switching, and storage.” The 1.6T generational shift that the market has been waiting for has officially started hitting the P&L — and it explodes in FY2027.

③ Custom silicon explosion = leading indicator of optical demand explosion (Attach Rate):
Custom silicon revenue surging from $0 to $1.5B means hyperscalers are deploying their own AI chips (AWS Trainium, Google Axion, etc.) at a furious pace. But scaling these hundreds of thousands of compute chips into massive clusters runs into clear physical limits with copper alone. Every custom chip deployed forces the attachment of high-speed optical transceiver modules to handle external high-speed data transmission. The custom silicon revenue explosion is a perfect leading indicator of the optical pipeline demand explosion that follows. Management guided custom business to “at least double year-over-year” in FY2028, meaning optical interconnect attach demand scales proportionally.

In short, Marvell’s earnings aren’t just a “semiconductor company did well” story. They’re a financial confirmation that optical interconnects have become the dominant growth engine of the AI data center. And the fact that design wins — the number of customer commitments to use Marvell’s chips in their next-generation products — hit an all-time record means the fuel for this engine will keep flowing for years.

2026: The Inference Inflection

Let’s set the big picture first. Entering 2026, over 55% of hyperscaler AI-optimized infrastructure spending has shifted from foundation model training to real-time inference — an inflection point.

GPU performance has been scaling exponentially, beyond Moore’s Law. But the problem is that the data movement pipeline — the network interconnect — hasn’t kept pace with that compute power. The result: inside massively capitalized AI factories, a significant portion of GPUs sit idle due to inefficient job scheduling and data wait times. Industry reports suggest that GPU utilization in large-scale clusters commonly stays in the 60–70% range.

When H100 GPU clusters sit idle while consuming power, 700W chips eat electricity doing nothing — driving up carbon emissions and OPEX. This isn’t just inefficiency; it’s a structural problem eating into the ROI of multi-billion-dollar investments.

For CTOs operating AI infrastructure, the ultimate KPI isn’t GPU clock speed. It’s Job Completion Time (JCT). If you can’t reduce JCT, billions of dollars in cluster investment go to waste. That’s why hyperscalers are racing to deploy 1.6T (Terabit-per-second) optical networking infrastructure across intra-rack, rack-to-rack, and inter-datacenter links.

Marvell’s earnings are the clearest evidence yet that capital is rotating en masse toward companies that control the blood vessels connecting Nvidia’s compute.

Key takeaway: The primary constraint on AI infrastructure has shifted from compute to connectivity. The 1.6T optical interconnect market is exploding as operators race to minimize JCT, and Marvell’s FY2028 $15B guidance is the opening salvo of this structural supercycle.

2. Deep Tech: The Limits of Copper and the Inevitability of Optics

2.1 The Copper Wall

As AI clusters have expanded from 10,000 GPUs to 100,000 and now toward 1 million, the copper-based interconnect technologies that once formed the backbone of data center networking have hit a physics wall — the Copper Wall.

Traditionally, short-reach server-to-switch links used passive copper twinax cables (DACs). Cheap, reliable, no issues. But as bandwidth doubles from 400G to 800G to 1.6T, serious problems emerge:

• Skin Effect: At high frequencies, current concentrates on the conductor’s surface, spiking resistance

• Insertion Loss: At 200Gbps per lane (200G/lane), passive copper cable reach drops to 2–3 meters — barely enough for intra-rack top-to-bottom connections

“Just use thicker cables?” In a 1.6T high-density switch environment, hundreds of fat cables completely block rack airflow. Thermal collapse. Cooling fails.

Active Electrical Cables (AECs) with retimer chips can extend reach to 5–7 meters, but their power draw exceeds per-rack power constraints when thousands of links are deployed.

The bottom line: in scale-out architectures where 100,000+ GPUs are distributed across tens of meters and must constantly exchange massive data for All-reduce synchronization, optical interconnects are the only solution that simultaneously overcomes bandwidth, reach, and power density limits.

Fiber-optic links can transmit data loss-free across tens of meters to kilometers. Legacy optical modules had their own issues — high power consumption in E/O conversion and failure rates up to 100x that of copper — but solving these problems is exactly what’s driving innovation across the entire value chain. And Marvell sits at the center.

2.2 PAM4 DSP: The Brain of Optical Communications

The critical brain that overcomes these physical limits and ensures optical signal integrity is the Digital Signal Processor (DSP).

In high-speed optical communications, data is encoded not as simple 0s and 1s (NRZ) but using PAM4 (Pulse Amplitude Modulation 4-level) — transmitting 2 bits per symbol across 4 amplitude levels. This naturally introduces signal distortion, chromatic dispersion, and noise. Correcting these mathematically and performing Forward Error Correction (FEC) is the DSP’s core job.

Marvell is the undisputed leader in PAM4 DSP.

Key points from the earnings release:

• Robust hyperscaler demand for 800G PAM4 DSPs continues

• Next-gen 1.6T solutions entered volume production in Q4

• Marvell’s 1.6T optical DSP ‘Ara’: industry-first 3nm process, 200G/lane interfaces

• 20%+ power reduction per bit vs. prior 5nm-based 800G generation (per Marvell’s official announcement)

Power efficiency matters enormously because optical modules are consuming an ever-larger share of total data center power budgets. Power per bit has become the most critical engineering metric. Marvell’s 3nm Ara platform, with its advanced node and optimized FEC algorithms, has mitigated pluggable optics’ biggest weakness — power consumption — and successfully ushered in the 1.6T era.

LightCounting analyst Bob Wheeler projects PAM4 DSP unit shipments will more than triple from 2024 to 2029, reaching approximately 127 million units annually, stating they will “remain the primary optical technology for connecting assets inside data centers for the foreseeable future”.

Beyond 2H 2026, the next speed transition to 3.2T is on the horizon via 200G/lane → 400G/lane evolution. Ara currently supports 200G/lane, and industry roadmaps (Ethernet Technology Consortium, IEEE 802.3 standardization) suggest 400G/lane-based 3.2T modules will begin sampling in 2027–2028.

2.3 Form Factor Evolution: Pluggable → CPO → Optical I/O

This is personally the most fascinating part. As bandwidth surges past 1.6T toward 3.2T and 6.4T, the physical form of optical communications is undergoing a fundamental architectural shift.

💡 [Form Factor Evolution]Pluggable (OSFP/QSFP-DD) → LPO (DSP removed) → CPO (ASIC + optics on same substrate) → Optical I/O (intra-chip photonics) Power efficiency: ~15 pJ/bit → ~10 pJ/bit → ~5-7 pJ/bit → ~few pJ/bit Reach: hundreds of meters–2km → hundreds of meters → meters–tens of meters → chip-to-chip direct

Pluggable Optics — Today’s data center workhorse. OSFP or QSFP-DD modules plug into switch front panels for easy serviceability. But the long electrical trace from switch ASIC to front-panel module wastes significant power compensating for signal attenuation.

LPO (Linear-drive Pluggable Optics) — A transitional approach that removes the power-hungry DSP chip inside the module, using only analog linear drivers. Gets power down to ~10 pJ/bit but sacrifices signal correction capability, making system-wide BER control difficult.

CPO (Co-Packaged Optics) — The game changer. Places the optical engine (silicon photonics) and switch ASIC on the same package substrate, shortening copper traces to millimeters. This eliminates signal loss at the source, dramatically improving efficiency to ~5–7 pJ/bit (Broadcom’s benchmark). Initial concerns about thermal management and external laser sourcing are being resolved as CPO becomes essential for high-end AI systems.

Optical I/O / Photonic Fabric — The ultimate evolution. Beyond switches, this stage performs GPU-to-memory (HBM) communication using light. This is the core technology domain of Celestial AI, which Marvell acquired. By bringing optical communication down to the transistor level inside silicon, it breaks through the Memory Wall.

Why does this matter? Industry estimates suggest Nvidia’s NVLink consumes roughly 62.5 pJ/bit, while Celestial AI’s Photonic Fabric operates at just a few pJ/bit with ultra-low latency — a potential efficiency improvement of several times to 10x. Celestial AI’s thermal stability is a key differentiator, enabling reliable operation in extreme heat environments created by multi-kilowatt XPUs, allowing vertical 3D packaging directly on top of XPUs rather than edge connections — freeing up precious die-edge real estate for more HBM.

2.4 Marvell’s Architecture Strategy: Scale-Out, Scale-Across, Scale-Up

Marvell’s recent M&A and product roadmap reveal a clear strategic intent to evolve beyond a component supplier into an end-to-end architect controlling all data flows inside AI data centers.

Scale-out — Rack-to-rack traffic. Marvell deploys its Ara 1.6T PAM4 DSP and Ethernet switch IP here. The earnings call revealed interconnect business expected to grow 50%+ YoY in FY2027, sharply above the prior 30% guidance.

Scale-across — Data center-to-data center. Power and space constraints prevent housing hundreds of thousands of GPUs in a single building, creating explosive demand for connecting geographically distributed data centers as a single virtual cluster. Marvell targets this DCI market with its industry-first 2nm 1.6T ZR/ZR+ coherent DSP ‘Electra’ and ‘COLORZ 1600’ module, featuring hardware MACsec encryption integrated on-chip for secure campus-to-campus transmission.

Scale-up: Chip-to-chip direct communication. This is the highlight. Marvell acquired Celestial AI ($3.25B) for its optical ‘Photonic Fabric’ technology.

But here’s what’s even more interesting: XConn Technologies ($540M). If optics is the future, why did Marvell buy a copper-based PCIe/CXL switch company? It’s not just about chips. It’s about seizing switching dominance over UALink (Ultra Accelerator Link) — the open standard that the anti-Nvidia coalition is building to counter Nvidia’s proprietary NVLink ecosystem.

Short-range (intra-rack) gets bound by XConn’s UALink copper switches; long-range (rack-to-rack, chip-to-chip) gets connected by Celestial AI’s optics. A complete anti-Nvidia ‘hybrid interconnect empire.’ As TechArena put it, “they didn’t buy a science experiment; they bought the plumbing for GPT-6”.

• Celestial AI acquisition: $3.25B (up to $5.5B with revenue milestones). AWS VP David Brown commented that this will “help further accelerate optical scale-up innovation for next-generation AI deployments”. Acquisition closed February 2, 2026.

• XConn Technologies acquisition: $540M. PCIe Gen 6 and CXL 3.1 switching for near-range memory pooling. Already engaged with 20+ customers; PCIe 5 / CXL 2.0 switches in production, PCIe 6 / CXL 3.1 sampling. Revenue contribution starts FY2027 Q3, targeting $100M in FY2028.

Key takeaway: As copper hits its physical wall, data centers are being forced through an architecture transition: 1.6T pluggable → CPO → optical I/O. Marvell’s acquisitions of Celestial AI ($3.25B) and XConn ($540M) extend its reach from scale-out (rack-to-rack) into scale-up (chip-to-chip), completing full-stack dominance of the AI data center interconnect market.

3. Global Optical Value Chain Mapping & Competitive Analysis

The optical interconnect ecosystem is fragmented into highly specialized layers. As the industry enters the 1.6T commercialization era, fierce technology and market share battles are underway at every tier.

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Welcome back. This is PhotonCap.

In Lecture 3, we laid down the roads for light inside the chip (waveguides), installed traffic lights at intersections to split and combine beams (splitters, couplers), and placed roundabouts that filter specific colors of light (ring resonators). The on-chip traffic infrastructure is in place.

But one thing is missing — the highway on-ramp. No matter how well the roads inside the chip are built, they’re useless if light from the outside world (optical fiber) can’t get in. The problem? The highway is 1,000 times wider than the city’s alleyways.

Lecture 4 tackles this “last millimeter” challenge, covering six coupling technologies — including those already adopted by industry and others still emerging from research.

1. Introduction: Why ‘Packaging’ Is the Biggest Bottleneck in Silicon Photonics

Modern data communication and high-performance computing architectures face unprecedented demands for bandwidth expansion, driven by the explosive growth of AI, cloud, and ultra-high-resolution streaming. Traditional copper (Cu)-based electronic packaging causes significant power loss and signal integrity degradation at centimeter-scale board-level transmission, serving as a physical limit on switch package bandwidth scaling. According to SemiAnalysis, optical transceivers alone consume approximately 17 MW in a 200,000-GPU-scale GB300 NVL72 cluster. CEO Jensen Huang also emphasized at GTC 2025 that scaling to one million GPUs would require 6 million transceivers consuming tens to hundreds of megawatts, underscoring the necessity of Co-Packaged Optics (CPO) [1].

Silicon photonics-based Photonic Integrated Circuits (PICs) have emerged as a key alternative to overcome this electronic bottleneck. Although manufacturing technology capable of integrating 10³–10⁵ optical devices on a single die has already matured, the photonics industry faces another severe bottleneck: Packaging, Assembly, and Test [2][3].

For electronic ICs, packaging accounts for roughly 20% of total manufacturing cost, whereas for silicon-based PICs this figure reaches 70–80%—a strikingly disproportionate structure [2][3][4]. Specifically, while cutting-edge 5 nm electronic SoCs cost approximately $0.57/mm² before packaging, silicon photonic chips cost only $0.1–0.4/mm² for the die itself [2]. Yet the final module cost escalates dramatically due to the physical difficulty of optical alignment and resulting assembly throughput limitations. While electronic packaging has evolved to large-scale passive alignment processes using solder bumps and hybrid bonding, photonic packaging still heavily relies on active alignment—directly injecting light to find the optimal coupling position [3][4].

This article (Part 1 of 2) analyzes the physical principles and structural limitations of optical I/O coupling technologies connecting chip interiors and exteriors, and compares the design metrics and trade-offs of major couplers (Edge, Grating, Evanescent, Free-form, Cantilever, Photonic Wirebond). Part 2 covers 3D Photonic Vias technology, CPO, quantum photonics, LiDAR, and other next-generation system applications

Why Optical Coupling Is the Bottleneck in System Evolution

The figure below illustrates how the position and requirements of the fiber-chip coupling interface change as datacenter switch architecture evolves from Pluggable Optics to 3D CPO [13].

The key point at each stage is where the fiber couples to the package. In the Pluggable approach, approximately 25 cm (~10 inches) of long electrical traces span across the PCB between the ASIC and transceiver (OE), with fibers coupling at the board edge using off-the-shelf connectors with relaxed tolerances (±10 µm). In 2.5D CPO, the optical engine sits on the same package substrate as the ASIC, reducing the electrical path to ~5 mm, with fibers coupling directly to the PIC at the package edge. In the final stage—3D CPO—the PIC is stacked directly above the ASIC on an interposer with electrical paths under 50 µm, making the fiber-to-chip coupling interface the single most critical point determining package performance and cost.

In other words, as integration tightens, the requirements for fiber-to-chip (F2C) coupling technology fundamentally change. In the Pluggable era, 2–3 dB of coupling loss was acceptable with generous connector tolerances, but in 3D CPO, thousands of channels must be coupled simultaneously at sub-dB loss with passive alignment.

The photo above shows the internals of the TX9190, a 51.2 Tbps liquid-cooled CPO switch jointly unveiled by Marvell and Jabil at OCP Summit 2025. Surrounding the ASIC are numerous optical engines connected by hundreds of fiber strands. Each optical engine contains a fiber-to-chip (F2C) coupling interface where the PIC waveguide meets the optical fiber.

One example of an F2C approach is the edge coupler. (The specific F2C method used in the TX9190 CPO switch will be covered in Part 2.) As CPO architectures evolve, the number of optical engines per package and channel density both increase, which inevitably drives up the number of these F2C assemblies. This is the fundamental reason why optical packaging technology is becoming exponentially more important. The coupling techniques covered in Part 1 (edge, grating, evanescent, free-form, and PWB) each address different stages and interface requirements along this roadmap. Understanding the insertion loss, alignment tolerance, and bandwidth tradeoffs of each is the starting point for CPO system design.

2. Physical Principles of Optical Coupling: The 1,000× Mode Mismatch

Coupling efficiency is the ratio of optical power transferred between two different optical waveguides, fundamentally determined by the spatial overlap of Mode-Field Diameter (MFD) and reflectance due to refractive index mismatch [2][5].

At the telecommunications wavelength (1550 nm), standard single-mode fiber (SMF-28) has a core diameter of approximately 8.2 µm and MFD of approximately 10.4 µm [6]. In contrast, a silicon waveguide (refractive index ~3.45) embedded in silica cladding (~1.45) operating in single-mode condition has a cross-section of approximately 400 nm × 220 nm, confining the optical mode to approximately 0.1 µm² [5]. The cross-sectional area difference between these two media is approximately 1,000×—the most fundamental physical barrier to high-efficiency optical coupling.

💡 [Analogy: Connecting a fire hose to a nano-straw]

Imagine feeding the water stream from a 10 cm diameter fire hose (optical fiber) into a 0.5 cm straw (chip waveguide) without spilling a drop. The cross-sectional area differs by approximately 1,000×, requiring specialized structures to physically transform the spatial shape (mode) of light.

Given the electric field distribution of the input waveguide E₁(r, φ) and the output waveguide E₂,ₖ(r, φ), the coupling efficiency ηₖ into the k-th guided mode is derived from the overlap integral [5]:

This expression shows that mode size mismatch (w₁/w₂) and lateral, longitudinal, and vertical alignment errors exponentially degrade coupling efficiency. Numerical analysis indicates that mode size mismatch has a more dominant effect on coupling loss than alignment error [5].

Additionally, the difference in effective refractive index (n_eff) between the two media causes Fresnel reflection at the interface. The transmission coefficient is t₂ = 2(n_eff,1 · n_eff,2)⁰·⁵ / (n_eff,1 + n_eff,2), so the total coupling efficiency is |t₂|² · ηₖ. Here |t₂|² = 4n₁n₂/(n₁+n₂)² is the power transmittance (T) at the interface, following the notation of [5]. Therefore, the design goal of all optical couplers is to maximize ηₖ through gradual geometric deformation that expands/contracts the MFD, and to control refractive index to bring |t₂|² close to 1 [2][5].

3. Edge Coupling: Intuitive but Demanding

3.1. Inverse Tapers and Spot-Size Converters (SSC)

Edge coupling (end-fire or butt coupling) is the most intuitive approach, directly facing the physical cross-sections of waveguides to transfer optical signals. A spot-size converter (SSC) is essential to resolve the mode mismatch on the high-index silicon photonics platform [5][7].

The most intuitive approach is 3D tapering of the silicon waveguide in both horizontal and vertical directions to directly expand the PIC mode to fiber mode size. However, this is not widely adopted in production lines due to the process complexity requiring multi-step etching or grayscale lithography in the vertical direction. Instead, the most widely used structure is the inverse taper, which gradually narrows the silicon waveguide width to tens to hundreds of nanometers (e.g., 100–200 nm) toward the chip edge. As the waveguide core narrows, the optical mode confinement weakens and the electromagnetic field expands in the form of an evanescent field, reducing the effective refractive index. Wrapping this with low- or medium-index 2D/3D overlay waveguides made of polymer, SiO₂, SiON, or Si₃N₄ ultimately forms an MFD of 3–10 µm diameter, enabling efficient coupling with lensed fiber, UHNA (Ultra-High Numerical Aperture), or standard SMF-28 fiber [5][7].

💡 [Analogy: Mist spreading from a needle tip]

In the wave world of light, when a silicon waveguide tip is shaved below 100 nm, the light can no longer be confined in the narrow silicon and spreads outward into the surrounding material (polymer or SiO₂). This intentional “pushing” of light outward enlarges its size to match the fiber MFD—the essence of the inverse taper.

Representative results: A 470 nm × 270 nm SOI waveguide parabolically tapered to 100 nm over 40 µm yields -3.3 dB (TM) and -6.0 dB (TE) [7]. A polymer-based 3 µm × 3 µm SSC combined with a 200 µm inverse taper (60 nm tip) achieves -0.8 dB (83.2% efficiency, TE) with PDL below 0.5 dB [7]. Further optimization has demonstrated improvements to -0.5 dB [2]. SiON enables graded-index design by tuning N₂/O₂ gas ratios to transition refractive index from Si₃N₄ (2.0) to SiO₂ (1.5), directly matching 10 µm-class SMF-28 fiber [5].

3.2. Advanced Edge Coupling Architectures: Multi-tip and Metamaterial Couplers

Various structural variants have been studied to maximize edge coupling efficiency and secure lithographic process margins.

Trident structure: Instead of a single inverse taper, multiple auxiliary tapers are placed around the main waveguide. Hatori et al. demonstrated a 150 µm trident coupler on a 220 nm SOI platform, achieving polarization-insensitive high efficiency of -0.92 dB (80.9%, TE) and -0.94 dB (TM) [7].

Subwavelength Grating (SWG) couplers: A metamaterial approach that artificially tunes the effective refractive index by patterning sub-wavelength features directly in the silicon waveguide [7][8]. Benedikovic, Cheben et al. developed a multi-level SWG coupler combining partial and full etch regions, experimentally achieving -0.69 dB (85.3%) with 60 nm 3-dB bandwidth when combined with a metal reflector [8]. Simulation-based L-shaped SWG designs report -0.25 dB (~95%) [9], though this requires experimental validation.

https://doi.org/10.1364/OE.23.022553

Vertical edge coupler (Elephant coupler): To overcome the constraint of die edge dicing, silicon waveguide cantilevers are bent 90° upward using ion implantation (80 keV) or thermal annealing stress, enabling vertical end-fire coupling. A -2.2 dB (TE) coupling efficiency has been confirmed with lensed fiber at a 3 µm bend radius [2][7].

Table 1. Performance comparison of major edge coupling methods (Data: [2][5][7][8])

3.3. Packaging Limitations of Edge Coupling

Despite high efficiency and broadband performance, edge coupling has three key weaknesses in high-density system-level packaging. First, I/O ports can only be placed at the chip edge, creating a “Shoreline Bottleneck” that limits channel scaling. Second, dicing and polishing post-processes are mandatory to expose the coupler facet, fundamentally blocking wafer-scale inline testing. Third, the alignment tolerance is typically ±1–2 µm, requiring active alignment and directly reducing production throughput [2][5][7].

Industry efforts to circumvent these limitations are noteworthy. Peter Winzer, CTO of Nubis Communications, presented at OCP Global Summit 2025 an optical engine architecture combining 2D optical fiber arrays with surface grating coupling to implement large-scale optical I/O from the chip top surface instead of edge coupling [14]. This approach fundamentally resolves the shoreline bottleneck, coupling 36+ channels via a 2D fiber array in a single engine to meet CPO’s high-throughput demands. However, as discussed in Section 4, grating coupler bandwidth limitations and polarization dependence remain challenges.

4. Grating Couplers: Bending Light at the Surface

Grating Couplers (GC) are the most practical alternative circumventing the spatial and process constraints of edge coupling. By etching sub-wavelength periodic patterns in the device layer, light is diffracted out-of-plane, allowing placement anywhere on the chip with high layout flexibility and enabling wafer-scale parallel optical testing without dicing [5][7].

💡 [Analogy: A sunroof installed on the chip surface]

Rather than sending light out the chip’s edge (like an exit door), a grating coupler acts like a sunroof—sending light upward through the chip surface via periodic corrugations. Adding a bottom reflector beneath the waveguide dramatically improves coupling efficiency by redirecting downward-leaked light back up.

4.1. Operating Principle and Directionality Improvement

GC operation is governed by the Bragg condition. The relationship between the propagation constant β = 2πn_eff/λ₀ and the surface-parallel component of the diffracted wave k_m,z is k_m,z = β − mK (where K = 2π/Λ, m is the diffraction order) [5].

Designing for perfectly vertical emission (θ = 0°) causes the second-order diffracted wave to become a back-reflection toward the input waveguide, inducing parasitic Fabry-Perot oscillation. Therefore, off-normal emission angles of 8°–15° are typically used to collect only the first-order diffracted light and minimize back-reflection [5][7].

Shallow-etched (e.g., 70 nm depth) uniform grating couplers lose approximately 35–45% of incident optical power toward the substrate, making directionality a critical issue [7]. Key approaches to address this include:

Bottom Reflector introduction: Inserting Au, Al thin film, or Si/SiO₂ distributed Bragg reflector (DBR) below the BOX layer to redirect downward-diffracted light upward. When BOX thickness matches constructive interference conditions, directionality exceeds 90%, and combined with an apodized grating, -0.62 dB (~87%) coupling efficiency has been reported [7].

Poly-Si Overlay: A CMOS-compatible process that grows polycrystalline silicon on the grating to break vertical refractive index symmetry. A 150 nm overlay on 220 nm etch achieves 85% directionality at -1.08 dB. A single-crystal silicon nanomembrane (Si-nmb) overlay variant reports -1.6 dB loss with 44 nm 1-dB bandwidth [7].

Dual-level Etch and Slanted Gratings: Alternating shallow (70 nm) and full (220 nm) etches in one period, or using focused ion beam (FIB) to create 50–60° angled etches for a blazed effect. The dual-etch structure reports -1.3 dB loss with 52 nm 3-dB bandwidth [7].

4.2. Apodization for Mode Matching

Even with improved directionality, mismatch between the fiber’s Gaussian beam profile and the grating emission profile causes mode matching loss. A uniform coupling strength (α) grating emits light in an exponential decay pattern (P(z) = P₀e⁻²αz), limiting overlap integral with the Gaussian mode to ~75% [7].

Linear chirp (FF = FF₀ − R·z) that gradually varies fill factor along propagation direction z corrects this. An apodized GC on a 260 nm SOI platform experimentally demonstrated -0.9 dB coupling efficiency [7].

4.3. 2D Polarization Diversity Grating Couplers

1D GCs exhibit extreme polarization dependence due to large effective index differences between TE and TM. To accommodate arbitrarily varying polarization states in telecom networks, 2D grating couplers that physically superimpose orthogonal 1D GCs are required. An optimized 2D-GC with aluminum reflector records -0.95 dB insertion loss and ~0.3 dB PDL at 1550 nm, serving as a key component in production-grade receiver modules [7].

Table 2. Performance comparison of major grating coupling methods (Data: [5][7])

GC assembly tolerance of ±2.0–3.0 µm is wider than edge couplers, suitable for high-speed pick-and-place equipment. However, the 1-dB bandwidth of 30–50 nm is narrower than edge coupling (>100 nm), requiring additional bandwidth expansion such as Si₃N₄ dual-level couplers for broadband WDM or multi-band (O-band and C-band) applications [5][7].

5. Adiabatic and Evanescent Coupling

5.1. Operating Principle

Adiabatic coupling is a technique where optical power gradually transitions between two waveguides via evanescent fields. While edge coupling completes coupling at the chip facet in one step, adiabatic coupling spreads mode transition across tens to hundreds of µm interaction regions. The beat length between two waveguides is defined as L_b = λ₀ / (n_eff,1 − n_eff,2), and the actual coupling region must be several to 10× this beat length to satisfy the adiabatic condition [2].

💡 [Analogy: Transferring cargo between two trains running side by side]

Instead of cutting and splicing rails, two trains (waveguides on different chips) run side by side in close proximity. As one gradually narrows and the other widens, the cargo (optical energy) naturally transfers from the narrowing to the widening train. This is the principle enabling inter-layer optical transfer without facet cutting.

This characteristic is useful not only for fiber-to-PIC coupling, but is particularly powerful in heterogeneous chip-to-chip 3D hybrid stacking. For example, when waveguides from a III-V compound semiconductor laser chip (top) and a silicon photonic chip (bottom) face each other across a tens-to-hundreds-nm DVS-BCB bonding layer, designing a “cross inverse taper” structure where both waveguide widths change inversely enables mode transition across the refractive index barrier [2].

5.2. HIC vs. LIC: Trade-offs by Refractive Index Contrast

Evanescent coupler packaging assembly tolerance is strongly influenced by waveguide refractive index contrast (Δn) [2].

High Index Contrast (HIC) systems (e.g., Si-Si): Δn of 0.5–2 requires adiabatic lengths exceeding 500 µm with multi-segment tapers for ±3 µm assembly tolerance. Coupling efficiency is sensitive to vertical gap errors and adhesive refractive index variations.

Low Index Contrast (LIC) systems (e.g., polymer/glass-Si): Ion-exchanged (IOX) waveguides or flexible polymer ribbons have very low Δn < 0.006. The adiabatic length increases to 1.5–2 mm for ±3 µm tolerance, but sensitivity to refractive index errors or thermal media changes is approximately 15× lower than HIC, providing significant packaging stability advantages [2].

Evanescent coupling theoretically achieves near-zero reflected power, insertion loss below 0.5 dB, and coupling bandwidth exceeding 100 nm. The most notable advantage is the ability to narrow pitch to 10 µm, securing density above 100 connections/mm. This exceeds the physical limit of conventional fiber arrays (8 connections/mm max) by more than 10×, attracting attention as a key technology for ultra-high-density CPO architectures [2].

6. Free-form and Mechanical Cantilever Couplers

6.1. Micro-lens/Mirror-based Free-form Coupling

Free-form couplers use two-photon polymerization (TPP), grayscale lithography, or nanoimprint lithography (NIL) to precision-print 45° total internal reflection (TIR) mirrors or collimating micro-curved lenses on the chip surface [2][10].

Light traveling horizontally in the waveguide hits the 45° mirror, deflects vertically (Z-axis), and expands its beam size (MFD) through the lens structure. By intentionally enlarging the beam diameter, the lateral assembly tolerance widens from ±2 µm to ±10–35 µm or more, and the Z-axis vertical separation also accommodates tens to hundreds of µm [2][10].

💡 [Analogy: Making the target 10× bigger]

Threading a hair through a needle eye (±1 µm tolerance) is slow and expensive. A free-form lens acts like a magnifying glass, expanding the beam diameter by 10× or more. Since the beam is wider, the target is larger, enabling stable coupling even with tens of µm chip misalignment—the key principle enabling optical assembly within the tolerance range of electrical bump equipment.

This optical relaxation accommodates solder bump (C4, Cu pillar) process tolerances in electronic packaging, making it the key mechanism for simultaneous electro-optical hybrid bonding (co-packaging). Free-form structures have low refractive index dispersion (±200 nm 1-dB bandwidth) and operate independently of TE/TM polarization [2][10]. Ranno et al. experimentally achieved 0.8 dB coupling loss and >180 nm 1-dB bandwidth between SMF-28 and a 220 nm SOI platform [10]. However, the serial nature of TPP fabrication requires transition to multi-beam exposure or NIL-based parallel replication for high-volume production.

6.2. Stress-Induced Mechanical Cantilever Coupling

An alternative approach physically bends the waveguide itself upward. Applying high-temperature (770°C) oxide stress to substrate-released silicon waveguides, or implanting silicon ions (Si⁺, 80 keV, dose 1.7 × 10¹⁶ cm⁻²) to create lattice defects, generates surface stress gradients that bend the cantilever waveguide 90° [2].

This method achieves edge coupling facets in the vertical direction with 3–5 µm bend radii, enabling fiber coupling at wafer scale without dicing. However, high ion implantation doses increase waveguide propagation loss (up to 40 dB/mm), and research on novel cladding materials and polymer SSC structures to mitigate this is ongoing [2].

7. Photonic Wirebonding (PWB): Nullifying Alignment Error

One of the most advanced packaging technologies is Photonic Wirebonding (PWB), inspired by electrical wirebonding [2][11]. If the packaging bottleneck lies in the process of aligning components to exact positions, PWB takes the reverse approach: place components approximately, then create the optical path afterward.

💡 [Analogy: Place the islands first, draw the bridge later]

Traditional packaging precisely aligns two islands (chips) to a pre-built bridge. PWB reverses this: place the two islands with generous tolerance, then use a 3D scanner to determine actual positions and a 3D printer (laser) to draw a custom bridge on the spot. Since the software compensates for any chip misalignment, the variable of positional alignment error itself is eliminated.

The process works as follows: two chips (e.g., laser chip and silicon photonic chip) are placed on the packaging substrate with ±50 µm mechanical tolerance. A high-resolution 3D machine vision system then scans each chip’s I/O waveguide facet coordinates at nanometer precision. The system calculates the optimal 3D spline waveguide trajectory connecting the two coordinates, and a femtosecond laser TPP 3D printer exposes a photocurable polymer resin along the trajectory to form a 3D polymer optical waveguide connecting the two chips [2][11].

The core value is the fundamental elimination of coupling loss due to alignment error. Recent research has demonstrated 0.7 dB insertion loss with ~0.8 Tbit/s data transmission [11], and 1.6 dB or less over a 1280–1580 nm ultra-broadband (>300 nm) range [2]. Variant techniques such as SCRIBE (mesoporous silicon scaffold-based) have also been developed to support flexible multi-mode and single-mode interconnection [12].

However, since the laser sequentially draws each path, throughput (tens of seconds per bond) is insufficient for high-volume production lines processing tens of thousands of I/Os. Research on multi-beam lenses and projection-based light-sheet exposure for electrical wire bonder-level speeds (<0.1 s/bond) is actively progressing [2].

Table 3. Performance comparison of evanescent, free-form, cantilever, and PWB coupling (Data: [2][10][11][12])

†PWB insertion loss note: 0.7 dB is per bond (Billah 2018 [11]); 1.6 dB is total for both interfaces in C-band (Lindenmann 2012 [11]). Broadband (1240–1580 nm) total for both interfaces is 2.5 ± 1.1 dB.

8. Summary, Conclusions, and Part 2 Preview

As explored in this article, the optical I/O challenge in silicon photonics fundamentally originates from the mode mismatch between 10.4 µm MFD optical fiber and ~0.1 µm² cross-section submicron waveguides. To bridge this 1,000× gap, diverse approaches have evolved: edge coupling (inverse taper, SWG), grating couplers (apodization, reflectors), evanescent coupling, free-form lenses, cantilevers, and photonic wirebonding.

Each technology presents different trade-offs across five axes—insertion loss, alignment tolerance, bandwidth, polarization dependence, and manufacturing scalability—and no single technology satisfies all requirements. Industry trends show a clear shift from active alignment at the chip periphery toward passive alignment-compatible structures that route through the chip surface or substrate interior. Grating couplers (§4) enable wafer-scale passive alignment anywhere on the chip surface; free-form couplers (§6) achieve wide ±10–35 µm tolerance through beam expansion; and photonic wirebonding (§7) renders alignment irrelevant through post-fabrication correction. Nubis (§3.3 [14]) circumventing the shoreline bottleneck with 2D optical arrays and surface grating coupling, and Marvell TX9190 (§1 [15]) placing dozens of optical engines around the ASIC, are both designs predicated on high-throughput mass assembly.

Conclusion: Channel Count Scaling Is the Next Battleground

In the author’s view, increasing channel count per package will be the most dominant technical direction as CPO evolves. As already evident in the Marvell TX9190, a single switch requires hundreds of F2C junctions, and this number will grow to thousands in next-generation 3D CPO. Insertion loss remains a critical metric, but ultimately what the system demands is simultaneously achieving low loss and high channel density.

Edge coupling can achieve the lowest loss below 0.5 dB, but faces fundamental limits in channel scaling due to the shoreline bottleneck. However, V-groove-based passively aligned fiber arrays can implement edge coupling without active alignment [16], representing meaningful progress in production throughput. Evanescent coupling can also achieve sub-0.5 dB loss, but the hundreds-of-µm-long coupling regions pose compatibility challenges with large-area packaging. While these technologies are clearly advancing in insertion loss, passive alignment compatibility, and other dimensions, the structural limitation of 1D shoreline constrains dramatic throughput scaling.

In contrast, grating couplers and free-form couplers can utilize the entire chip surface for 2D array placement, offering high degrees of freedom for channel scaling. Bringing these approaches’ loss down to sub-dB levels while securing manufacturing compatibility is one promising direction. Another compelling direction is the use of glass substrates (Glass Interposer/Substrate). Glass has a refractive index (~1.5) nearly identical to fiber cladding, fundamentally favoring fiber-to-PIC mode matching and enabling dramatic insertion loss reduction. Furthermore, glass substrates can be scaled to much larger areas than silicon dies, substantially alleviating the shoreline bottleneck. Ultimately, whoever first implements at production scale a method to increase channel count while reducing loss—whether through surface coupling loss improvement or glass substrate mode matching optimization—will determine the outcome of the CPO era.

Part 2 (subscriber-only) broadens the scope. We compare which F2C approaches Nvidia, Broadcom, Marvell, Nubis, and other major companies have actually chosen; dig into why glass substrates are beginning to be called “the second silicon” as previewed in Part 1; explore Photonic Vias where light penetrates substrates vertically; the assembly nightmare where curing epoxy destroys alignment; and beyond CPO switches—optically connected memory, neuromorphic chips that compute with light, quantum photonics handling single photons, thumbnail-sized LiDAR, and biosensors diagnosing from a single blood drop—the next-generation battlegrounds that silicon photonics packaging is opening up.

As of 3/8, the Part 2 draft is complete but topics are still being refined. If you have topics you’d like covered or questions, anyone is welcome to drop a comment — subscriber suggestions will be prioritized.

References

[1] NVIDIA, “NVIDIA Announces Spectrum-X Photonics, Co-Packaged Optics Networking Switches to Scale AI Factories to Millions of GPUs,” GTC 2025 Press Release (March 18, 2025).

https://nvidianews.nvidia.com

— SemiAnalysis, “Co-Packaged Optics (CPO) – Scaling with Light for the Next Wave of Interconnect” (2026).

SemiAnalysis

Co-Packaged Optics (CPO) Book – Scaling with Light for the Next Wave of Interconnect

Co-Packaged Optics (CPO) has long promised to transform datacenter connectivity, but it has taken a long time for the technology to come to market, with tangible deployment-ready products only arriving in 2025. In the meantime, pluggable transceivers have kept pace with networking requirements and remain the default path thanks to their relative cost-effectiveness, familiarity in deployment, and standards-based interoperability…

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3 months ago · 247 likes · 4 comments · Dylan Patel, Daniel Nishball, Myron Xie, Ivan Chiam, Clara Ee, and Patrick Zhou

[2] Weninger, D., Serna, S., Ranno, L., Kimerling, L., & Agarwal, A., “Advances in waveguide to waveguide couplers for 3D integrated photonic packaging,” Light: Science & Applications 15, 17 (2026). https://doi.org/10.1038/s41377-025-02048-w

[3] Ranno, L. et al., “Integrated Photonics Packaging: Challenges and Opportunities,” ACS Photonics 9(11), 3467–3485 (2022). https://doi.org/10.1021/acsphotonics.2c00891

[4] Optics & Photonics News, “AI Factories: Photonics at Scale” (November 2025); Semiconductor Engineering, “Silicon Photonics Manufacturing Ramps Up” (May 2024); CITC/vario-optics, “Advancing the semiconductorisation of photonic chip packaging,” PIC Magazine.

[5] Son, G. et al., “High-efficiency broadband light coupling between optical fibers and photonic integrated circuits,” Nanophotonics 7(12), 1845–1864 (2018). https://doi.org/10.1515/nanoph-2018-0075

[6] Corning, SMF-28 Ultra Optical Fiber Product Specification. MFD: 10.4 ± 0.5 µm at 1550 nm, Core diameter: 8.2 µm. https://www.corning.com/optical-communications

[7] Marchetti, R. et al., “Coupling strategies for silicon photonics integrated chips,” Photonics Research 7(2), 201–239 (2019). https://doi.org/10.1364/PRJ.7.000201

[8] Benedikovic, D., Cheben, P. et al., “Subwavelength index engineered surface grating coupler with sub-decibel efficiency for 220-nm silicon-on-insulator waveguides,” Optics Express 23(17), 22628–22635 (2015). https://doi.org/10.1364/OE.23.022628 — Experimental: -0.69 dB (85.3%) with metal reflector.

[9] Benedikovic, D. et al., “Sub-decibel silicon grating couplers based on L-shaped waveguides and engineered subwavelength metamaterials,” Optics Express 27(18), 26239–26250 (2019). https://doi.org/10.1364/OE.27.026239 — Simulation: -0.25 dB (~95%).

[10] Ranno, L., Sia, J. X. B. et al., “Highly efficient fiber to Si waveguide free-form coupler for foundry-scale silicon photonics,” Photonics Research 12(5), 1055–1066 (2024). https://doi.org/10.1364/PRJ.514999

[11] Billah, M. R. et al., “Hybrid integration of silicon photonics circuits and InP lasers by photonic wire bonding,” Optica 5(8), 876–883 (2018). https://doi.org/10.1364/OPTICA.5.000876 — 0.7 dB insertion loss, ~0.8 Tbit/s demonstration. Juodkazis, S., Light: Science & Applications 9, 72 (2020). Lindenmann, N. et al., Optics Express 20, 17667–17677 (2012) — First PWB concept demonstration.

[12] Richards, C. A. et al., “Low loss fiber-coupled volumetric interconnects fabricated via direct laser writing,” Optica 11(7), 995 (2024). https://doi.org/10.1364/OPTICA.524899 — SCRIBE technique, 2.14 dB insertion loss (fiber-PIC-fiber).

[13] Minkenberg, C. et al., “Co-packaged datacenter optics: Opportunities and challenges,” IET Optoelectronics 15(2), 77–91 (2021). https://doi.org/10.1049/ote2.12020 — Figure 6: CPO roadmap. Low journal IF but 150+ citations as a widely referenced CPO evolution framework.

[14] Winzer, P. (CTO, Nubis Communications), “Resolving Operational Barriers to AI Scale Up with Co-Packaged Copper Optics Sockets,” OCP Global Summit 2025.

— 2D optical array + surface grating coupling optical engine architecture.

[15] Marvell Technology / ServeTheHome, “Marvell TX9190 Liquid-Cooled CPO Switch at OCP 2025” (November 2025). https://www.servethehome.com/marvell-tx9190-liquid-cooled-cpo-switch-at-ocp-2025/ — 51.2 Tbps liquid-cooled CPO switch reference design, co-developed with Jabil. Figure 1-c source.

[16] Nagarajan, R. et al., “2.5D Heterogeneous Integration for Silicon Photonics Engines in Optical Transceivers,” IEEE Journal of Selected Topics in Quantum Electronics 29(3), 8200209 (2023). https://doi.org/10.1109/JSTQE.2022.3214418 — Passively aligned fiber array assembly for 2.5D SiPh engine. Figure 1-c bottom inset source.

1. Introduction: The Announcement and the Market’s Reaction

In early March 2026, NVIDIA announced a strategic partnership involving a combined $4 billion investment — $2 billion each — in two global leaders in photonics: Coherent Corp. and Lumentum Holdings. This was far more than a passive equity stake. The deal directly funds R&D and domestic U.S. manufacturing expansion at both companies, and includes multi-year commitments to purchase optical components at scale.

The Market’s Immediate Reaction

On the Broadcom earnings call, CEO Hock Tan said:

““We can do it with copper, and we can push the envelope from 100G to 200G to even 400,” Tan added. “We have SerDes now running 400G that can drive distance on a rack to run copper. What all I’m trying to say is you don’t need to go run into some bright shiny objects called CPOs, even as we are the lead in CPOs. CPOs will come in its time, not this year, maybe not next year, but in its time.”

The market immediately framed this as a battle: who’s right? Is the age of optics here, or can copper hold on longer? But that framing was completely wrong. Both companies were right — they were just solving different problems. The market missed this crucial distinction entirely.

2. Start with the Physics: Why the “Copper Cliff” Is Real

For decades, copper cables handled communication inside data centers. They were cheap, simple, and perfectly adequate at smaller scales. But the AI era broke that equation. Physics stepped in and said no.

When you push electrical signals through copper, the signal degrades as distance and frequency increase — a consequence of the skin effect and dielectric loss. Combating this degradation requires amplification, and amplification burns power exponentially.

According to Marvell’s data, the effective transmission distance of copper wire collapses as speeds increase:

In an environment where AI racks consume 120–130 kW of power, a communications layer that alone eats through 10% or more of that budget is simply not acceptable. Fiber, by contrast, has almost no distance constraints. It supports 10 km+ transmission, is immune to electromagnetic interference, and draws minimal power.

In an AI factory, optics are not a choice — they are a physical inevitability.

3. Broadcom vs. NVIDIA: Both Are Right. The Market Was Wrong.

What Hock Tan Actually Said

Hock Tan was not wrong. He said copper would continue to handle the 2–3 meter connections inside the rack. At that range, 400G SerDes is impressive technology — cheaper and simpler than optics. CPO is still complex, expensive, and unproven at volume. Within the 2026–2027 timeframe, Hock Tan is 100% correct.

What Jensen Huang Is Looking At

Jensen wasn’t wrong either. He’s just solving a different problem. Connecting 576 GPUs in a Rubin Ultra cluster requires linking hundreds of racks together. At 10 meters, 50 meters, or 100 meters, copper is physically out of the picture. Within the 2028–2030 timeframe, Jensen’s direction is 100% correct.

Key Insight: The market mistook Broadcom and NVIDIA as giving opposite answers to the same question. Hock Tan was talking about within-rack distances (0–2 m) in 2026–2027. Jensen was looking at cross-cluster distances (10–100 m+) in 2028–2030. This isn’t a contradiction — it’s two different conversations on two different axes of time and distance.

The Distance × Time Matrix

The Larger the Cluster, the More Optics Dominates

4. Why Is NVIDIA Betting $4 Billion Right Now?

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